22FDX TM Enabling IoT Growth. Tim Dry, (for Jamie Schaeffer, Ph.D). Leading Edge Product Line Management GLOBALFOUNDRIES
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1 22FDX TM Enabling IoT Growth Tim Dry, (for Jamie Schaeffer, Ph.D). Leading Edge Product Line Management GLOBALFOUNDRIES
2 The First Truly Global Foundry East Fishkill, New York Malta, New York Burlington, Vermont Dresden, Germany Singapore 5 Manufacturing Centers on 3 Continents 2
3 Company Highlights REVENUE MORE THAN ~6B* 25,000 2nd Largest Foundry Patents & Applications 250 Customers 18,000 Employees FAB LOCATIONS FAB CAPACITY Burlington East Fishkill Malta Dresden 300mm 200mm Singapore Trusted Foundry 200K Wafers/Mo 133K Wafers/Mo *Based upon analysts estimates 3
4 What Will it Take to Make IoT Take Off? Typical IoT Edge Node Chipset Power Cost Integration Security Today: 20+ components on MCM/PCB Future IoT Edge Nodes GLOBALFOUNDRIES 4
5 IoT Edge Nodes 2015 Specification Low-End Low MCU, Analog Mid-Range Mid/High-end MCU High-End MPU Examples Smart lighting, Building sensors Smart meters, Health and fitness monitors Smart glasses, Smart Watches Primary Requirements Cost Power Power Performance Cost Performance Power Cost Processing Requirements Low end <24MHz e.g. 8 bit, ARM CM0, ARC APEX Mid end <240MHz e.g. 16/32bit ARM CM0, 4F, 7, MIPs, ARC High end <1.5Ghz e.g. 32/64bit ARM CM A7, MIPS, HMI/Image processing Memory OTP/MTP/eNVM/SRAM <128Kbyte Flash envm 128K to 4MByte Flash External NOR, NAND Flash and DDR Memory Connectivity /Thread/ BT Smart/ <1GHz /ZigBee / BT Smart/<1GHz 3G/4G/LTE, WiFi / BT / (Off-chip 2015) Power Active: 50uA/MHz Sleep: 1uA (tbc) Stop: 10nA (tbc) Active: 350uA/MHz (CPU) Sleep: 10uA Stop: 300nA Battery life years Smoke detector Gas Meter 10years Wristband 3 days Active: 500uA/MHz Sleep: 100uA Stop: 500nA Smart watch 4 days GLOBALFOUNDRIES Confidential 5
6 IoT Edge Nodes 2015 Specification Low-End Low MCU, Analog Mid-Range Mid/High-end MCU High-End MPU Examples Smart lighting, Building sensors Smart meters, Health and fitness monitors Smart glasses, Smart Watches Primary Requirements Cost Power Power Performance Cost Performance Power Cost Processing Requirements Low end <24MHz e.g. 8 bit, ARM CM0, ARC APEX Mid end <240MHz e.g. 16/32bit ARM CM0, 4F, 7, MIPs, ARC High end <1.5Ghz e.g. 32/64bit ARM CM A7, MIPS, HMI/Image processing Memory OTP/MTP/eNVM/SRAM <128Kbyte Flash envm 128K to 4MByte Flash External NOR, NAND Flash and DDR Memory Connectivity /Thread/ BT Smart/ <1GHz /ZigBee / BT Smart/<1GHz 3G/4G/LTE, WiFi / BT / (Off-chip 2015) Power Active: 50uA/MHz Sleep: 1uA (tbc) Stop: 10nA (tbc) Active: 350uA/MHz (CPU) Sleep: 10uA Stop: 300nA Battery life years Smoke detector Gas Meter 10years Wristband 3 days Active: 500uA/MHz Sleep: 100uA Stop: 500nA Smart watch 4 days GLOBALFOUNDRIES Confidential 6
7 IoT Edge Nodes 2015 Specification Low-End Low MCU, Analog Mid-Range Mid/High-end MCU High-End MPU Examples Smart lighting, Building sensors Smart meters, Health and fitness monitors Smart glasses, Smart Watches Primary Requirements Cost Power Power Performance Cost Performance Power Cost Processing Requirements Low end <24MHz e.g. 8 bit, ARM CM0, ARC APEX Mid end <240MHz e.g. 16/32bit ARM CM0, 4F, 7, MIPs, ARC High end <1.5Ghz e.g. 32/64bit ARM CM A7, MIPS, HMI/Image processing Memory OTP/MTP/eNVM/SRAM <128Kbyte Flash envm 128K to 4MByte Flash External NOR, NAND Flash and DDR Memory Connectivity /Thread/ BT Smart/ <1GHz /ZigBee / BT Smart/<1GHz 3G/4G/LTE, WiFi / BT / (Off-chip 2015) Power Active: 50uA/MHz Sleep: 1uA (tbc) Stop: 10nA (tbc) Active: 350uA/MHz (CPU) Sleep: 10uA Stop: 300nA Battery life years Smoke detector Gas Meter 10years Wristband 3 days Active: 500uA/MHz Sleep: 100uA Stop: 500nA Smart watch 4 days GLOBALFOUNDRIES Confidential 7
8 Connected Edge Node MCU + RF Mid/High End Big Little: Big: M4F/7F Little: M0+ On Chip Oscillator Fast wake Clock trees On chip Power supplies to Power Islands. In conjunction with NoC and clocks Sensor hub with always listening sensor interface that runs at low power while rest of system asleep, and wakes up system on correct events CM0+ Peripherals, GPIO Clocks, OCO Power modes PMIC [DC-DC, LDOs] Power Islands Network-on-Chip (NOC) Always listening CM4/7F Peripherals, GPIO Sensor Hub Multi-Standard Radio(s) BT Smart, envm, MTP Density, speed, reliability, duration LV SRAM Customer Own IP HMI: Audio Touch Display Color TFT LCD Security Authorization, Crypto, Unique ID, Key gen and vault, Enabling Low power November 14, 2015 FIFO PHY Low Voltage SRAM. Low leakage Retention area/ NoC Reduced Total System power allows more power for Transmit and Receive, enabling better Link budget and robust communications
9 Total System Power Active and Standby HW accelerators, intelligent peripherals, offload engines and sensor hubs Fast wake up OCO Faster process time Reduce Vdd Power modes Retain SRAM Low leakage memories Reduce static power Reduce RF power 6/11/2015 Tim Dry 9
10 Varying Requirements of IoT Edge Nodes Duty Cycle High Standby: 5% Active: 95% High Wireless Smart Meters Wildlife Camera Edge Gateways High-end Wearables 28nm Super low power High Performance Low Dynamic Power Processing Performance Low Smart Lighting Building Sensors Home Automation 55, 40, 28nm Ultra low power Low-end Wearables Drones, Robotics, 3D Printing Health and Fitness Monitors IP Security Cameras Trackers (Asset, People..) Active: 17% 55nm, 40nm Ultra low leakage High Duty Cycle Low Static Power Standby: 83% Sleepy Duty Cycle Chatty Duty Cycle Low GLOBALFOUNDRIES Confidential 10
11 Introducing 22FDX Platform Industry s first 22nm fully-depleted silicon-on-insulator (FD-SOI) technology Delivers FinFET-like performance and power-efficiency at 28nm cost Ultra-lower power consumption with 0.4 volt operation Software-controlled transistor bodybiasing for flexible trade-off between performance and power Integrated RF for reduced system cost and back-gate feature to reduce RF power up to ~50% Enables applications across mobile, IoT and RF markets Fully Depleted Channel for Low Leakage Ultra-thin Buried Oxide Insulator FD-SOI Planar process similar to bulk 70% lower power than 28HKMG 20% smaller die than 28nm bulk planar 20% lower die cost than 16/14nm GLOBALFOUNDRIES 11
12 Body-Biasing Provides Greatest Design Flexibility Forward BB (FBB) enables low voltage operation down to 0.4v without speed loss Reverse BB (RBB) enables low leakage down to 1pA/micron Dynamic body biasing enables active tradeoff of performance vs. power Improve within die or die-to-die uniformity Post-Silicon Tuning/Trimming -2V to +2V Body-Biasing GLOBALFOUNDRIES Confidential 12
13 Body-Biasing Enables Power/Performance Trade-off Leakage Power Maximum Performance Operating Mode Forward Body Bias (FBB) Reverse Body Bias (RBB) Minimum Leakage In Standby Mode Max Frequency GLOBALFOUNDRIES Confidential 13
14 Body-Bias Provides a New Dimension to Optimize for Power and Performance 100 Relative Leakage Power Best perf./watt 1x F max Vdd-100mV Lowest total power 0.5x Fmax mV Vt Rev Body-Bias -60mV Vt Fwd Body-Bias No BB 1x F max Vdd+100mV Best performance 1.6x F max Relative Active Power
15 22FDX Benefits RF Applications RF/Analog designers use Gate Length (Lg) greater than Lg (min) to improve matching and gain. FD device gives higher self gain than bulk at the same Lg FD enables shorter (20nm) Lg that increases gm and f T performance HKMG enables low Tinv and high channel charge Planar structure allows for lower Rsd and Rg compared to Finfet Local Back Gate bias give dynamic control of threshold voltage for innovative circuits SOI structure allows more flexible layout reducing overall parasitism at larger pitch The plot indicates that 22FDX has superior self gain and higher f T than 28nm bulk at larger Lg from nm. (For a Gm/I =15, a moderate inversion) GLOBALFOUNDRIES Confidential 15
16 RF Circuit Benefits for 22FDX Reverse-back-gate biasing optimizes gain efficiency while maintaining dynamic range Conventional approach (non IMG) Approach w/ IMG 22FDX is an Independent-Multi-Gate (IMG) Technology Back-gate utilized to optimize bias current and transconductance Free up front-gate voltage for signal path dynamic range Eliminate bias circuitry losses of single-gate technologies such as bulk and FinFET GLOBALFOUNDRIES Confidential 16
17 22FDX Base Platform and Extensions 22FDX Base Platform 4 Core Vts (FBB & RBB) 2 IO 1.2/1.5/1.8v Passives SRAMs (HD, HC, LV, ULV, TP) 8T/12T libraries IP solutions for IoT, Mobile, and RF Software controlled Fwd/ Rev body-bias Base platform PDK & IP -ulp adds logic libraries and memory compiler optimized for 0.4v logic operation -ull adds devices, libraries, and memory compilers to achieve 1pA/um leakage -uhp adds optimized BEOL stacks, 12T libraries optimized at OD, high-speed SERDES (16/28GHz), and MIM capacitor -rfa adds RF enablement, BEOL passives, and IP for BTLE, WiFi Application-optimized extensions GLOBALFOUNDRIES Confidential 17
18 22FDX TM Offers 3 Types of Transistors, Optimized for Performance vs. Power SLVT/LVT Lowest V T Optimized for FBB Highest performance ULL Adds triple gate oxide layer Longer gate length Coupled with RBB achieves 1pA/um leakage Relative Fmax RVT/HVT Mid-range V T Optimized for RBB Balance of low leakage and high performance GLOBALFOUNDRIES Confidential 18
19 22FDX Provides FinFET-like Power Efficiency Forward Body-Bias (FBB) Extends FD-SOI Flexibility Freq. (normalized) 1.80 Frequency vs. Total Power % Faster 50% Less Power 22FDX 50% lower power at same frequency 40% faster performance at same power % Faster 50% Less Power 28HKMG Same performance at lower Vdd FBB Advantage: Software-controlled body-bias enables dynamic tradeoffs between power, performance and leakage RO-Based Metric: INV2, NAND2x1, NOR2x1, NAND3x1 (each one has its own RO) Wire load is added in each stage of RO (FO = 3) Delay / Iddq is estimated by taking weighted average of 4 ROs Delay/Iddq metric = (0.4*INV+0.2*NAND2+0.2*NOR2+0.2*NAND3) Iddq / Delay is tt, 25C 70% dynamic and 30% Static Power for Total Power estimation. Total Power (normalized) GLOBALFOUNDRIES 19
20 IoT Example: Remote Security Camera Application Optimize Standby and Dynamic Power Integrated RF FBB for lowest dynamic power Wakes up comms to transmit message Wireless Comms High Performance Application Processor Wakes up Image Processor to zoom in and analyze potential threat Watchdog Processor RBB for lowest leakage Detects motion 22FDX die 22FDX Delivers: 10x lower static power w/ Reverse body-bias Up to 92% lower active power with forward body-bias RF integration for reduced BOM cost and 50% lower power GLOBALFOUNDRIES Confidential 20
21 FDSOI Case Study Smart Watch Next Generation Device Specification CPU Freq GHz Vdd 0.6v SRAM up to 16Mb -25C to +85C Integration Path: BLE, WiFi, PMIC Ingenic 40nm Device today Smart Watch User Case 40LP 28SLP FinFet FD FD+FBB FD+FBB +BLE ISO Freq ISO power mw/day (active and static) Battery Life (Days) Battery Life ISO FD+FBB +BLE+WiFi Battery life increases from 4.5 to 14+ days. GLOBALFOUNDRIES 21
22 22FDX Lower Power on ARM M % power reduction -85% area reduction % power reduction -40% area reduction T-1.2v 9T-1.1v 9T-1.0v 8T-0.8v 0.14 Dynamic Power Std Cell Area GF55LP GF40LP GF28SLP 22FDX Source: VeriSilicon Timing signoff 100MHz under SS corner Leakage/Dynamic typical corner 25C Zero body bias on 28/22FD FDSOI has significant PPA advantage over bulk on low-end M0 applications GLOBALFOUNDRIES Confidential 22
23 Varying Requirements of IoT Edge Nodes Duty Cycle High Standby: 5% Active: 95% High Wireless Smart Meters Wildlife Camera Edge Gateways High-end Wearables 28nm Super low power High Performance Low Dynamic Power Processing Performance Low Smart Lighting Building Sensors Home Automation 55, 40, 28nm Ultra low power Low-end Wearables Drones, Robotics, 3D Printing Health and Fitness Monitors IP Security Cameras Trackers (Asset, People..) Active: 17% 55nm, 40nm Ultra low leakage High Duty Cycle Low Static Power Standby: 83% Sleepy Duty Cycle Chatty Duty Cycle Low GLOBALFOUNDRIES Confidential 23
24 Easy Design Migration from Bulk to 22FDX 22FDX Digital Design Flow Design Planning (FBB vs RBB) Library Char + POCV/ LVF variability RTL Synthesis Cell placement + Tapcell Placement + CTS pre-route Routing Optimization UPF Connectivity Leakage recovery w/ Vt swapping + Lgate optimization Sign-Off PEX/STA (+DPT extraction) Physical Verification + EMIR Lib char with BB (Added corners) Implant-aware + CNRX Placement Tapcell connections (BB mesh + HV rules) Optional: use FBB/RBB performance/power optimization Optional: Add sign-off corners for dynamic BB variables (PVTB) Digital Design Flow is similar to bulk digital design flow The differences are taken care of in our Reference Flow releases Reference flow is test-chip proven and available today Test Chip Proven In-Design Modules (DRC + PM + MetalFill + EMIR) Bulk Flow New Step for 22FDX GLOBALFOUNDRIES 24
25 22FDX has lower process complexity and faster cycle times than FinFET technology Process Complexity (a.u.) 28Poly/SiON 22FDX FinFET Far_BEOL BEOL MOL RMG Post_Gate Gate Wells Active Fin 22FDX has 50% fewer immersion lithography steps than FinFET Fewer Well and Post-Gate process steps than 28nm Poly/SiON Avoids complex Fin, Post-gate, RMG, MOL, and BEOL integration in FinFET GLOBALFOUNDRIES Confidential 25
26 22FDX Ecosystem Expanding Design Services EDA IP Industry Groups Supply Chain GLOBALFOUNDRIES Confidential 26
27 Summary Industry's first 22nm FD-SOI platform Enables FinFET-like performance and power efficiency at 28nm cost Provides design flexibility and intelligent control Optimized for Mobile, Consumer, IoT and RF GLOBALFOUNDRIES 27
28 Thank-you Learn more at GLOBALFOUNDRIES.com 2013 GLOBALFOUNDRIES Inc. All rights reserved.
Ramya Srinivasan GLOBALFOUNDRIES 22FDX: Tempus Body-Bias Interpolation QoR. April
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