Alberto Scandurra Microcontrollers, Memories and Secure microcontrollers Microcontrollers Division Senior Member of Technical Staff

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1 1. Sistemi di comunicazione per SoC per applicazioni Consumer 2. Interconnessioni ottiche on-chip 3. Gestione di Power, Reset e Clock in microcontrollori Alberto Scandurra Microcontrollers, Memories and Secure microcontrollers Microcontrollers Division Senior Member of Technical Staff

2 Sistemi di comunicazione per SoC per applicazioni Consumer

3 Systems on Chip Past and present SoCs Different classes of traffic CPUs require very low latency and high bandwidth Real-time processing require high bandwidth DMAs (background processes) use residual bandwidth Bottleneck is external memory (SDRAM, DDR, ) Finite bandwidth Limited efficiency Initiators (processors, real time blocks, DMAs) External fast memories On-chip communication system Slow memories Peripherals

4 Systems on Chip HD - Set Top Box DDRs CTRL: 400MHz STNoC: 400 MHz IP & STBus: up to 200 MHz IP & STBus: 100 MHz

5 Systems on Chip STBus Initiator IFs ST231+ST STAC INIT STAC IF AXI Master IFs A9+ GPU COMPO DMU0 DMU1 BDISP VID DISP DISPRW STNoC Subsystem PERIPH_HP0 PERIPH_LP0 PERIPH_HP1 PERIPH_LP1 LMI0 LP LMI1 LP LMI0 HP STBus Target IFs LMI1 HP TRANSP DMA???? STBus Target IFs STAC TARG STBus Initiator IFs STAC IF

6 Systems on Chip Future SoCs => MPSoCs Greater IP computation capability, leading to greater bandwidth requirement Small gate delay in comparison to wire delay Nanometer effects (leakage, variability, ) The bottleneck will be the interconnect

7 Microcontroller

8 Microcontroller

9 STBus/STNoC STBus Specification UN0484 User manual STBus Application STBus complex interconnect design and verification for a HDTV SoC STNoC Application An HDTV SoC based on a mixed circuit-switched/noc interconnect architecture (STBus/VSTNoC)

10 The SoC interconnect problem Many digital and analog blocks Analog blocks do not scale as much as digital blocks Analog blocks are big and have a lot of pads, also big themselves Systems are pad limited, i.e. analog blocks pads limit the available room for digital blocks Uncompatible power supply voltages and oxide thickness (1.5V, 30A for DDR3, >1.5V, 50 for HDMI)

11 System in Package concept Tx Rx OCN Tx Rx Die #1 Tx Rx OCN Tx Rx Die #2 A SiP consists of a number of dice interconnected A possible structure consists of dice laying on the same plane OCN OCN Die #3 Die #4

12 System in Package concept Die 1 Tx Rx OCN Rx OCN Tx OCN Die #1 Die #2 A NiP consists of a number of dice interconnected A possible structure consists of dice laying on the same plane An alternative structure consists of dice stacked on each other (most common) Tx Rx Die #3

13 System in Package concept Die 1 Tx OCN OCN Rx Die #1 Communication between different dice happens through the dedicated interface module Rx Tx Die #2 OCN Tx Rx Die #3

14 System in Package concept Die 1 Tx OCN OCN Rx Die #1 Communication between different dice happens through the dedicated interface module Rx Tx Die #2 OCN Tx Rx Die #3

15 System in Package concept Die 1 Tx OCN OCN Rx Die #1 Communication between different dice happens through the dedicated interface module Rx Tx Die #2 OCN Tx Rx Die #3

16 On-Chip Optical Interconnect

17 The SoC interconnect problem CMOS chip IP Interface Routing Node PROBLEM: routing issues and congestion

18 Interconnect SoC bandwidth requirements increasing (blue curve) Metal wire capacity insufficient from 65nm technology (red curve) Optical interconnect capacity (SOI waveguides, green curve, photonic crystals, violet curve) able to satisfy SoC bandwidth requirements

19 Interconnect SoC bandwidth requirements increasing (circles) Metal wire capacity always sufficient (rombs) SOI Optical interconnect capacity (triangles) slightly sufficient Polymer Optical interconnect capacity (squares) not sufficient

20 Interconnect SoC bandwidth requirements increasing (circles) Metal wire capacity always sufficient (rombs) SOI Optical interconnect capacity (triangles) slightly sufficient Polymer Optical interconnect capacity (squares) not sufficient DWM technique is required to increase OI bandwidth

21 Photonics based solutions On-chip optical interconnect WADIMOS european project III-V emitters/detectors SOI waveguides DWM-based routing Off-chip optical interconnect NAVOLCHI european project Based on plasmonics Overcoming diffraction limit 100 times smaller devices Much lower power consumption

22 Above CMOS chip photonic layer CMOS chip Network Interface Optical Tx/Rx Optical waveguide Routing issues and congestion no longer exist l router Photonic chip

23 Above CMOS chip photonic layer

24 WADIMOS : the objective

25 Optical NoC architecture IP block Optical wavelength router Multiple wavelength optical data communication Electrical data communication Optical NoC interface

26 initiator NI l-router waveguide Transmitter circuit clk 2 (f 2 =n b *f 1 ) n b -bits flit 1-bit flit Driver nl Laser nl Serializer Demux Driver 3 Laser 3 Driver 2 Laser 2 Driver 1 Laser 1 Address Decoder Digital Analog Optoelectronic

27 Transmitter circuit : LASER driver Drive current pulse Drive current pulse V dd i mod V d I bias The LASER has to be biased at or just above threshold in order to speed up the 0 to 1 switching 0 : almost no light 1 : light

28 initiator Optical router Passive filters Scalable architecture (limited by lithographical precision) Wavelength multiplexing Circuit switching (address coded by wavelength) No contention Requires high-speed optoelectronic interface circuits target l 2 l 3 l 1 l 4 2 l 3 l 4 l 2 l 1 3 l 1 l 2 l 4 l 3 4 l 4 l 1 l 3 l 2 I1 I2 I3 I4 l 1 l 1 l 2 4µm l 3 l 3 l 4 T1 T2 T3 T4 microdisk of resonant wavelength l n l n depends on: - geometry (radius) - material parameters (optical indices) SiO 2 Si l = l n l l n

29 l-router demultiplexer target NI Receiver circuit clk 2 (f 2 =n b *f 1 ) 1-bit flit clk 1 (f 1 ) n b -bits flit detector nl receiver nl deserializer nl + buffer detector 3 receiver 3 deserializer detector 3 2 receiver 2 deserializer + buffer detector 1 receiver 2 1 deserializer 1 + buffer + buffer Digital Analog Optoelectronic

30 Receiver circuit D D demultiplexing microdisk array... l 2 r 2 l 4 r 4 l 1 r 1 l 3... r 3 D D broadband photodetectors

31 Receiver circuit R f i in A C d v ref

32 Gestione di Power, Reset e Clock in microcontrollori

33 Microcontroller

34 Start-up and reset strategy When a microcontroller is powered up, the power supply voltage traverses voltage ranges where the device is not guaranteed to operate, before reaching its final stage Some modules can start operating at voltage levels lower than other modules on the same chip In order to guarantee that the chip starts up in a known state it must contain a power-up circuit (power up/power down reset) The same circuits are required to guarantee a safe behavior when the chip wakes up from low power modes, in particular when some modules are shut-off for eliminating completely power consumption (including leakage) Power supply noise can lower the voltage level to such a value that circuits can t work safely; a dedicated logic is required to protect such circuits (brownout reset)

35 Reset strategy In a VLSI device the Power-On Reset (POR) is a module that detects the power applied to the chip and generates a reset pulse reaching the entire circuit and ensuring it starts operating in a known state An Oscillator Start-up Timer (OST) is a module used to keep the reset signal active until the crystal oscillator is stable

36 Reset strategy A Low Voltage Detector (LVD) is a peripheral generating a reset signal when the power supply voltage Vcc falls below a reference value Vref Sometimes it is combined with POR and it s called POR-LVD A Programmable Voltage Detector (PVD) generates an interrupt when the voltage goes below the selected threshold (7 different thresholds are available in STM32)

37 Reset strategy Brown Out Reset (BOR) is a reset signal generated when the power supply voltage falls below a certain value such that the chip wouldn t work reliably anymore STM32 BOR circuit keeps the device under reset until the supply voltage reaches the specified VBOR threshold (5 programmable VBOR thresholds can be selected) When the supply voltage drops below the selected threshold, a device reset is generated

38 Reset strategy A bandgap voltage reference is a temperature independent voltage reference circuit producing a constant voltage irrespective of power supply variations, temperature changes and loading on the device It generates an output voltage around 1.25 V, close to the theoretical 1.22 ev bandgap of Si at 0 K

39 Reset strategy A Watchdog Timer (WDT) is a timer used to detect and recover from circuit malfunctions. Corrective actions typically include placing the chip in a safe state and restoring normal system operation

40 Typical MCU operation modes Run Sleep or Standby High frequency clock oscillators remain running, but CPU clock tree is disabled Deep sleep Stop MCU critical elements (i.e. RTC) are active, high frequency system clocks and other non-essential loads are disabled Both high and low frequency oscillators are disabled, the state of the MCU pointer and configuration registers is preserved Off or Shutoff The MCU is completely powered down but is in a near-death state ensuring the minimum functionality needed to trigger wake-up from external stimuli

41 Typical MCU operation modes Consumption and wake-up times Run? Sleep or Standby 200 ua, >= 1 clock cycle Deep sleep ua, 5-8 us Stop ua, 5-8 us Off or Shutoff 1.5 ua, >= 160 us

42 Power Control scenario Context ULP MCU target is maximize battery life cycle by reducing overall system power consumption, ensuring the high performance required for computational tasks Typical LP applications spend most of the time in sleep/deep sleep mode waiting for external events or interrupts to wake-up Problems P = VDD x IDD be reduced through Dynamic Voltage Scaling, IDD can be reduced lowering system frequency sineduced a) keeping the system in sleep modes as long as possible, b) waking up MCU for the shortest required time, c) gating clocks of unused peripherals During wakeup the system resumes as if reset, and requires time to re-configure the system Metrics ma/mhz, ma/dmips, DMIPS/MHz

43 State of the art: programmable LDO VR

44 Power consumption estimation

45 Power consumption estimation

46 Wake-up energy

47 Low power analog peripherals