Hello and welcome to this Renesas Interactive Course that provides an overview of the timers found on RL78 MCUs.

Transcription

1 Hello and welcome to this Renesas Interactive Course that provides an overview of the timers found on RL78 MCUs. 1

2 The purpose of this course is to provide an introduction to the RL78 timer Architecture. Our objectives are to learn about the RL78 timers' structure and capabilities, Including the Timer Array Unit, the real time counter, interval timer, watchdog timer, as well as the PCL buzzer output 2

3 First, we ll discuss the RL78s timer array unit, or TAU. 3

4 The Timer Array Unit, also called TAU, is a peripheral module containing several timer channels. The largest of these units contains up to 8 timer channels and each channel is a 16 bit timer. Therefore it s important to distinguish between the channels and the unit. Where a channel is more or less one independent timer within a unit, a unit can have up to 8 channels. These 8 channels operate independently but can be combined together. There are several operation modes available in the Timer Array Unit and these can be independent or combined modes. In independent modes only one channel of the timer unit is used, and we have the following available modes: The interval timer is a simple mode which generates an interrupt at a fixed interval. The square wave output mode is almost identical to the interval timer mode except that the port output is enabled. External event count mode is not an output, but instead an input is connected to the timer and we can count external events using the rising, or falling, or even both edges. In Divider operation the frequency of an input signal can be divided down using one of the timer channels. Input pulse interval measurement or capture mode can measure the time between two rising or two falling edges. And the last one is the input high/low level width in this case it s almost the same as interval measurement but here we can measure the pulse width from high to 4

5 low level or vice-versa. 4

6 Now to the combined operation modes; in these modes at least two of the channels of one timer array unit are used together or combined. The simplest mode of these combined operation modes is the PWM output mode. In PWM mode, one channel of the TAU is used in master mode, it determines the period of the PWM signal. And the second channel - called slave mode - is used to determine the duty cycle of the PWM signal. Another combined operation mode is the one shot pulse mode. In this mode it s possible to output a pulse on a pin with a selectable delay pulsle width, this means the pulse will be output after a specific delay, selectable by the master. The last combined mode is where not just two channels of the TAU but even more channels can be connected together; this is the multiple PWM output mode. In this case one master is used to select the period of all the PWM signals and each channel is able to generate a different PWM with a specific duty cycle. All the PWMs in multiple PWM mode run completely synchronously because the trigger of the master is used to start all of the slave channels. A special timer function is used for LIN-bus support and this only uses channel 7 of the TAU0. It can be used to detect a Wake-up signal and a Sync Break Field in the in the LIN protocol and thus measure the pulse width of the sync field. All this is supported in hardware, with the receive pin of the UART directly connected to the 5

7 timer input of the Timer Array Unit. 5

8 Here is the block diagram of the Timer Array Unit with the three major blocks. The first one is the Timer Clock Selection block; this is the common block at the top of the Timer Array Unit. Here the entire Timer Array Unit can be switched on by the TAU enable bit to provide the peripheral with a valid clock signal. To reduce power consumption this flag can also switch off the entire Timer Array Unit. Next is the global pre-scalar, for the entire TAU array unit, where four different sub-clocks can be selected for the TAU channels. There are also additional control registers in the global timer clock selection block containing flags which start and stop each timer channel of the TAU. The second logic block is used for clock monitoring. It s a very simple block connected between the internal low speed oscillator or internal sub oscillator and channel 5 s timer input. Internal logic allows monitoring of the device s clocks, which is a requirement of IEC regulations. Using this logic it s easily possible to check the main system clock frequency by comparing it to another available clock signal which is completely independent of the main system clock. The third block contains the 8 channels themselves. Each channel is completely independent, however only even channels can be selected as master channels and the odd channels can operate as slave channels. Typically each channel has an input, an output and a dedicated control register to set up how the channel should 6

9 operate, for example as an interval timer or in PWM slave mode. 6

10 Here are the basic rules for using the combined operating modes. This is an example of how the Timer Array Unit can be split for a certain application. In this application channel zero is used as PWM master and channels one and two are used as slaves, thus by using these three channels 0-2 in PWM mode, two outputs can be generated. Both outputs are completely independent but the period is the same for both, because both PWM s are using the same master. Channel three is setup here for single operation as an interval timer. And channels four and five are again used together for PWM, and this PWM is completely independent from the channel zero PWM. Channels six and seven are again used as independent channels. In this example the channel zero master is using the input clock CK00, which could be the direct system clock (Fx) maybe at 32 or even 24MHz, and CK01 which might be a much slower clock, like the main system clock Fx divided by 8 or by 16. This provides the flexibility to select the input clocks independently for each channel. 7

11 This slide shows a block diagram of a single channel. In the TAU up to 8 of these single channels are available. There is a selector in the input path which determines the input clock to be used; in this case we can choose between input signals CK00 or CK01. On other channels it s possible to select from a maximum of four clocks, and the selected clock will be used internally inside the channel. Next is the timer counter register TCR and the compare register TDR both of which are 16 bit wide. Depending on the mode, a match between these registers or an underflow will directly affect the output controller of each timer channel to generate a square wave output, or to simply generate an internal interrupt -one of which is available for each timer channel. On the other side of the input path is the timer input pin with an edge detection circuit inside. Because of the synchronous design of the whole Timer Array Unit, you always need an internal clock signal f MCK to count external pulses or to do pulse width measurement from the input pin TI0n. The TMR register at the bottom of the block diagram is the timer s mode register. Here you can select which input clock is used, whether the channel should work as a master or as a slave, additional mode settings such as interval or PWM mode, and settings for switching the output on or off, and so on. You can also see all the connections to the slave master controller - at the top of the block diagram - to the 8

12 other channels, which are needed for combined operation mode. 8

13 Here is an example of Interval Timer Mode, where the interrupt of the timer INTTM0n is generated at a preset interval set by the TDR register. The interrupt interval can be calculated by multiplying the period of the input count clock by the value set in the TDR register plus one. 9

14 In this timing diagram you can see the functionality of the timer in Interval Timer Mode. After setting up the timer and starting it with the timer enable bit and the timer start trigger, the TCR register is pre-loaded with the value written to the TCR register. In Interval Timer mode shown here, the TR register is counting down and if an underflow occurs or zero is reached then an interrupt is generated, and the output is toggled - if enabled. Note the interval time is determined by the value of the TDR register plus one. Additionally there are shadow registers for each TDR register, so that the value of the TDR register can be re-written independently of the state of the internal timer. The next time the timer underflows, the new value will be written to the real TDR register automatically. 10

15 With this simple example code you can see which registers need to be setup to enable the TAU. It s actually very simple; first the peripheral zero register PER0 must be set. A specific flag in this register enables the power to the Timer Array Unit, and the clock is supplied to the unit. Clock frequencies are selected in the global clock selection circuit of each TAU unit via the TPS0 register. In this case f CLK /2 is being set for both paths. Then we have to select the mode for each channel, and here only channel zero is used and it is selected by the TMR00 register. Next the Timer Zero Compare register TDR0 must be initialized, and finally after all the settings are done, TS0 bit zero is set to start the timer count operation. 11

16 Now let s look at a combined timer, in this example PWM mode, where at least two channels operate together, with one master and one slave. The master defines the interval time and so the period of the PWM signal, and the slave operates in onecount mode to output the PWM duty cycle. The pulse period and the duty factor can be calculated as follows; the period is the master channel compare register TDR0 value plus one, multiplied by the count clock. And the duty factor is the value written to the slave compare register, divided by the value of the master register plus one. On the next slide you can see the timing diagram of how this works. 12

17 Here is a block diagram of the PWM mode; at the top is the master channel responsible for the period of the PWM cycle, and at the bottom is the slave channel. Both are connected together using internal signals to trigger each other. The master channel defines the period and a complete PWM cycle will be started by triggering the master channel via the TS0n bit, starting the timer count register TCR0. The timer counter register of the slave will be started at the same time, also using the internal trigger. When the timer slave count register reaches zero, the duty is over and the output will be toggled from high to low level or vice-versa, however the master channel will still count down to zero. When the master channel reaches zero the complete period is over, and the output port is set to one again. The logic of the output port can also be inverted if necessary for your application. 13

18 In this slide you can see the operation as a timing diagram. After the master has been started the slave also starts counting automatically and both count registers start down-counting from the initial value. When the slave reaches zero the output will be toggled and an interrupt will be generated. Then the slave channel counter stops and is reloaded with the initial value again, meanwhile the count register of the master still counts down to zero. When this has also reached zero the output pin will be toggled once more. In this PWM mode we don t have to take care about timing issues when re-writing the registers for the duty cycle and the master period. Also values of 100% and 0% PWM output can be generated easily just by writing in zero or 0xff into the compare registers. 14

19 Next we ll cover the R78 s RTC, or real time counter. 15

20 The Real Time Counter has several operation modes. The main mode is Calendar Timer Mode which automatically counts year, months, weeks, days, hours, minutes and seconds up to 99 years, based on the 32 KHz sub-oscillator input signal. This counter allows the micro to be in sleep mode for several days before the core needs to be woken up. During this time the real-time operation continues in the system. Additional modes are; Constant Period Interrupt, where in addition to the calendar timer functionality, the timer is able to generate an interrupt with a fixed period from half a second to one month. Additionally an alarm interrupt function is implemented, which allows you to set up an alarm value to wake up the micro at a specific date - selectable by week, hour and minute. And finally a 1Hz pin output function is included to generate a very slow 1Hz signal on an output pin. 16

21 Here is the block diagram of the Real Time Counter. On the lower part of the slide are all the registers counting up year, month, week and so on. Each has a buffer in front to preset the data or to read out the current value. Although it is possible to read directly from the registers, writing must be done via the buffers. At the top are all of the control registers to set up the real-time counter and registers to set up the alarm time you want to wake up the controller. The real-time counter can select between the sub-system clocks; which are typically an external 32 KHz crystal or the internal low-speed oscillator, which is usually 15 KHz. There is also a Sub-Clock Count register and a preceding Watch Error Correction register which we will explain in a bit more in detail on the next slide. 17

22 The sub count register RSUBC counts the reference time for a one second interval, it counts up to 0x8000 (corresponding to khz) and then the Second Count Register will be incremented by one and so on. Since sub-oscillator crystals are not that accurate and can have a wide drift over temperature range, Renesas has implemented a Watch Error Correction feature. The watch error correction value can be set depending on the temperature, to improve accuracy of the realtime counter by offsetting the inaccuracy of the sub-system clock drift over temperature. 18

23 Next we ll explain the functionality of the Interval Timer. 19

24 There are several operation modes available for the Interval Timer. The timer itself is a very simple 12 bit timer, with a 12 bit counter and a 12 bit compare register. An interrupt is generated if both registers match. A major application for such interval timers is to enable the RL78 s low power operation. For example if you want to do a cyclic wake-up based on the internal sub-system clock, you can use the interval timer since it is running - even in Stop Mode - when the internal low speed oscillator is operating. The low speed internal oscillator together with the interval timer, enable very low power consumption down to 0.5uA during Stop Mode, but still have the capability to wake up the CPU based on the interrupt coming from the Interval Timer. The input clock for the interval timer can be either the 15 khz internal selector or the 32 khz sub-clock signal, the same as the real-time clock unit. 20

25 Finally here is the block diagram for the Interval Timer. It s a very simple timer with a 12 bit counter and a 12 bit compare register. In front of the timer is a selector to choose the sub-clock or the internal low speed oscillator clock to run the timer. Note that the control register which controls the input clock for the Interval Timer, is the same as the one which controls the input clock for the real-time clock timer. That means that both timers are always using the same time base; either the sub oscillator clock or the external 32 khz crystal or the internal 15 khz low speed oscillator. 21

26 Now for a quick look at the PCL buzzer output 22

27 Here is the PCL or buzzer output, a very simple peripheral which allows easy generation of a square wave output with fixed frequency. Once you have selected the output frequency, the output can be easily switched on or off using a single bit, by enabling or disabling the clock at the output. These clock signals can be used to drive buzzers or to provide a clock signal to external peripherals. The maximum output frequency is 10 MHz. 23

28 Finally, we ll have a look at the RL78s Watchdog timer. 24

29 The main function of this watchdog timer is to detect code runaway and generate a reset if this occurs. The watchdog is set up by the Option Byte, so there is no way to affect the behavior of the watchdog timer from the application code. The Option Byte is set by constants located in the FLASH memory. Using this option byte the watchdog timer interval can be selected and the watchdog timer can be disabled or enabled. Overflow size, or time, and window size can be selected. If the window is not selected then it operates as a standard watchdog. And as a last option we can select the window watchdog timer operation in halt or stop mode. Here it is possible to run the watchdog timer from the internal low-speed oscillator - even in stop modewhile the rest of the system is in sleep mode. This is often a requirement for security applications. To re-trigger the watchdog timer the whole WDTE register is used, by writing the magic word 0xAC to clear the watchdog timer and start counting again. 25

30 In the center of the watchdog timer block diagram is the 17bit counter, with the input fixed to the internal low speed oscillator and no other selection possible. Using the option byte you can select the window size and the time of the watchdog timer. Usually in case of a watchdog timer overflow or underflow if the window size check occurs, a system reset will be generated. As a second option the watchdog timer can also be used as an interval timer interrupt. That means if 75% of the overflow time of the watchdog timer occurs an internal interval interrupt will be generated. This can be used, for example in Stop Mode, to get a pre-warning that the watchdog timer will overflow soon and wake up the system to re trigger the watchdog timer. 26

31 This slide shows the operation of the watchdog timer using the window size - the green area which here has been defined as 50%. When the window is opened the watchdog timer can be retriggered after it has reached 50% of the overall overflow time. If the retrigger is too late, i.e. the overflow time has been reached an interrupt will be generated. Using the window function, if the retrigger comes too early - before 50% of the complete overflow time - the reset will be generated. Other operations causing a reset from the watchdog timer are; when an incorrect magic word is written to the WDTE register or attempting a bit operation on the WDTE register. 27

32 In summary, in this course, we talked about the RL78s timer units. Including the Timer Array Unit, the real time counter, interval timer, watchdog timer, as well as the PCL buzzer output. We would like to thank you for viewing this course. For more information on RL78 products, please view the RL78 Family Overview course, or visit 28

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