Hardware Flags. and the RTI system. Microcomputer Architecture and Interfacing Colorado School of Mines Professor William Hoff

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1 Hardware Flags and the RTI system 1

2 Need for hardware flag Often a microcontroller needs to test whether some event has occurred, and then take an action For example A sensor outputs a pulse when a model train approaches a crossing The MCU must sense this pulse and then lower the crossing gate sensor MCU To make sure that it doesn t miss the input pulse, the MCU must continually read the input signal very rapidly This means that it can t do anything else (e.g., sensing and controlling other gates) 2

3 Hardware flag Instead of continuously reading an input signal, it is much more efficient to have the input signal set a hardware flag (i.e., a flip-flop) Then the MCU can occasionally read the flip-flop and tell that the event occurred it doesn t have to catch the input pulse when it happens No need to rapidly poll the input V DD (ie, logic 1) D flip-flop D Q Computer tests flag Device sets flag (on rising edge of input signal) CLR Computer clears flag We assert CLR to force the flip-flop to zero (this is an asynchronous control input) 3

4 Timing for the two methods Rapidly polling input signal read signal detect signal time n input set? y output control signal Occasionally polling hardware flag flag set? y n do other useful things read flag detect flag time output control signal clear flag 4

Recall that input/output ports are assigned to memory addresses Input is done by reading to that address Output is done by writing to that address A hardware

5 Recall that input/output ports are assigned to memory addresses Input is done by reading to that address Output is done by writing to that address A hardware flag looks like a bit in a memory location You can sense whether the flag is set by reading that bit You can clear the flag by writing to that bit Memory mapped IO 5

6 Flag Reading and Clearing You read a flag by reading the bit from the data bus If a read occurs to that address, signal R/W is set to 1 V DD D Q Data bus Event signal CLR You clear a flag by writing a 1 to that bit on the data bus If a write occurs to that address, signal R/W is set to 0 R/W Note: you clear a flag (ie, set it to zero) by writing a 1 to it (nonintuitive!) 6

7 Timer flags Flags are set by many kinds of events Some are caused externally (e.g., by an input signal) Others are caused internally Timers are an example of an internal event A counter automatically counts up every clock tick When it reaches a certain value, a flag is set This is a much better way to estimate time than using delay loops! Doesn t waste (as many) CPU cycles Can be more accurate 7

8 Example: RTI System Real Time Interrupt (RTI) system provides a periodic timer Clock divider is set in register RTICTL The period (in units of OSCCLK cycles) is determined by bits RTR0..RTR6 when timeout occurs, the RTIF flag (a flipflop) is set RTIF Counter RTR6:RTR0 Frequency divider RTICTL OSCCLK reset: RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR Figure 6.16 CRG RTI control register (RTICTL) 8

9 N The period (in units of OSCCLK cycles) is (N+1)*2 (M+9), where N is the bit field RTR3 through RTR0 Table 6.4 RTI interrupt period (in units of OSCCLK cycle) RTR[3:0] 0000 ( 1) 0001( 2) 0010 ( 3) 0011 ( 4) 0100 ( 5) 0101 ( 6) 0110 ( 7) 0111 ( 8) 1000 ( 9) 1001 ( 10) 1010 ( 11) 1011 ( 12) 1100 ( 13) 1101 ( 14) 1110 ( 15) 1111 ( 16) M is the bit field RTR6 through RTR4 000 (off) 001 (2 10 ) (2 11 ) RTR[6:4] 011 (2 12 ) M 100 (2 13 ) (2 14 ) (2 15 ) (2 16 ) M=0 means RTI off 9

10 RTI Flag CRGFLG register RTIF is bit 7 of CRGFLG Check this bit to see if a timeout has occurred Reset the flag by writing a 1 to that bit RTIF reset CRGFLG Register There are other flags in bits 6:0... their names aren t shown 10

11 A note about clocks An external crystal is used to generate a square wave called OSCCLK In our board it is 8 MHz This goes into a phase-locked loop (PLL) circuit which increases the frequency to 48 MHz makes it stable (v.s. jitter, skew, etc) The PLL clock is divided by 2 to make the 24 MHz E-clock But the RTI system uses the original 8 MHz OSCCLK OSCCLK (8 MHz) E-clock (24 MHz) Colpitts oscillator circuit 11

12 Example Set up the RTI system to generate periodic timeouts at intervals of approximately 0.01 second 12

13 Example Set up the RTI system to generate periodic timeouts at intervals of approximately 0.01 second Solution: The desired frequency of timeouts is 100 Hz We want to get the 8 MHz OSCCLK frequency down to 100 Hz So divide by a factor of 8 MHz/100 Hz = is 10*8000, and 8000 is about 2^13 We can get this by setting N=9, M=4 So RTR[3:0] = 9, RTR[6:4] = 4 Code: RTICTL = 0x49; 0x49 in binary is

14 Example N = = 9 10 Table 6.4 RTI interrupt period (in units of OSCCLK cycle) RTR[3:0] 0000 ( 1) 0001( 2) 0010 ( 3) 0011 ( 4) 0100 ( 5) 0101 ( 6) 0110 ( 7) 0111 ( 8) 1000 ( 9) 1001 ( 10) 1010 ( 11) 1011 ( 12) 1100 ( 13) 1101 ( 14) 1110 ( 15) 1111 ( 16) 000 (off) 001 (2 10 ) (2 11 ) RTR[6:4] 011 (2 12 ) (2 13 ) M = = (2 14 ) (2 15 ) (2 16 )

15 Example What s the slowest period for the RTI system, assuming a 8 MHz OSC clock? 15

16 Example What s the slowest period for the RTI system, assuming a 8 MHz OSC clock? Solution: From the table, 16*(2^16) is the slowest period This is 2^20, or about 10^6 cycles At us per cycle, this is sec So we get about 8 timeouts per second 16

17 Example - heartbeat Flash an LED at a rate of about 1 per second I.e., turn on for one second, then turn off for 1 sec This is kind of a heartbeat indicator by which you can tell your program is running The slowest RTI timeout rate is 8/second So we only want to take an action every 8 th timeout We will have to keep a count of timeouts Every time we sense a timeout, we increment the counter When the counter reaches 8, we reset the counter to zero and toggle the LED PT0 17

18 Example - heartbeat (continued) Psuedocode Set up PT0 for output Set up RTI rate for slowest rate initialize count = 0 while (true) while (RTIF is clear) do nothing clear RTIF by writing a 1 to it increment count end if count = 8 toggle PT0 count = 0 end 18

19 C code Example - heartbeat (continued) int count = 0; DDRT = 0x01; // Set up PT0 for output RTICTL = 0x7f; // Set up slowest RTI rate while (1) { while (!(CRGFLG & 0x80)) ; // wait till RTIF set // Clear RTIF by writing a 1 to it. // Writing 0 s to other flag bits doesn t affect them. // Don t do CRGFLG = 0x80; this will clear other flags CRGFLG = 0x80; } count++; if (count == 8) { PTT ^= 0x01; count = 0; } // toggle PT0 19

20 Example wag tail Assume PWM channel 4 is set up to control a servo motor, such that duty = 10 moves the motor all the way left, and duty = 20 moves the motor all the way right. Gradually move the motor from all the way left to all the way right over a period of about 20 seconds. Approach: We ll use the RTI system to generate timeouts every ~0.125 seconds (i.e., 8 per second). We will need to increment the duty cycle 10 times over 20 seconds. Or, increment it once every 2 seconds. Each RTI timeout occurs about seconds, so in 2 seconds we have 2.0/0.125= 16 timeouts Every 16 th timeout, increase the PWM duty cycle a little more 20

21 Example wag tail (continued) // Some code to set up PWM channel 4 follows... // : // Set up RTI system to generate timeouts at the slowest rate. The period // is about seconds. RTICTL = 0x7f; // longest possible period // We will need to increment the duty cycle 10 times over 20 seconds. // Or, increment it once every 2 seconds. Each RTI timeout occurs // every seconds, so in 2 seconds we have 2.0/0.125 = 16 timeouts. PWMDTY4 = 10; for (i=0; i<10; i++) { for (j=0; j<16; j++) { while (!(CRGFLG & 0x80)) ; } CRGFLG = 0x80; } PWMDTY4++; // wait for RTI timeout // Clear RTIF by writing a 1 to it // increment duty time 21

22 Summary / Questions A hardware flag is just a flip-flop. When an event occurs (i.e., a signal is received), the flag is set. Then the computer can read the flag later and see that the event had occurred. An example of a system that sets a hardware flag is the RTI system. It is just a periodic timer. Why is the flag system better than just directly sensing the event, for example by continuously reading an input pin? 22

PWM System. Microcomputer Architecture and Interfacing Colorado School of Mines Professor William Hoff

PWM System. Microcomputer Architecture and Interfacing Colorado School of Mines Professor William Hoff PWM System 1 Pulse Width Modulation (PWM) Pulses are continuously generated which have different widths but the same period between leading edges Duty cycle (% high) controls the average analog voltage