Microcontrollers: Lecture 3 Interrupts, Timers. Michele Magno

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1 Microcontrollers: Lecture 3 Interrupts, Timers Michele Magno 1

2 Calendar : Power consumption; Low power States; Buses, Memory, GPIOs Serial Communications Programming STM Interrupts, Timers Exercises Programming STM ADC-DMA / Interfacing external devices (STARTING AT 11:00 sharp!) Sensors / Radios Projects presentation and exercises. 2

3 Outline Interrupts Introduction and STM32 Timers Exercises. 3

4 Interrupt Definition From Wikipedia: A hardware interrupt is an electronic alerting signal sent to the processor from an external device, either a part of the [device, such as an internal peripheral] or an external peripheral. 4

5 Waiting for an Event: Family Vacation Polling 5

6 Waiting for an Event: Family Vacation Polling Interrupts Wake me up when we get there... An engineering example... 6

7 Typical application profile 2 Tperiod Tperiod I DD Process IRQ ACTIVE IRQ ACTIVE OFF STARTUP INITIALIZATION TASKS TASKS INACTIVE INACTIVE INACTIVE Application phases: OFF power is not applied to MCU STARTUP INITIALIZATION MCU performs configuration (peripherals, clocks, ) Tperiod INACTIVE MCU is in low power mode to reduce power consumption ACTIVE MCU is in normal mode and performs tasks Time 7

8 Waiting for an Event: Button Push Polling Interrupts while(1) { // Polling GPIO button while (GPIO_getInputPinValue()==1) } GPIO_toggleOutputOnPin(); 100% CPU Load // GPIO button interrupt #Iterrupt servise routine interrupt void rx (void){ GPIO_toggleOutputOnPin(); } > 0.1% CPU Load How interrupts can affect system design 8

9 Interrupts Help Support Ultra Low Power Very little CPU effort required Keep CPU asleep (i.e. in Low Power Mode) while waiting for event Interrupt wakes up CPU when it s required Another way to look at it is that interrupts often cause a program state change Only timers are running Often, work can be done by peripherals, letting CPU stay in low power mode (e.g. Gate Lots of Time) sleep time Basic program topology... 9

10 Interrupts A way to respond to an external event (i.e., flag being set) without polling How it works: H/W senses flag being set Automatically transfers control to s/w that services the interrupt When done, H/W returns control to wherever it left off Main Prog ISR : : : : RETI Advantages: Transparent to user cleaner code μc doesn t waste time polling 10

11 Foreground / Background Scheduling main() { } //Init initgpio(); initclocks();... while(1){ background or Low Power Mode } ISR1 get data process ISR2 set a flag System Initialization The beginning part of main() is usually dedicated to setting up your system Background Most systems have an endless loop that runs forever in the background In this case, Background implies that it runs at a lower priority than Foreground In microcontrollers, the background loop often contains a Low Power Mode command this sleeps the CPU/System until an interrupt event wakes it up Foreground Interrupt Service Routine (ISR) runs in response to enabled hardware interrupt These events may change modes in Background such as waking the CPU out of low-power mode ISR s, by default, are not interruptible Some processing may be done in ISR, but it s usually best to keep them short 11

12 Foreground / Background (States) Foreground (higher priority) ISR1 ISR2 ISR2 Background main() main() (lower priority) 12

13 STM32L1x - Block Diagram 13 Presentation Title

14 Nested Vectored Interrupt Controller (NVIC) Hardware unit that coordinates among interrupts from multiple sources Define priority level of each interrupt source (NVIC_PRIx_R registers) Separate enable flag for each interrupt source (NVIC_EN0_R and NVIC_EN1_R) Interrupt does not set I bit Higher priority interrupts can interrupt lower priority ones 14

15 Nested Vector Interrupt Controller NVIC Up to 81 interrupts (depends on the STM32 device type) Programmable priority level of 0-15 A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority Dynamic reprioritization of interrupts Grouping of priority values into group priority and sub-priority fields Interrupt tail-chaining An external Non-maskable interrupt (NMI) 15

16 Nested Vector Interrupt Controller NVIC 16

17 Input floating EXTI module: from pin to NVIC GPIOA_0 GPIOB_0 Channel 0 EXTI Event CORTEX M4 GPIOI_0 Wakeup GPIOA_1 GPIOB_1 Channel 1 GPIOI_1 GPIOA_15 GPIOB_15 Channel 15 ENABLE Exti_0 Exti_1 NVIC GPIOI_15 DISABLE Exti_2 Exti_3 Exti_4 PVD RTC_Alarm USB OTG FS Wkup ETH Wkup USB OTG HS Wkup RTC Tamper RTC Wkup Interrupt Exti_9-5 Exti_15-10 PVD_IRQ RTC_IRQ

18 Nested Vector Interrupt Controller NVIC Nested Interrupt: If a interrupt request (IRQ) with higher priority is raised, it is served first Tail chaining: for nested ISR does not restore all saved registers from the stack. Stack pop pre-emption: If another exception occurs during the unstacking process of an exception, the processor abandons the stack Pop 18

19 19 TIMERS Presentation Title

20 Timers Correct system timing is a fundamental requirement for the proper operation of a real-time application; If the timing is incorrect, the input data may be processed after the output was updated The timers may be driven from an internal or external clock; Usually timers include multiple independent capture and compare blocks, with interrupt capabilities; Main applications: Generate events of fixed-time period; Allow periodic wake-up from sleep; Count external signals/events; Signal generation (Pulse Width Modulation PWM); Replacing delay loops with timer calls allows the CPU to sleep between operations, thus consuming less power

21 Timer/Counter Basics Clock Input Clock GPIO Pin (TACLK) Counter Register Counter Overflow Action Interrupt Input Counter Action Notes Timers are often called Timer/Counters as a counter is the essential element Timing is based on counting inputs from a known clock rate What happens on each clock input? 21

22 Timer/Counter Basics TAR Clock Input Clock GPIO Pin (TACLK) Counter Register Counter Overflow Action Interrupt (TAIFG) FFFD FFFE FFFF Interrupt occurs when timer overflows back to zero Each pulse of clock input increments the counter register Notes Timers are often called Timer/Counters as a counter is the essential element Timing is based on counting inputs from a known clock rate Actions don t occur when writing value to counter Can I 'capture' a count/time value? 22

23 Frequency, Time Period, Resolution With what resolution can we determine if an event occurred here? timer interrupt timer interrupt timer interrupt Time Period Definitions Frequency: Time Period: Resolution: How many times per second Amount of time between successive events Granularity in determining system events 23

24 Capture Basics TAR 15 0 Clock Input Clock GPIO Pin Counter Register Counter Overflow Action Interrupt (TAIFG) Notes Capture time (i.e. count value) when Capture Input signal occurs Alternatively, use CCR for compare... 24

25 Capture Basics TAR 15 0 Clock Input Clock GPIO Pin (TACLK) Counter Register Counter Overflow Action Interrupt (TAIFG) Capture Input signal triggers transfer: Counter Capture Capture/Compare Register (CCR n ) Notes Capture time (i.e. count value) when Capture Input signal occurs When capture is triggered, count value is placed in CCR and an interrupt is generated 25

26 Capture Basics TAR 15 0 Clock Input Clock GPIO Pin (TACLK) Counter Register Counter Overflow Action Interrupt Capture Input signal triggers transfer: Counter Capture Capture Input CCInA CCInB Software Capture/Compare Register (CCR n ) Capture Actions Interrupt Signal peripheral Modify pin (TIM_OUT) Notes Capture time (i.e. count value) when Capture Input signal occurs When capture is triggered, count value is placed in CCR and an interrupt is generated Capture Overflow (COV): indicates 2 nd capture to CCR before 1 st was read 26

27 Compare Basics Clock Input Clock GPIO Pin (TACLK) Counter Register Counter Overflow Action Interrupt A key feature for timers is the ability to create consistent, periodic interrupts 27

28 Compare Basics Clock Input Clock GPIO Pin (TACLK) Counter Register Counter Overflow Action Interrupt Capture/Compare Register (CCR n ) 28

29 Compare Basics Clock Input Clock GPIO Pin (TACLK) TAR Counter Register Counter Overflow Action Interrupt (TAIFG) when Counter = Compare Compare Actions can occur Capture/Compare Register (CCR n ) Compare Actions Interrupt Signal peripheral Modify pin (TIM_OUT) Notes There are usually 2 to 7 compare registers (CCR s), therefore up to 8 interrupts or signals can be generated Counter must count-to Compare value to generate action 29

30 Example Divide by 5-bits (up to 64) 16-bit Counter (TA0R) Enable (TA0IE) Interrupt (TA0IFG) CCR0 CCR1 CCR2 CCR3 CCR4 CCR5 CCR6 30

31 Timer_A7 Summary 15 0 Divide by 5-bits (up to 64) 16-bit Counter (TAR) Enable (TAIE) Interrupt (TAIFG) CAP=0 CAP=1 CM SCS COV CCR0. CCR6 CC0IE CC6IE CC0IFG TA0.0 CC6IFG TA0.6 TimerA0.0: Is the first instance (Timer0 or TA0) of Timer_A7 on the device _A7 means it has 7 Capture/Compare Registers (CCR s) CCR registers can be configured for: Compare (set when CAP=0) generates interrupt (CCnIFG) and modifies OUT signal when TAR = CCRn Capture (when CAP=1) grabs the TAR value and sets an interrupt (CCnIFG) when triggered by the selected CCIx input 31

32 Timers STM32 The general-purpose timers consist of a 16-bit (or 32bits) auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers. General-purpose TIMx timer features include: - 16-bit up, down, up/down auto-reload counter bit programmable prescaler used to divide (also on the fly ) the counter clock frequency by any factor between 1 and Up to 4 independent channels for: Input capture Output compare PWM generation (Edge- and Center-aligned modes) One-pulse mode output 32

33 Timers Basic architecture STM32. CLOCKS CLOCKS / N Counter/Autro-reload Capture/compare 33

34 RCC Real Time Clock Control 34

35 Timers General-purpose timer block diagram 35

36 Timers PATH: TimerX - Channel 1 - output compare 36

37 Timers PATH: TimerX - Channel 2 - output compare 37

38 Timers PATH: TimerX - Channel 3 - output compare 38

39 Timers PATH: TimerX - Channel 4 - output compare 39

40 Timers 24MHz 40

41 Timers 41

42 Timers The counter clock can be divided by a prescaler. 42

43 Timers The main block of the programmable timer is a 16- bit counter with its related auto-reload register. The counter can count up, down or both up and down. CNT CK_CNT 43

44 Timers In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. Period Autoreload Register Timer Interrupt CNT CK_CNT 44

45 Timers Output compare mode: This function is used to control an output waveform or indicating when a period of time has elapsed. Autoreload Register Timer Interrupt Compare Register CNT CH1 Interrupt OC1 CK_CNT 45

46 Timers Output compare mode: This function is used to control an output waveform or indicating when a period of time has elapsed. Used to schedule periodic events Autoreload Register Timer Interrupt Compare Register CNT CH1 Interrupt OC1 CK_CNT 46

47 PWM What is Pulse Width Modulation? Pulse width modulation (PWM) is a simple method of using a rectangular digital waveform to control an analog variable PWM delivers a variable amount of power efficiently to external hw devices PWM control is used in a variety of applications, ranging from communications to automatic control, i.e. control speed of electric motors, brightness of a LED, temperature of heating element 47

48 PWM The period is normally kept constant, and the pulse width, or on time is varied The duty cycle is the proportion of time that the pulse is on or high, and is expressed as a percentage: duty cycle = 100% * (pulse on time) / (pulse period) 48

49 PWM Whatever duty cycle a PWM stream has, there is an average value, as indicated by the dotted line If the on time is small, the average value is low; if the on time is large, the average value is high By controlling the duty cycle, we control this average value 49

50 PWM The average value can be extracted from the PWM stream with a low-pass filter In this case, and as long as PWM frequency and values of R and C are appropriately chosen, Vout becomes an analog output In practice, this sort of filtering is not always required; many physical systems have response characteristics which, in reality, act like low pass filters 50

51 Applications using PWM Devices used in robotics DC motors Servos Solenoids Closed loop control systems Communications and pulse code modulation Any device whose response to changes in current or voltage is slow compared to the frequency of the PWM signal is a candidate for being controlled via PWM. Benefits include Microprocessor control Efficient use of power Tolerance to analog noise Not susceptible to component drift 51

52 STM32 GPIO Timers for PWM The STM32 hardware timers are separate hardware blocks that can count from 0 to a given value triggering some events in between. In the PWM mode the timer controls the output of 1 or more output channels. When the counter value reaches 0, maximum or a compare value defined for each channel, the output value of the channel can be changed. Various configuration options define which events change the value and how it is changed. T; f = 1/T 52

53 STM32 GPIO Timers for PWM Up to 4 channel Edge-aligned mode Center-aligned mode Timer Type Resolution Prescaler Channels MAX INTERFACE CLOCK MAX TIMER CLOCK* TIM1, TIM8 Advanced 16bit 16bit 4 SysClk/2 SysClk 2 TIM2, TIM5 General purpose 32bit 16bit 4 SysClk/4 TIM3, TIM4 General purpose 16bit 16bit 4 SysClk/4 SysClk, SysClk/2 SysClk, SysClk/2 TIM9 General purpose 16bit 16bit 2 SysClk/2 SysClk 2 APB 1 1 TIM10, TIM11 General purpose 16bit 16bit 1 SysClk/2 SysClk 2 TIM12 General purpose 16bit 16bit 2 SysClk/4 SysClk, SysClk/2 1 TIM13, TIM14 General purpose 16bit 16bit 1 SysClk/4 SysClk, SysClk/2 1 TIM6, TIM7 Basic 16bit 16bit 0 SysClk/4 SysClk, 1 53

54 Frequency and Times Example, a 16 bit Timer fsystemclock=ftimer=8mhz As you said we have a tick in every, Ttimer=1/fSystemClock=1/ftimer=1/8MHz=0.125μs With a 16 bit Timer it means, ticksmax=(2 16-1)=65535ticks So the timer will overflow in every, toverflow=ticksmax Ttimer= μs= ms 54

55 GPIO Timer Block diagram 55

56 APB1 or APB 2? APB2 APB1 56

57 Timer Example exercises Calculate the Timer Setting for the Clock & divider values needed to create a timer interrupt every 2seconds when the CPU of the following processor is in the deep sleep mode allowed. 57

58 Timers - Exercises Low Power Sleep Low Power Model= Input Clock= 32KHz 1 32KHz Timer Clock= 32KHz / = 1/ 32KHz Time = * = 2s 16 or 32 bit? Duty Cycling 1 = * 100 / = 50% Capute compare value Duty Cycling 2 = * 100 / = 25% Capute compare value THIS IS VALID ONLY FOR TIMER IN UP-COUNTING MODE!! THERE ARE MANY MODALITIES GENERATING MANY DIFFERENT PWM 58

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