ECE 4510/5530 Microcontroller Applications Midterm Review

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1 Microcontroller Applications Midterm Review Dr. Bradley J. Bazuin Associate Professor Department of Electrical and Computer Engineering College of Engineering and Applied Sciences

2 Exam Composition HC12 Parallel Pin use for external components Hardware design for: LED Bar, Dip switch, Keypad, 5x7 Display, electro-mechanical relay, push-button interrupt HC12 Peripheral Components Clock and Reset Generator (CRG), Enhanced Timer/Counter (ECT), Pulse Width Modulator (PWM), Serial Communication Interface (SCI) Software Software time delay Code to generate parallel outputs in time Peripheral initialization Peripheral interrupts Main programs to perform various operations

3 Important Peripherals 3

4 Time Delay Software Approaches Delay Loop Software Delay Subroutine Hardware/Peripheral Based Approaches Real-time interrupt (RTI) hardware in the CRG Modulus Down Counter in the ECT Output Compare Timer in the ECT 4

5 Program Execution Time Example: find delay created if E = 41.67ns = 1/24 MHz. ldx #$1234 ; 2E Loop1: ldy #$ABCD ; 2E Loop2: dbne Y, Loop2 ; 3E taken/3e not dbne X, Loop1 ; 3E taken/3e not Total time Inner loop: (2 + Yreg-1)*3 + 3) E Cycles IL approx. (Yreg*3)*41.67ns 43981*3/24 MHz sec Outer loop: (2+Xreg*IL+(Xreg-1)*3 +3) * 41.67ns Total Exact = (Xreg*Yreg*3+Xreg*(3+2)+2) * 41.67ns Total Approx. (4660*(43981)*3) /24 MHz sec

6 EXTERNAL HARDWARE 6

7 MC7805CTG Linear Regulator 5V Positive Voltage Regulator Output Current in Excess of 1.0 A No External Components Required Internal Thermal Overload Protection Internal Short Circuit Current Limiting Output Transistor Safe Area Compensation Output Voltage Offered in 1.5%, 2% and 4% Tolerance Available in Surface Mount D2PAK 3, DPAK 3 and Standard 3 Lead Transistor Packages Data Sheet: MC7805CTG, ON Semiconductor 7

8 Lab LED and Light Bar Connections Buffer the HC12 port (!!!) Inverting buffer 540 Non-inverting buffer 541 Provide current sinking for the LED Resistor between +5 and LED The resistor provides current limiting Resistor Value LED needs ~1.2 to 1.5 V drop LED wants ~ 10 ma or more I ~ from 8 to 12 ma 5V 1.2V 0.8V OL R mA

9 Lab Dip Switch Connections Buffer the HC12 port (!!!) Inverting buffer 540 Non-inverting buffer 541 Provide isolation from switch Resistor between +5 and switch If you short the switch while probing, the resistor provides current limiting. Resistor Value 330 ohms or greater (10 kohm preferred)

10 Class Keypads 10

11 Driving a 5 x 7 LED Array Lighting One LED Source current to a row Selectively sink current from a column 20 ma, V 80 ma, V Matrix Driving Separately source all rows where LEDs are to turn on in Column 1 AND sink current from only column 1. Do the next column and repeat. Lite-On Technology Corp. LTP-757G 11

12 Driving a 5 x 7 LED Array Source MIC x 7 LED Array Sink ULN2803a Sink Column Select 74HCT595 (not shown) 12

13 Operating the MIC5891YN A. Minimum data active time before clock pulse (data set-up time) 75ns B. Minimum data active time after clock pulse (data hold time) 75ns C. Minimum data pulse width.150ns D. Minimum clock pulse width 150ns E. Minimum time between clock activation and strobe 300ns F. Minimum strobe pulse width 100ns G. Typical time between strobe activation and output transition 1.0μs 13

14 Lab 4 Relay Design 14

15 Parts Kit RS-232 Transceiver IC MAX232IN Meets or Exceeds TIA/EIA-232-F and ITU Recommendation V.28 Operates From a Single 5-V Power Supply With 1.0-uF Charge-Pump Capacitors Operates Up To 120 kbit/s Two Drivers and Two Receivers ±30-V Input Levels Low Supply Current... 8 ma Typical ESD Protection Exceeds JESD V Human-Body Model (A114-A) Upgrade With Improved ESD (15- kv HBM) and 0.1-uF Charge-Pump Capacitors is Available With the MAX202 Applications TIA/EIA-232-F, Battery-Powered Systems, Terminals, Modems, and Computers 15

16 Interfacing with the Transceiver Interfacing the HCS12 SCI0 to the EIA-232 using the DS14C232 chip and implements the NULL modem connection so that this connection can talk to a PC directly. DS14C232 1 DCD 6 DSR PS1/TxD 11 T1IN T1OUT 14 2 RxD CTS* 10 T2IN R2IN 8 7 RTS PS0/RxD 12 R1OUT R1IN 13 3 TxD RTS* 9 R2OUT T2OUT 7 8 CTS Note: Both CTS and RTS are jumpered to an I/O pin in case hardware handshake is needed DTR RI GND DB9 connector Figure 9.19 Diagram of SCI and EIA232 DB9 connector wiring in SSE256 demo board

17 INTERNAL PERIPHERALS 17

18 Clock and Reset Generation Block (CRG) RESET XCLKS EXTAL XTAL XFC VDDPLL VSSPLL VREG CRG Clock monitor OSC PLL Power on reset CM fail OSCCLK PLLCLK Clock and Reset Control Reset generator Clock quality checker COP Registers RTI System Reset Bus clock Core clock Oscillator clock Figure 6.4 Block diagram of CRG

19 Choice of Clock Source extal xtal Phase lock loop Oscillator OSCCLK gating condition PLLCLK = clock gate Clock monitor PLLSEL or SCM 1 0 SCM 1 0 WAIT, STOP wait(rtiwai), stop(pstp,pre) RTI enable wait (COPWAI), stop(pstp, PCE) COP enable wait (SYSWAI), stop stop (PSTP) SYSCLK wait (CWAI,SYSWAI) stop clock phase generator Figure 6.15 HCS12 clock generation circuit 2 RTI COP Core clock Bus clock oscillator clock oscillator clock ( pseudo stop mode) E-Clock Real Time Interrupt Comp. Operating Properly

20 RTI Counter Chain Note: OSCCLK not SYSCLK and not E-Clock Key Registers: RTICTL CRGINT CRGFLG to CRG Block User Guide V02.07, Doc. Number S12CRGV2/D

21 Enhanced Timer-Counter (ECT) Key Registers: TCNT TSCR1 TSCR2 TIOS TIE TFLG1 TFLG2 TCTL1/2 TCTL3/4 TCx, x=0:7 MCCTL MCCNT MCFLG 21

22 ECT Block Diagram (Queue Mode) bus clock 1,2,..., bit load register 1, 4, 8, 16 Prescaler 16-bit free-running maintimer bus clock Prescaler 16-bit modulus down counter PTx pin logic Delay counter EDG x comparator TCxcapture/compare register one IC channel (IC0..IC3) TCxH hold register to other IC channels PTi pin logic EDG i MUX EDG j j = 8 - i comparator TCxcapture/compare register one IC channel (IC4..IC7) Figure 8.36 Enhanced Input capture function block diagram in Queue mode (channels IC0..IC3 block diagram) 22

23 PWM Block Diagram PWM Module PWM Channels Key Registers: Bus clock Clock select Control Enable PWM clock Channel 7 Period and duty Channel 6 Period and duty Channel 5 Period and duty Channel 4 Period and duty Counter Counter Counter Counter PWM7 PWM6 PWM5 PWM4 PWMPRCLK PWMSCLA PWMSCLB PWMCLK PWME PWMCNTx Polarity Alignment Channel 3 Period and duty Channel 2 Period and duty Counter Counter PWM3 PWM2 PWMDTYx PWMPERx PWMPOL Channel 1 Period and duty Counter PWM1 PWMCAE PWMCTL Channel 0 Period and duty Counter PWM0 Figure 8.38 HCS12 PWM block diagram 23

24 PWM Channel Block Diagram clock source GATE (clock edge sync) 8-bit counter PWMCNTx From port PTP data register up/ down reset 8-bit compare= PWMDTYx T R Q Q M U X M U X to pin driver 8-bit compare= PPOLx PWMPERx Q Q T R CAEx PWMEx Figure 8.44 PWM channel block diagram 24

25 The HCS12 SCI Subsystem Key Registers: RxD Bus clock TxD BAUD generator SCI data register Receive shift register Receive and wake up control 16 Data format control Transmit control Transmit shift register SCI data register Interrupt generation Interrupt generation Idle IRQ RDRF/OR IRQ TDRE IRQ TC IRQ O R I N G IRQ to CPU SCIxDRL SCIxBD SCIxCR1 SCIxCR2 SCIxSR1 SCIxSR2 Status Register 1 Figure 9.8 HCS12 SCI block diagram Status Register 2 25

26 The EIA-232E Electrical Specifications 26

27 Additional Software User inputs from and outputs to a PC terminal window User inputs from a keypad and outputs to an LED matrix display Using text line buffers (sscanf and sprintf) Time and calendar operations, with an alarm Computing periodicity and duty cycle Generating output waveforms (period and duty cycle) Collecting and buffering results IIR filter operation Operating States and modes within the states 27

ECE 4510/5530 Microcontroller Applications Week 6 Lab 5

ECE 4510/5530 Microcontroller Applications Week 6 Lab 5 Microcontroller Applications Week 6 Lab 5 Dr. Bradley J. Bazuin Associate Professor Department of Electrical and Computer Engineering College of Engineering and Applied Sciences Lab 5 Element Hardware