ECE 4510/5530 Microcontroller Applications Chapter 8 ECT and PWM

Transcription

1 Microcontroller Applications Chapter 8 ECT and PWM Dr. Bradley J. Bazuin Associate Professor Department of Electrical and Computer Engineering College of Engineering and Applied Sciences

2 Chapter 8 Enhanced Capture Timer 16-bit main counter with 7-bit prescaler 8 programmable input capture or output compare channels Two 8-bit or one 16-bit pulse accumulators 8 PWM channels Programmable period and duty cycle 8-channel 8-bit or 4-channel 16-bit Separate control for each pulse width and duty cycle Center-aligned or left-aligned outputs Programmable clock select logic with a wide range of frequencies Fast emergency shutdown input Usable as interrupt inputs 2

3 Memory Addresses 3

4 Adapt9S12DP512 I/O Pins 4

5 Overview of Timer Functions Many applications require a dedicated timer system Time delay creation and measurement Period and pulse width measurement Frequency measurement Event counting Arrival time comparison Time of day tracking Periodic interrupt generation Waveform Generation The TIM (and ECT also) shares the eight Port T pins (IOC0 IOC7). 5

6 Overview of Timer Functions The applications mentioned will be very difficult to implement without a dedicated timer system HCS12 implements a very complicated timer system to support the implementation of these applications HCS12 microcontroller consists of a 16-bit timer counter The timer can be started or stopped according to the wishes of the programmer Three different timer functions can be implemented in HCS12 Input-capture Output compare Timer overflow 6

7 The HCS12 Timer System (1 of 2) The HCS12 has a standard timer module (TIM) that consists of: Eight channels of multiplexed input capture and output compare functions. 16-bit pulse accumulator A 16-bit timer counter The TIM block diagram is shown in Figure 8.1. The DP512 devices have implemented an Enhanced Capture Timer module (ECT). The ECT module contains: All the features contained in the TIM module One 16-bit buffer register for each of the input capture channels Four 8-bit pulse accumulator A 16-bit Modulus Down Counter with 4-bit prescaler Four user selectable delay counters for increasing input noise immunity The TIM (of course ECT also) shares the eight Port T pins (IOC0 IOC7). 7

8 The HCS12 Timer System (2 of 2) 8

9 Applications of Input Capture Function Event arrival time recording Period measurement: need to capture the main timer values corresponding to two consecutive rising or falling edges one period (a) Capture two rising edges one period (b) Capture two falling edges Figure 8.9 Period measurement by capturing two consecutive edges Pulse width measurement: need to capture the rising and falling edges Pulse width Rising edge Falling edge Figure 8.10 Pulse-width measurement using input capture

10 Input Capture Interrupt generation: Each input capture function can be used as an edge-sensitive interrupt source. Event counting: count the number of signal edges arrived during a period e 1 e 2 e 3 e 4 e i e j Start of interval End of interval Figure 8.11 Using an input-capture function for event counting Time reference: input-capture used in conjunction with an output compare function Time t 0 Time t 0 + delay Time of reference (set up by signal edge) Figure 8.12 A time reference application Time to activate output signal (set up by output compare)

11 Duty Cycle Measurement T T duty cycle = T T * 100% Figure 8.13 Definition of duty cycle 11

12 Phase Difference Measurement T signal S1 T signal S2 T phase difference = * 360 o T Figure 8.14 Phase difference definition for two signals 12

13 T Pin Related Registers Timer Counter Registers TIOS = $40 TCFORC = $41 TOC7M = $42 TOC7D = $43 TCNT = $44 (16-bit) TSCR1 = $46 TTOV = $47 TCTL1 = $48 TCTL2 = $49 TCTL3 = $4A TCTL4 = $4B TIE = $4C TSCR2 = $4D TFLG1 = $4E TFLG2 = $4F Timer Counter Registers TC0 = $50 (16-bit) TC1 = $52 (16-bit) TC2 = $54 (16-bit) TC3 = $56 (16-bit) TC4 = $58 (16-bit) TC5 = $5A (16-bit) TC6 = $5C (16-bit) TC7 = $5E (16-bit) and more through $7F 13

14 The HCS12 Timer Elements Bus clock Timer overflow interrupt Prescaler 16-bit counter Channel 0 Input Capture Output compare Channel 1 Input Capture Output compare Channel 2 IOC0 IOC1 16-bit free-running main timer Prescalaer TC0 interrupt TC1 interrupt TC2 interrupt TC3 interrupt TC4 interrupt Registers Input Capture Output compare Channel 3 Input Capture Output compare Channel 4 Input Capture Output compare IOC2 IOC3 IOC4 16-bit modulus downcounter Prescalaer Load Control Registers TC5 interrupt TC6 interrupt TC7 interrupt PA overflow interrupt PA input interrupt 16-bit Pulse accumulator A Channel 5 Input Capture Output compare Channel 6 Input Capture Output compare Channel 7 Input Capture Output compare IOC5 IOC6 IOC7 Interrupt Registers Capture/Compare Registers Figure 8.1 HCS12 Standard Timer (TIM) block diagram 14

15 Timer Block Diagram (Latch Mode) bus clock 1,2,..., bit load register 1, 4, 8, 16 Prescaler 16-bit free-running 16-bit modulus main timer bus clock Prescaler down counter PTx pin logic Delay counter EDG x comparator TCx capture/compare register one IC channel (IC0..IC3) TCxH hold register to other IC channels ICLAT, LATQ, BUFEN (force latch) Latch write $0000 to modulus counter LATQ (MDC latch enable) PTi pin logic EDG i MUX EDG j j = 8 - i comparator TCx capture/compare register one IC channel (IC4..IC7) Figure 8.35 Enhanced Input capture function block diagram in latch mode 15

16 Timer Block Diagram (Queue Mode) bus clock 1,2,..., bit load register 1, 4, 8, 16 Prescaler 16-bit free-running maintimer bus clock Prescaler 16-bit modulus down counter PTx pin logic Delay counter EDG x comparator TCxcapture/compare register one IC channel (IC0..IC3) TCxH hold register to other IC channels PTi pin logic EDG i MUX EDG j j = 8 - i comparator TCxcapture/compare register one IC channel (IC4..IC7) Figure 8.36 Enhanced Input capture function block diagram in Queue mode (channels IC0..IC3 block diagram) 16

17 Timer Counter Register (TCNT) Required for input capture and output compare functions. An up counter. Must be accessed in one 16- bit operation in order to obtain the correct value Three other registers related to the operation of the TCNT: TSCR1, TSCR2, TFLG2. The 16-bit main timer is an up counter. A full access for the counter register should take place in one clock cycle. A separate read (any mode)/write (test mode) for high byte and low byte will give a different result than accessing them as a word. Read anytime. Write has no meaning or effect in the normal mode; only writable in special modes (test_mode = 1). The period of the first count after a write to the TCNT registers may be a different size because the write is not synchronized with the prescaler clock. 17

18 Running the TCNT Counter Timer Counter Register 1 (TSCR1) Select the mode of operation for the module STOP: Timer and modulus counter are off since clocks are stopped. FREEZE: Timer and modulus counter keep on running, unless TSFRZ in TSCR($06) is set to one. WAIT: Counters keep on running, unless TSWAI in TSCR ($06) is set to one. NORMAL: Timer and modulus counter keep on running, unless TEN in TSCR($06) respectively MCEN in MCCTL ($26) are cleared. Timer Counter Register 2 (TSCR2) Timer prescale counting factor, timer overflow IE, and timer counter reset enable Timer Interrupt Flag 2 Register (TFLG2) Bit 7 (TOF) Set when 16-bit free-running timer overflows from $FFFF to $0000. This bit is cleared automatically by a write to the TFLG2 register with bit 7 set. (See also TCRE control bit explanation.) 18

19 Timer System Control Register 1 (TSCR1) Setting and clearing the bit 7 of TSCR1 will start and stop the counting of the TCNT. Setting the bit 4 will enable fast timer flag clear function. If this bit is clear, then the user must write a one to a timer flag in order to clear it value TEN TSWAI TSFRZ TFFCA after reset TEN -- timer enable bit 0 = disable timer; this can be used to save power consumption 1 = allows timer to function normally TSWAI -- timer stops while in wait mode bit 0 = allows timer to continue running during wait mode 1 = disables timer when MCU is in wait mode TSFRZ -- timer and modulus counter stop while in freeze mode 0 = allows timer and modulus counter to continue running while in freeze mode 1 = disables timer and modulus counter when MCU is in freeze mode TFFCA -- timer fast flag clear all bit 0 = allows timer flag clearing to function normally 1 = For TFLG1, a read from an input capture or a write to the output compare channel causes the corresponding channel flag, CnF, to be cleared. For TFLG2, any access to the TCNT register clears the TOF flag. Any access to the PACN3 and PACN2 registers clears the PAOVF and PAIF flags in the PAFLG register. Any access to the PACN1 and PACN0 registers clears the PBOVF flag in the PBFLG register. Figure 8.2 Timer system control register 1 (TSCR1) 19

20 Timer System Control Register 2 (TSCR2) Bit 7 is the TCNT overflow interrupt enable bit. The clock input (E-CLK) to TCNT (E-Clock) can be prescaled by a factor selecting by bits 2 to 0 of TSCR value TOI TCRE PR2 PR1 PR0 after reset TOI -- timer overflow interrupt enable bit 0 = interrupt inhibited 1 = interrupt requested when TOF flag is set TCRE -- timer counter reset enable bit 0 = counter reset inhibited and counter free runs 1 = counter reset by a successful output compare 7 If TC7 = $0000 and TCRE = 1, TCNT stays at $0000 continuously. If TC7 = $FFFF and TCRE = 1, TOF will never be set when TCNT rolls over from $FFFF to $0000. Figure 8.3 Timer system control register 2 (TSCR2) TCNT can be reset to 0 when TCNT equals TC7 by setting bit 3 of TSCR2. Table 8.1 Timer counter prescale factor PR2 PR1 PR0 Prescale Factor

21 Timer Interrupt Flag 2 Register Only bit 7 (TOF) is implemented. Bit 7 will be set whenever TCNT overflows. (TFLG2) TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit to one. Read anytime. Write used in clearing mechanism (set bits cause corresponding bits to be cleared). Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set. TOF Timer Overflow Flag Set when 16-bit free-running timer overflows from $FFFF to $0000. This bit is cleared automatically by a write to the TFLG2 register with bit 7 set. (See also TCRE control bit explanation.) 21

22 Using TCNT Values Once the counter is set up, the timer functions can be used to: In - Input-Capture: The TCNT value is captured when the desired external event occurs Out - Output-Compare: The output occurs when TCNT equals the preset register value 22

23 Timer Port Pins Each port pin can be used as a general I/O pin when timer function is not selected. Pin 7 can be used as input capture 7, output compare 7 action, and a pulse accumulator input. The pulse accumulation function is unique to this pin. When a timer port pin is used as a general I/O pin, its direction is configured by the DDRT register. 23

24 24

25 INPUT CAPTURE 25

26 Input Capture Functions (1 of 2) Physical time is often represented by the contents of the main timer. The time when an event occurs can be recorded by latching the count of the main timer when a signal edge arrives as illustrated in Figure 8.4. The occurrence of an event is represented by a signal edge (rising or falling edge). The HCS12 has eight input capture channels. Each channel has a 16-bit capture register, an input pin, edge-detection logic, and interrupt generation logic. Input capture channels share most of the circuit with output compare functions. For this reason, they cannot be enabled simultaneously. Rising edge Falling edge or Figure 8.4 Events represented by signal edges

27 Input Capture Functions (2 of 2) The selection of input capture and output compare is done by programming the TIOS register. The contents of the TIOS register are shown in Figure 8.5. Setting a bit select the output compare function. Otherwise, the input capture function is selected value IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 after reset IOS[7:0] -- Input capture or output compare channel configuration bits 0 = The corresponding channel acts as an input capture 1 = The corresponding channel acts as an output compare Figure 8.5 Timer input capture/output compare select register (TIOS) The following instruction will enable the output compare channels and input capture channel 3 0: movb #$F0,TIOS 27

28 Timer Control Register 3 and 4 The signal edge to be captured is selected by TCTL3 and TCTL value EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A after reset (a) Timer control register 3 (TCTL3) EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A The edge to be captured is selected by two bits. The user can choose to capture the rising edge, falling edge, or both edges (b) Timer control register 4 (TCTL4) EDGnB EDGnA -- Edge configuration 0 0 : Capture disabled 0 1 : Capture on rising edges only 1 0 : Capture on falling edges only 1 1 : Capture on both edges Figure 8.5 Timer control register 3 and 4 28

29 Timer Interrupt Enable Register (TIE) The arrival of a signal edge may optionally generate an interrupt to the CPU. The enabling of the interrupt is controlled by the Timer Interrupt Enable Register C7I C6I C5I C4I C3I C2I C1I C0I reset: C7I-C0I: input capture/output compare interrupt enable bits 0 = interrupt disabled 1 = interrupt enabled Figure 8.7 Timer interrupt enable register (TIE) 29

30 Timer Interrupt Flag 1 Register (TFLG1) Whenever a signal edge arrives, the associated timer interrupt flag will be set to 1. Read anytime. Write used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero will not affect current status of the bit C7F C6F C5F C4F C3F C2F C1F C0F reset: CnF: input capture/output compare interrupt flag bits 0 = interrupt condition has not occurred 1 = interrupt condition has occurred Figure 8.8 Timer interrupt flag register 1 (TFLG1) 30

31 How to Clear a Timer Flag Bit In normal mode, write a 1 to the flag bit to be cleared. Method 1 BSET TFLG1, $01 ;will clear the C0F flag. Method 2 movb #$01,TFLG1 ;will clear the C0F flag. C-code TFLG1 = C0F; //clear the C0F Flag When the fast timer flag clear function is enabled (TFFCA bit in the TSCR register is set), a read from an input capture or a write into an output compare channel ($10 $1F) will cause the corresponding channel flag CnF to be cleared. See Figure 8.1.

32 Example 8.2: Period Measurement (1 of 2) Use the IC0 to measure the period of an unknown signal. The period is known to be shorter than 128 ms. Assume that the E clock frequency is 24 MHz. Use the number of clock cycles as the unit of the period. Solution: Since the input-capture register is 16-bit, the longest period of the signal that can be measured with the prescaler to TCNT set to 1 is: 2^16 24 MHz = 2.73 ms. To measure a period that is equal to 128 ms, we have two options: Set the prescale factor to 1 and keep track of the number of times the timer counter overflows. Set the prescale factor to 64 and do not keep track of the number of times the timer counter overflows. We will set the prescale factor to TCNT to 64 (2^16 24 MHz /64 = ms or 2 2/3 usec time steps). The logic flow for measuring the signal period is shown in Figure 8.16.

33 Example 8.2: Period Measurement (2 of 2) Start Choose to capture the rising edge Set the timer counter prescale factor to 16 Enable the timer counter Clear the C0F flag one period (a) Capture two rising edges one period no C0F = 1? yes Saved the captured first edge Clear the C0F flag (b) Capture two falling edges Figure 8.9 Period measurement by capturing two consecutive edges no C0F = 1? yes Take the difference of the second and the first captured edges Stop Figure 8.16 Logic flow of period measurement program 33

34 Example 8.2: Assembly Program for Period Measurement #include "c:\miniide\hcs12.inc".org $1000 edge1:.byte 2 ; memory to hold the first edge period:.byte 2 ; memory to store the period.text _main:: movb #$90,TSCR1 ; enable timer counter and enable fast timer flags clear bclr TIOS,IOS0 ; enable input-capture 0 movb #$06,TSCR2 ; disable TCNT overflow interrupt, set prescaler to 64 movb #$01,TCTL4 ; capture the rising edge of PT0 signal movb #C0F,TFLG1 ; clear the C0F flag L1: brclr TFLG1,C0F,L1 ; wait for the arrival of the first rising edge ldd TC0 ; save the first edge and clear the C0F flag std edge1 L2: brclr TFLG1,C0F,L2 ; wait for the arrival of the second edge ldd TC0 subd edge1 ; compute the period std period swi 34

35 Example 8.2: C Program for Period Measurement #include "c:\egnu091\include\hcs12.h" void main(void) { unsigned int edge1, period; TSCR1 = 0x90; /* enable timer counter, enable fast flag clear*/ TIOS &= ~IOS0; /* enable input-capture 0 / TSCR2 = 0x06; /* disable TCNT overflow interrupt, set prescaler to 64 */ TCTL4 = 0x01; /* capture the rising edge of the PT0 pin */ TFLG1 = C0F; /* clear the C0F flag */ while (!(TFLG1 & C0F)); /* wait for the arrival of the first rising edge */ edge1 = TC0; /* save the first captured edge and clear C0F flag */ while (!(TFLG1 & C0F)); /* wait for the arrival of the second rising edge */ period = TC0 - edge1; asm ("swi"); } 35

36 Example 8.3: Measure the Pulse Width Write a program to measure the pulse width of a signal connected to the PT0 pin. The E clock frequency is 24 MHz. Solution: Set the prescale factor to TCNT to 32. Use clock cycle as the unit of measurement. (1 1/3 usec time steps) The pulse width may be longer than 2^16 clock cycles (87.4 msec). We need to keep track of the number of times that the TCNT timer overflows. Let ovcnt = TCNT counter overflow count diff = the difference of two consecutive edges edge1 = the captured time of the first edge edge2 = the captured time of the second edge The pulse width can be calculated by the following equations: Case 1: edge2 edge1 pulse width = ovcnt diff Pulse width Case 2: edge2 < edge 1 pulse width = (ovcnt 1) diff Rising edge Falling edge Figure 8.10 Pulse-width measurement using input capture

37 37 no no no Start overflow 0 Set up to capture the rising edge. Disable all interrupts. C0F = 1? yes Clear timer overflow flag. Enable main timer overflow interrupt. Clear C0F flag. Save the first captured edge. C0F = 1? yes Compute the difference of two edges. Is second edge smaller? yes overflow overflow - 1 Combine the results. Timer overflow interrupt service routine Clear TOF flag. overflow overflow + 1. Execute the RTI instruction. Stop Figure 8.17 Logic flow for measuring pulse width of slow signals Example 8.3 Flow Diagram Note: an interrupt is used Return from interrupt TOV interrupt

38 Example 8.3: Code (1) #include "c:\miniide\hcs12.inc".org $1000 edge1:.byte 2 overflow:.byte 2 ; overflow and pulse-width form a 32-bit pulse_width:.byte 2 ; long word for the solution.text _main:: movw #tov_isr,usertimerovf ; set up TCNT overflow interrupt vector lds #$3C00 ; set up stack pointer movw #0, overflow movb #$90, TSCR1 ; enable TCNT and fast timer flag clear movb #$05, TSCR2 ; disable TCNT interrupt, set prescaler to 32 bclr TIOS, IOS0 ; select IC0 movb #$01, TCTL4 ; capture rising edge movb #C0F, TFLG1 ; clear C0F flag wait1: brclr TFLG1,C0F,wait1 ; wait for the first rising edge movw TC0,edge1 ; save the first edge & clear the C0F flag movb #TOF,TFLG2 ; clear TOF flag bset TSCR2,$80 ; enable TCNT overflow interrupt cli ; " movb #$02,TCTL4 ; capture the falling edge on PT0 pin wait2: brclr TFLG1,C0F,wait2 ; wait for the arrival of the falling edge 38

39 Example 8.3: Code (2) next ldd TC0 subd edge1 std pulse_width bcc next ; is the second edge smaller? ldx overflow ; second edge is smaller, so decrement dex ; overflow count by 1 stx overflow ; " swi tov_isr movb #TOF, TFLG2 ; clear TOF flag ldx overflow inx stx overflow rti

40 Example 8.3: C Program for Pulse Width Measurement (1 of 2) #include <hcs12.h> #include <vectors12.h> #define INTERRUPT attribute ((interrupt)) unsigned diff, edge1, overflow; unsigned long pulse_width; void INTERRUPT tovisr(void); void main(void) { UserTimerOvf = (unsigned short)&tovisr; overflow = 0; TSCR1 = 0x90; /* enable timer and fast flag clear */ TSCR2 = 0x05; /* set prescaler to 32, no timer overflow interrupt */ TIOS &= ~IOS0; /* select input-capture 0 */ TCTL4 = 0x01; /* prepare to capture the rising edge */ TFLG1 = C0F; /* clear C0F flag */ while(!(tflg1 & C0F)); /* wait for the arrival of the rising edge */ TFLG2 = TOF; /* clear TOF flag */

41 Example 8.3: C Code (2 of 2) } TSCR2 = 0x80; /* enable TCNT overflow interrupt */ asm("cli"); edge1 = TC0; /* save the first edge */ TCTL4 = 0x02; /* prepare to capture the falling edge */ while (!(TFLG1 & C0F)); /* wait for the arrival of the falling edge */ diff = TC0 - edge1; if (TC0 < edge1) overflow -= 1; pulse_width = overflow * 65536u + diff; asm ("swi"); void INTERRUPT tovisr(void) { TFLG2 = TOF; /* clear TOF flag */ overflow = overflow + 1; } 41

42 Output Compare Function The HCS12 has eight output compare functions. Each output compare channel consists of A 16-bit comparator A 16-bit compare register TCx (also used as input capture register) An output action pin (PTx, can be pulled high, pulled low, or toggled) An interrupt request circuit A forced-compare function (CFOCx) Control logic

43 OUTPUT COMPARE 43

44 Output Compare Function The HCS12 has eight output compare functions. Each output compare channel consists of A 16-bit comparator A 16-bit compare register TCx (also used as input capture register) An output action pin (PTx, can be pulled high, pulled low, or toggled) An interrupt request circuit A forced-compare function (CFOCx) Control logic 2510

45 Operation of the Output-Compare One of the applications of the output-compare function is to trigger an action at a specific time in the future. To use an output-compare function, the user Makes a copy of the current contents of the TCNT register Adds to this copy a value equal to the desired delay Stores the sum into an output-compare register (TCx, x = 0..7) A successful compare will set the corresponding flag bit in the TFLG1 register. An interrupt may be optionally requested if the associated interrupt enable bit in the TIE register is set.

46 Control of the Output-Compare The actions that can be activated on an output compare pin include Pull up to high Pull down to low Toggle The action is determined by the Timer Control Register 1 & 2 (TCTL1 & TCTL2): value OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 after reset value after reset (a) TCTL1 register OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL (b) TCTL2 register read: anytime write: anytime OMn OLn : output level no action (timer disconnected from output pin) toggle OCn pin clear OCn pin to 0 set OCn pin to high Figure 8.18 Timer control register 1 and 2 (TCTL1 & TCTL2)

47 Example 8.4 Output-Compare Example 8.4 Generate an active high 1 KHz digital waveform with 30 percent duty cycle from the PT0 pin. Use the polling method to check the success of the output compare operation. The frequency of the E clock is 24 MHz. Solution: An active high 1 KHz waveform with 30 percent duty cycle is shown in Figure The logic flow of this problem is illustrated in Figure Setting the prescaler to the TCNT to 8, then the period of the clock signal to the TCNT will be 1/3 ms. The numbers of clock cycles that the signal is high and low are 900 and 2100, respectively. 300 s 700 s Figure KHz 30 percent duty cycle waveform 47

48 Example 8.4 Flow Diagram Start Select pull high as pin action Clear C0F flag Start OC0 output compare with a delay of 700 s no C0F = 1? yes Select pull low as pin action Clear C0F flag Start OC0 output compare with a delay of 300 s no C0F = 1? yes Figure 8.20 The program logic flow for digital waveform generation 48

49 Example 8.4 Assembly Code #include "c:\miniide\hcs12.inc" hi_time = 900 lo_time = 2100.text _main:: movb #$90,TSCR1 ; enable TCNT with fast timer flag clear movb #$03,TSCR2 ; disable TCNT interrupt, set prescaler to 8 bset TIOS,OC0 ; enable OC0 movb #$03,TCTL2 ; select pull high as pin action ldd TCNT ; start an OC0 operation with 700 us as delay repeat: addd #lo_time ; " std TC0 ; " low: brclr TFLG1,C0F,low ; wait until OC0 pin go high movb #$02,TCTL2 ; select pull low as pin action ldd TC0 ; start an OC operation with 300 us as delay addd #hi_time ; " std TC0 ; " high: brclr TFLG1,C0F,high ; wait until OC0 pin go low movb #$03,TCTL2 ; select pull high as pin action ldd bra TC0 repeat

50 Example 8.4 C Code #include "c:\egnu091\include\hcs12.h" #define hi_time 900 #define lo_time 2100 void main (void) { TSCR1 = 0x90; /* enable TCNT and fast timer flag clear */ TIOS = OC0; /* enable OC0 function */ TSCR2 = 0x03; /* disable TCNT interrupt, set prescaler to 8 */ TCTL2 = 0x03; /* set OC0 action to be pull high */ TC0 = TCNT + lo_time; /* start an OC0 operation */ while(1) { while(!(tflg1 & C0F)); /* wait for PT0 to go high */ TCTL2 = 0x02; /* set OC0 pin action to pull low */ TC0 += hi_time; /* start a new OC0 operation */ while(!(tflg1 & C0F)); /* wait for PT0 pin to go low */ TCTL2 = 0x03; /* set OC0 pin action to pull high */ TC0 += lo_time; /* start a new OC0 operation */ } }

51 Example 8.5: 1 msec Time Delay Write a function to generate a time delay which is a multiple of 1 ms. Assume that the E clock frequency is 24 MHz. The number of milliseconds is passed in Y. Also write an instruction sequence to test this function. Solution: One method to create 1 ms delay is as follows: Set the prescaler to TCNT to 64 Perform the number of output-compare operations (given in Y) with each operation creating a 1-ms time delay. The number to be added to the copy of TCNT is 375. ( = 1 ms) 51

52 Example 8.5: Y x 1 msec Time Delay Subroutine delayby1ms: pshd movb #$90,TSCR1 ; enable TCNT & fast flags clear movb #$06,TSCR2 ; configure prescaler to 64 bset TIOS,OC0 ; enable OC0 ldd TCNT again0: addd #375 ; start an output-compare operation std TC0 ; with 1 ms time delay wait_lp0: brclr TFLG1,OC0,wait_lp0 ldd TC0 dbne y,again0 puld rts 52

53 Example 8.5: C Code void delayby1ms(int k) { int ix; TSCR1 = 0x90; /* enable TCNT and fast timer flag clear */ TSCR2 = 0x06; /* disable timer interrupt, set prescaler to 64 */ TIOS = OC0; /* enable OC0 */ TC0 = TCNT + 375; for (ix = 0; ix < k; ix++) { while(!(tflg1 & C0F)); TC0 += 375; } TIOS &= ~OC0; /* disable OC0 */ } See Textbook CD: Utilities/delay.c The above is from the old textbook CD 53

54 Textbook Delay Code Delay.asm delayby50us ; multiple passed in Y reg delayby1ms ; multiple passed in Y reg delayby10ms ; multiple passed in Y reg delayby100ms ; multiple passed in Y reg Delay.c void delayby10us(int k); void delayby50us(int k); /* time delay based on */ void delayby1ms(int k); /* 24 MHz E-clock. */ void delayby10ms(int k); void delayby100ms(int k);

55 Example 8.6: Estimate Frequency Use an input-capture and an output-compare functions to measure the frequency of the signal connected to the PT0 pin. Solution: To measure the frequency, we will Use one of the output-compare function to create a one-second time base. Keep track of the number of rising (or falling) edges that arrived at the PT0 pin within one second.

56 Example 8.6: Estimate Frequency (1 of 2) #include "c:\miniide\hcs12.inc" CR = $0D LF = $0A.org $1000 oc_cnt.blkb 1 frequency.blkb 2 msg:.byte CR,LF.ascii The frequency is %d.byte CR,LF,0.org $3E6E ; set up interrupt vector number.word TC0_isr ; for TC0.text _main:: movb #$90,TSCR1 ; enable TCNT and fast timer flags clear movb #$02,TSCR2 ; set prescale factor to 4 movb #$02,TIOS ; enable OC1 and IC0 movb #100,oc_cnt ; prepare to perform 100 OC1 operation, each ; creates 10 ms delay and total 1 second movw #0,frequency ; initialize frequency count to 0 movb #$01,TCTL4 ; prepare to capture the rising edges of PT0 movb #C0F,TFLG1 ; clear the C0F flag bset TIE,IC0 ; enable IC0 interrupt cli ; "

57 Example 8.6: Code (2 of 2) ldd TCNT ; start an OC1 operation with 10 ms delay continue: addd #60000 ; " std TC1 ; " w_lp: brclr TFLG1,C1F, w_lp; wait for 10 ms ldd TC1 dec oc_cnt bne continue sei ; set I, disabling all interrupts ldd frequency pshd ldd #msg ldx #00 jsr [printf, X] leas 2,sp swi TC0_isr: ldd TC0 ; clear C0F flag ldx frequency ; increment frequency count by 1 inx ; " stx frequency ; rti 57

58 Example 8.6: C Code (1 of 2) #include <hcs12.h> #include <vectors12.h> #include <convert.c> #include <stdio.c> #define INTERRUPT attribute ((interrupt)) unsigned int frequency; void INTERRUPT TC0_isr(void); void main(void) { char arr[7]; char *msg = "Signal frequency is "; int i, oc_cnt; unsigned frequency; UserTimerCh0 = (unsigned short)&tc0_isr; TSCR1 = 0x90; /* enable TCNT and fast flag clear */ TSCR2 = 0x02; /* set prescale factor to 4 */ TIOS = 0x02; /* select OC1 and IC0 */ oc_cnt = 100; /* prepare to perform 100 OC1 operations */ frequency = 0;

59 Example 8.6: C Code (2 of 2) TCTL4 = 0x01; /* prepare to capture PT0 rising edge */ TFLG1 = C0F; /* clear C0F flag */ TIE = IC0; /* enable IC0 interrupt */ asm("cli"); TC1 = TCNT ; while (oc_cnt) { while(!(tflg1 & C1F)); TC1 = TC ; oc_cnt = oc_cnt - 1; } asm( sei"); int2alpha(frequency, arr); puts(msg); puts(&arr[0]); asm("swi"); } void INTERRUPT TC0_isr(void) { TFLG1 = C0F; /* clear C0F flag */ frequency ++; }

60 Making Sound Using the Output-Compare Function A sound can be generated by creating a digital waveform with appropriate frequency and using it to drive a speaker or a buzzer. The simplest song is a two-tone siren. HCS12DP F PT5 Buzzer Figure 8.21 Circuit connection for a buzzer 60

61 Example 8.7: Algorithm for Generating a Siren Step 1 Enable an output compare channel to drive the buzzer (or speaker). Step 2 Start an output compare operation with a delay count equal to half the period of the siren and enable the OC interrupt. Step 3 Wait for the duration of the siren tone (say half a second). During the waiting period, interrupts will be requested many times by the output compare function. The interrupt service routine simply restart the output compare operation. Step 4 At the end of the siren tone duration, choose a different delay count for the output compare operation so that the siren sound may have a different frequency. Step 5 Wait for the same duration as in Step 3. During this period, many interrupts will be requested by the output compare operation. Step 6 Go to Step 2. 61

62 Example 8.7 Siren Generation Write a program to generate a two-tone siren that oscillates between 300 Hz and 1200 Hz. Solution: Set the prescaler to TCNT to 1:8. The delay count for the low frequency tone is ( ) = The delay count for the high frequency tone is ( ) =

63 Example 8.7 Siren Generation (1 of 2) #include "c:\miniide\hcs12.inc" hi_freq = 1250 ; delay count for 1200 Hz (with 1:8 prescaler) lo_freq = 5000 ; delay count for 300 Hz (with 1:8 prescaler) toggle = $04 ; value to toggle the TC5 pin.org $1000 delay:.blkw 1 ; store the delay for output-compare operation.text _main:: lds #$3C00 movw #oc5_isr,usertimerch5 ; initialize the interrupt vector entry movb #$90,TSCR1 ; enable TCNT, fast timer flag clear movb #$03,TSCR2 ; set main timer prescaler to 8 bset TIOS,OC5 ; enable OC5 movb #toggle,tctl1 ; select toggle for OC5 pin action movw #hi_freq,delay ; use high frequency delay count first ldd TCNT ; start the low frequency sound addd delay ; " std TC5 ; " bset TIE,OC5 ; enable OC5 interrupt cli 63

64 Code (2 of 2) forever: ldy #5 ; wait for half a second jsr delayby100ms ; " movw #lo_freq, delay ; switch to low frequency delay count ldy #5 jsr delayby100ms movw #hi_freq, delay ; switch to high frequency delay count bra forever oc5_isr: ldd TC5 ; half period of frequency addd delay std TC5 rti #include c:\miniide\delay.asm 64

65 C Program for Siren Generation (1 of 2) #include "c:\egnu091\include\hcs12.h" #include "c:\egnu091\include\delay.c" #define HiFreq 1250 #define LoFreq 5000 int delay; /* delay count for OC5 operation */ int main(void) { asm("cli"); TSCR1 = 0x90; /* enable TCNT and fast timer flag clear */ TSCR2 = 0x03; /* set prescaler to TCNT to 1:8 */ TIOS = BIT5; /* enable OC5 */ TCTL1 = 0x04; /* select toggle for OC5 pin action */ delay = HiFreq; /* use high frequency delay count first */ TC5 = TCNT + delay; /* start an OC5 operation */ TIE = BIT5; /* enable TC5 interrupt */ asm("cli"); 65

66 C Program for Siren Generation (2 of 2) } while(1) { delayby100ms(5); /* wait for half a second */ delay = LoFreq; /* switch to low frequency tone */ delayby100ms(5); /* wait for half a second */ delay = HiFreq; /* switch to high frequency tone */ } return 0; #pragma interrupt_handler oc5_isr void oc5_isr(void) { TC5 += delay; } #pragma abs_address:vtimch5 // Initialize the Interrupt Vector address void (*interrupt_vectors[]) (void) = {oc5_isr}; // Assign the function pointer #pragma end_abs_address // to the ISR 66

67 Preferred Initialization void init_timerch5(void) { TSCR1 = 0x90; /* enable TCNT and fast timer flag clear */ TSCR2 = 0x03; /* set prescaler to TCNT to 1:8 */ TIOS = BIT5; /* enable OC5 */ TCTL1 = 0x04; /* select toggle for OC5 pin action */ TIE = BIT5; /* enable TC5 interrupt */ } Then we have. int main(void) { asm( sei"); init_timerch5(); /* initialize channel 5*/ delay = HiFreq; /* use high frequency delay count first */ TC5 = TCNT + delay; /* start an OC5 operation */ asm("cli"); 67

68 More Timing Capabilities Play The Star-Spangled Banner More digital waveform generation Pulse accumulator operations N pulse event detector Alternate frequency measurement technique Gate time method for measuring a pulse duration Modulus down-counter to generate periodic interrupts See delay.asm from textbook CD 68

69 PWM 69

70 Overview of PWM Functions Many applications require the generation of digital waveform. Output compare function can be used to generate digital waveform but incur too much overhead. Pulse width modulation requires only the initial setup of period and duty cycle for generating the digital waveform. PWM Applications Motor Drive Systems Waveform Generation Periodic Clock Outputs Low Cost Digital to Analog Converter (PWM and a Filter) The PWM shares the eight Port P pins (PWM0 PWM7). 70

71 Pulse Width Modulation (PWM) Each PWM channel has a period register, a duty cycle register, a control register, and a dedicated counter. The clock input to PWM is programmable through a twostage circuitry. There are four possible clock sources for the PWM module: clock A, clock SA, clock B, and clock SB. Clock A and clock B are derived by dividing the E clock by a power of 2. The power can range from 0 to 7. Clock SA is derived by dividing the clock A by an even number ranging from 2 to 512. Clock SB is derived by dividing the clock B by an even number ranging from 2 to

72 Pulse Width Modulation (PWM) Many applications require the generation of digital waveform. Output compare function can be used to generate digital waveform but incur too much overhead. Pulse width modulation requires only the initial setup of period and duty cycle for generating the digital waveform. The MC9S12DP512 has an 8-channel PWM module. 72

73 Pulse Width Modulation (PWM) Each PWM channel has a period register, a duty cycle register, a control register, and a dedicated counter. The clock input to PWM is programmable through a twostage circuitry. There are four possible clock sources for the PWM module: clock A, clock SA, clock B, and clock SB. Clock SA is derived by dividing the clock A by an even number ranging from 2 to 512. Clock SB is derived by dividing the clock B by an even number ranging from 2 to 512. Clock A and clock B are derived by dividing the E clock by a power of 2. The power can range from 0 to 7. 73

74 PWM Block Diagram PWM Module PWM Channels Channel 7 Period and duty Counter PWM7 Bus clock Clock select PWM clock Channel 6 Period and duty Counter PWM6 Control Channel 5 Period and duty Counter PWM5 Channel 4 Enable Period and duty Counter PWM4 Polarity Channel 3 Period and duty Counter PWM3 Alignment Channel 2 Period and duty Counter PWM2 Channel 1 Period and duty Counter PWM1 Channel 0 Period and duty Counter PWM0 Figure 8.38 HCS12 PWM block diagram 74

75 PWM Clock Generation The prescale factors for clock A and clock B are determined by the PCKA2 PCKA0 and PCKB2 PCKB0 bits of the PWMPRCLK register. Clock SA is derived by dividing clock A by the value of the PWMSCLA register and then dividing by 2. Clock SB is derived by dividing clock B by the value of the PWMSCLB register and then dividing by 2. The clock source selection is controlled by the PWMCLK register PCKB2 PCKB1 PCKB0 0 PCKA2 PCKA1 PCKA0 reset: Table 8.3 Clock B prescaler selects Table 8.4 Clock A prescaler selects PCKB2 PCKB1 PCKB0 value of clock B PCKA2 PCKA1 PCKA0 value of clock A E clock E clock/2 E clock/4 E clock/8 E clock/16 E clock/32 E clock/64 E clock/ E clock E clock/2 E clock/4 E clock/8 E clock/16 E clock/32 E clock/64 E clock/128 Figure 8.41 PWM prescale clock select register (PWMPRCLK) 75

76 PWM Clock Source Selection PCLK7 PCLK6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0 reset: PCLKx: PWM channel x clock select (x = 7, 6, 3, 2) 0 = clock B as the clock source 1 = clock SB as the clock source PCLKy: PWM channel y clock select (y = 5, 4, 1, 0) 0 = clock A as the clock source 1 = clock SA as the clock source Figure 8.42 PWM clock select register (PWMCLK) 76

77 PWM Channel Timers The main part of each PWM channel x consists of an 8-bit counter (PWMCNTx), an 8-bit period register (PWMPERx), and an 8-bit duty cycle register (PWMDTYx). The waveform output period is controlled by the match between the PWMPERx register and PWMCNTx register. The waveform output duty cycle is controlled by the match of the PWMDTYx register and the PWMCNTx register. The starting polarity of the output is selectable on a per channel basis by programming the PWMPOL register. A PWM channel must be enabled by setting the proper bit of the PWME register. The overall operation of the PWM module is shown in Figure

78 PWMPOL and PWME PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0 reset: PPOLx: PWM channel x polarity 0 = PWM channel x output is low at the start of a period, then goes high when the duty count is reached. 1 = PWM channel x output is high at the start of a period, then goes low when the duty count is reached. Figure 8.43 PWM polarity register (PWMPOL) PWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0 reset: PWMEx: PWM channel x enable 0 = PWM channel x disabled. 1 = PWM channel x enabled. Figure 8.45 PWM enable register (PWME) 78

79 PWM Channel Block Diagram clock source GATE (clock edge sync) 8-bit counter PWMCNTx From port PTP data register up/ down reset 8-bit compare= PWMDTYx T R Q Q M U X M U X to pin driver 8-bit compare= PPOLx PWMPERx Q Q T R CAEx PWMEx Figure 8.44 PWM channel block diagram 79

80 PWM Waveform Alignment PWM output waveform can be left-aligned or centeraligned. The choice of alignment is controlled by the PWMCAE register CAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0 reset: CAEx: Center aligned enable bit for channel x 0 = PWM channel x output is left aligned 1 = PWM channel x output is center alighed Figure 8.46 PWM center align enable register (PWMCAE) 80

81 Left-Aligned Output The PWMCNTx counter is configured as a count-up counter. PWMx frequency = Clock(A, B, SA, SB frequency) PWMPERx Polarity = 0 PWMx duty cycle = [(PWMPERx PWMDTYx) PWMPERx] 100% Polarity = 1 PWMx duty cycle = [PWMDTYx PWMPERx] 100% PPOLx = 0 PPOLx = 1 PWMDTYx Period = PWMPERx Figure 8.47 PWM left-aligned output waveform 81

82 Center-Aligned Mode PWM counter operates as an up/down counter and is set to count up whenever the counter is equal to $00. When the counter matches the duty register the output flip-flop changes state causing the PWM output to also change state. A match between the PWM counter and the period register changes the counter direction from an up-count to a down-count. When the PWM counter decrements and matches the duty register again, the output flip-flop changes state causing the PWM output to also change state. When the PWM counter decrements to 0, the counter direction changes from a down-count back to an up-count and the period and duty registers are reloaded from their buffers. 82

83 In Aligned Mode PWMx frequency = Clock (A, B, SA, or SB) frequency (2 PWMPERx) When polarity = 0, PWMx duty cycle = [(PWMPERx PWMDTYx) PWMPERx] 100% When polarity = 1, PWMx duty cycle = [PWMDTYx PWMPERx] 100% PPOLx = 0 PPOLx = 1 PWMDTYx PWMDTYx PWMPERx PWMPERx Period = PWMPERx * 2 Figure 8.48 PWM center aligned output waveform 83

84 PWM 16-bit Mode (1 of 2) Two adjacent PWM channels can be concatenated into a 16-bit PWM channel. The concatenation of PWM channels are controlled by the PWMCTL register. The 16-bit PWM system is illustrated in Figure When channel k and k+1 are concatenated, channel k is the high-order channel, whereas channel k+1 is the lower channel. (k is even number). A 16-bit channel outputs from the lower-order channel pin and is also enabled by the lower-order channel. Both left-aligned and center-aligned mode apply to the 16- bit mode. 84

85 PWM 16-bit Mode (2 of 2) CON67 CON45 CON23 CON01 PSWAI PFRZ 0 0 reset: CONjk: concatenate channels j and k (j = 0, 2, 4, or 6; k = j+1) 0 = channel j and k are separate 8-bit PWMs 1 = Channels j and k are concatenated to create one 16-bit PWM channel. Channel j becomes the high order byte and channel k becomes the low order byte. Channel k output pin is used as the output for this 16-bit PWM. Channel k clock select bit determines the clock source, channel k polarity bit determines the polarity, channel k enable bit enables the output and channel k center aligned enable bit determines the output mode. PSWAI: PWM stops in wait mode 0 = allow the clock to the prescaler to continue while in wait mode 1 = stop the input clock to the prescaler whenever the MCU is in wait mode PFRZ: PWM counters stop in freeze mode 0 = allow PWM to continue while in freeze mode 1 = disable PWM input clock to the prescaler whenever the part is in freeze mode. Figure 8.40 PWM control register (PWMCTL) 85

86 PWM 16-bit Block Diagram Clock source 7 high PWMCNT6 low PWMCNT7 Period/Dutycompare PWM7 Clock source 5 high PWMCNT4 low PWMCNT5 Period/Dutycompare PWM5 Clock source 3 high PWMCNT2 low PWMCNT3 Period/Dutycompare PWM3 Clock source 1 high PWMCNT0 low PWMCNT1 Period/Dutycompare PWM1 Figure 8.49 PWM 16-bit mode 86

87 Example 8.21 Write an instruction sequence to generate a 100KHz waveform with 50% duty cycle from the PWM0 pin (PP0). Assume that the E clock frequency is 24 MHz. Solution: Use the following setting: Select clock A as the clock source to PWM0 and set its prescaler to 2. Select left-aligned mode. Load the value 120 into the PWMPER0 register (= ) Load the value 60 into the PWMDTY0 register (= %) #include c:\miniide\hcs12.inc movb #0,PWMCLK ; select clock A as the clock source for PWM0 movb #1,PWMPRCLK ; set clock A prescaler to 2 movb #1,PWMPOL ; channel 0 output high at the start of the period movb #0,PWMCAE ; select left-aligned mode movb #$0C,PWMCTL ; 8-bit mode, stop PWM in wait and freeze mode movb #120,PWMPER0 ; set period value movb #60,PWMDTY0 ; set duty value movb #0,PWMCNT0 ; reset the PWM0 counter bset PWMEN,PWME0 ; enable PWM channel 0 87

88 Example 8.22 Write an instruction sequence to generate a square wave with 20 ms period and 60% duty cycle from PWM0 and use center-aligned mode. Solution: Select clock A as the clock source and set its prescaler to 2. Load the value 120 into PWMPER0 register. PWMPER0 = (20 24,000, ,000) 2 2 = 120 PWMDTY0 = PWMPER0 60% = 72. movb #0,PWMCLK ; select clock A as the clock source movb #1,PWMPOL ; set PWM0 output to start with high level movb #1,PWMPRCLK ; set the PWM0 prescaler to clock A to 2 movb #1,PWMCAE ; select PWM0 center-aligned mode movb #$0C,PWMCTL ; select 8-bit mode, stop PWM in wait mode movb #120,PWMPER0 ; set period value movb #72,PWMDTY0 ; set duty value bset PWME,PWME0 ; enable PWM channel 0 88

89 Example 8.23 Write an instruction sequence to generate a 50 Hz digital waveform with 80% duty cycle using the 16-bit mode from the PWM1 output pin. Solution: Using the following setting: Select clock A as the clock source and set its prescaler to 16. Select left aligned mode and select polarity 1. Load the value into the PWMPER0:PWMPER1 register. Load the value into the PWMDTY0:PWMDTY1 register. movb #0,PWMCLK ; select clock A as the clock source movb #2,PWMPOL ; set PWM0:PWM1 output to start with high level movb #4,PWMPRCLK ; set prescaler to 16 movb #$1C,PWMCTL ; concatenate PWM0:PWM1, stop PWM in wait mode movb #0,PWMCAE ; select left align mode movw #30000,PWMPER0 ; set period to movw #24000,PWMDTY0 ; set duty to bset PWME,PWME1 ; enable PWM0:PWM1 89

90 Example 8.24 Use PWM to dim the light bulb. Assume that we use the PWM0 output to control the brightness of a light bulb. Write a C program to dim the light to 10% brightness gradually in five seconds. The E clock frequency is 24 MHz. Solution: Set duty cycle to 100% at the beginning. Dim the brightness by 10% in the first second and then 20% per second in the following four seconds. Load 100 into the PWMPER0 register at the beginning. Decrement PWMPER0 by 1 every 100 ms during the first second and decrement PWMPER0 by 2 every 100 ms in the following four seconds. #include c:\egnu091\include\hcs12.h #include c:\egnu091\include\delay.c 90

91 C Code void main () { int dim_cnt; PWMCLK = 0; /* select clock A as the clock source */ PWMPOL = 1; /* make waveform to start with high level */ PWMCTL = 0x0C; /* select 8-bit mode */ PWMPRCLK = 2; /* set clock A prescaler to 4 */ PWMCAE = 0; /* select left-aligned mode */ PWMPER0 = 100; /* set period of PWM0 to 0.1 ms */ PWMDTY0 = 100; /* set duty cycle to 100% */ PWME = 0x01; /* enable PWM0 channel */ /* reduce duty cycle 1 % per 100 ms in the first second */ for (dim_cnt = 0; dim_cnt < 10 ; dim_cnt ++) { delayby100ms(1); PWMDTY0--; } /* reduce duty cycle 2% per 100 ms in the next 4 seconds */ for (dim_cnt = 0; dim_cnt < 40; dim_cnt ++) { delayby100ms(1); PWMDTY0 -= 2; } asm ("swi"); } 91

92 DC Motor Control (1 of 4) The DC motor has a permanent magnetic field and its armature is a coil. When a voltage and a subsequent current flow are applied to the armature, the motor begins to spin. The voltage level applied across the armature determines the speed of rotation. Changing the speed requires varying the effective voltage level of the input to the motor. (Use PWM duty cycles) Almost every application that uses a DC motor requires it to reverse its direction of rotation or vary its speed. Reversing the direction is done by changing the polarity of voltage applied to the motor. 92

93 DC Motor Control (2 of 4) Changing the voltage level can be achieved by varying the pulse width of a digital signal input to the DC motor. The HCS12 can interface with a DC motor through a driver as shown in Figure A suitable driver must be selected to take control signals from the HCS12 and deliver the necessary voltage and current to the motor. An example of DC motor driver is shown in Figure The L293 has two supply voltages: VSS and VS. VSS is logic supply and can be from 4.5 to 36V. VS is analog and can be as high as 36 V. 93

94 DC Motor Control (3 of 4) HCS12 PP7 direction PP3 speed on/off Driver DC motor PT0 feedback Figure 8.52 Simplified circuit for DC motor control 94

95 DC Motor Control (4 of 4) V SS CE1 IN1 OUT1 GND GND OUT2 IN2 V S L V SS IN4 OUT4 GND GND OUT3 IN3 CE2 M L M M (a) Pin Assignment V S (b) Motor connection Figure 8.53 Motor driver L293 pin assignment and motor connection 95

96 DC Motor Feedback (1 of 2) The DC motor speed must be fed back to the microcontroller so that it can be controlled. The motor speed can be fed back by using an optical encoder, infrared detector, or a Hall-effect sensor. Basing on the speed feedback, the microcontroller can make adjustment to increase or decrease the speed, reverse the direction, or stop the motor. Assume two magnets are attached to the shaft (rotor) of a DC motor and a Hall-effect transistor is mounted on the armature (stator). As shown in Figure 8.54, every time the Hall-effect transistor passes through the magnetic field, it generates a pulse. The input capture function of the HCS12 can capture the passing time of the pulse. The time between two captures is half of a revolution. Thus the motor speed can be calculated. 96

97 DC Motor Feedback (2 of 2) Magnets Hall-effect transistor t T/2 T is the time for one revolution Figure 8.54 The output waveform of the Hall effect transistor 97

98 A DC Motor Control System (1 of 4) Schematic is shown in The PWM output from the PP3 pin is connected to one end of the motor whereas the PP7 pin is connected to the other end of the motor. The circuit is connected so that the motor will rotate clockwise when the voltage of the PP7 pin is 0 while the PWM output is nonzero (positive). The direction of motor rotation is illustrated in Figure By applying appropriate voltages on PP7 and PP3 (PWM3), the motor can rotate clockwise, counterclockwise, or even stop. 98

99 A DC Motor Control System (2 of 4) Input capture channel 0 is used to capture the feedback from the Halleffect transistor. When a DC motor is first powered, it takes time for the motor to reach its final speed. When a load is added to the motor, it will be slowed down and hence the duty cycle of the PWM3 should be increased to keep the speed constant. When the load is reduced, the speed of the motor will be increased and hence the duty cycle of the PWM3 should be decreased. A DC motor does not respond to the change of the duty cycle instantaneously. Several cycles must be allowed for the microcontroller to determine if the change of the duty cycle has achieved its effect. 99