For reference only Refer to the latest documents for details

Transcription

1 STM32F3 Technical Training For reference only Refer to the latest documents for details

2 General Purpose Timers (TIM2/3/4/5 - TIM12/13/14 - TIM15/16/17 - TIM6/7/18)

3 TIM2/5 TIM3/4/19 TIM12 TIM15 TIM13/14 TIM16/17 TIM6/7/18 STM32F30x Timer features overview 3 Counter resolution Counter Type Prescaler factor DMA Capture Compare channels Synchronization Master config Slave config General purpose TIM2 General purpose TIM3 and TIM4 32 bit 16 bit Up, Down and Up/Down Up, Down and Up/Down YES 4 YES YES YES 4 YES YES Basic TIM6 and TIM7 16 bit Up YES 0 YES NO 1 channel, 1 complementary output TIM16 and TIM17 2 channels, 1 complementary output TIM15 16 bit Up NO 1 YES (1) NO 16 bit Up NO 2 YES YES (1) TIM16 and TIM17 have no TRGO output, instead OC output is used

4 TIM2/5 TIM3/4/19 TIM12 TIM15 TIM13/14 TIM16/17 TIM6/7/18 STM32F37x Timer features overview 4 Counter resolution Counter Type Prescaler factor DMA Capture Compare channels Synchronization Master config Slave config General purpose TIM2 and TIM5 32 bit Up, Down and Up/Down YES 4 YES YES General purpose TIM3, TIM4 and TIM19 16 bit Up, Down and Up/Down YES 4 YES YES Basic TIM6, TIM7 and TIM18 1 channel, 1 complementary output TIM16 and TIM17 2 channels, 1 complementary output TIM15 16 bit Up YES 0 YES NO 16 bit Up NO 1 YES (1) NO 16 bit Up NO 2 YES YES 1 channel TIM13 and TIM14 16 bit Up NO 1 YES (2) NO 2 channels TIM12 16 bit Up NO 2 NO YES (1) TIM16 and TIM17 have no TRGO output, instead OC output is used (2) TIM13 and TIM14 have no TRGO output, instead OC output is used

5 TIM2/5 TIM3/4/19 Features overview (1/3) 5 Up to 4 16-bit resolution Capture Compare channels (TIM3/4/19) ETR Clock ITR 1 ITR 2 ITR 3 ITR 4 Trigger/Clock Controller Trigger Output Up to 4 32-bit resolution Capture Compare channels (TIM2/5) Inter-timers synchronization 16-Bit Prescaler +/- 16/32-Bit Counter Auto Reload REG Up to 6 IT/DMA Requests Encoder Interface Hall sensor Interface CH1 CH2 CH3 Capture Compare Capture Compare Capture Compare Capture Compare CH1 CH2 CH3 CH4 CH4

6 TIM12 TIM15 Features overview (2/3) 6 Up to 2 16-bit resolution Capture Compare channels ETR Clock ITR 1 ITR 2 ITR 3 ITR 4 Trigger/Clock Controller Trigger Output Inter-timers synchronization 16-Bit Prescaler Encoder Interface Auto Reload REG Only TIM15 has complementery output on channel1 CH1 +/- 16/32-Bit Counter CH1 Capture Compare Capture Compare CH1 Comp CH2 CH2

7 TIM2/5 TIM3/4/19 TIM12 TIM15 TIM13/14 TIM16/17 TIM6/7/18 Features overview (3/3) 7 One 16-bit resolution Capture Compare channels ETR Clock ITR 1 ITR 2 ITR 3 ITR 4 Trigger/Clock Controller Trigger Output Only TIM16/17 has complementary output on channel 1 16-Bit Prescaler +/- 16/32-Bit Counter Auto Reload REG CH1 CH1 Capture Compare CH1 Comp

8 TIM2/5 TIM3/4/19 Counting Modes (1/2) 8 There are three counter modes: Up counting mode Down counting mode Center-aligned mode Center Aligned Up counting Down counting Update Event

9 TIM12 TIM15 TIM13/14 TIM16/17 TIM6/7/18 Counting Modes (2/2) 9 There is only one counting mode: Up counting mode Up counting Update Event

10 TIM2/5 TIM3/4/19 TIM12 TIM15 TIM13/14 TIM16/17 Update Event 10 The content of the preload register is transferred into the shadow register depends on the Auto-reload Preload feature if enabled or not If enabled, at each Update Event the transfer occurs If not enabled, the transfer occurs Immediately The Update Event is generated For each counter overflow/underflow Through software, by setting the UG bit (Update Generation) The Update Event (UEV) request source can be configured to be Next to counter overflow/underflow event Nest to Counter overflow/underflow event plus the following events Setting the UG bit by software Trigger active edge detection (through the slave mode controller)

11 TIM2/5 TIM3/4/19 TIM12 TIM15 Counter Clock Selection 11 Clock can be selected out of 8 sources Internal clock TIMxCLK provided by the RCC Internal trigger input 1 to 4: ITR1 / ITR2 / ITR3 / ITR4 Using one timer as prescaler for another timer External Capture Compare pins Pin 1: TI1FP1 or TI1F_ED Pin 2: TI2FP2 External pin ETR TIMxCLK ETR Polarity selection & Edge Detector & Prescaler & Filter Trigger Controller Enable/Disable bit Programable polarity 4 Bits External Trigger Filter External Trigger Prescaler: ITR1 ITR2 ITR3 ITR4 TI1F_ED Controller TRGO Prescaler off Division by 2 Division by 4 TI1FP1 TI2FP2 Division by 8

12 TIM2/5 TIM3/4/19 TIM12 TIM15 TIM13/14 TIM16/17 Capture Compare Array presentation 12 Up to 4 channels TIM2/3/4/5/19 have 4 channels TIM12/15 have 2 channels TIM13/14/16/17 have one channel TIM6/7/18 have no channels Programmable bidirectional channels Input direction: channel configured in Capture mode Output direction: Channel configured in Compare mode Channel s main functional blocs Capture/Compare register Input stage for capture 4-bit digital filter Input Capture Prescaler: Output stage for Compare Output control bloc

13 TIM2/5 TIM3/4/19 Capture stage architecture Input Capture Mode (1/2) 13 TI1 Input Filter & Edge detector TRC IC1 Prescaler 16 bit Capture/Compare 1 Register TI2 Input Filter & Edge detector TRC IC2 Prescaler 16 bit Capture/Compare 2 Register TI3 Input Filter & Edge detector TRC IC3 Prescaler 16 bit Capture/Compare 3 Register TI4 Input Filter & Edge detector TRC IC4 Prescaler 16 bit Capture/Compare 4 Register

14 TIM2/5 TIM3/4/19 Input Capture Mode (2/2) 14 Flexible mapping of TIx inputs to channels inputs ICx {TI1->IC1}, {TI1->IC2}, {TI2->IC1} and {TI2->IC2} are possible When an active Edge is detected on ICx input, the counter value is latched in the corresponding CCR register. When a Capture Event occurs, the corresponding CCXIF flag is set and an interrupt or a DMA request can be sent if they are enabled. An over-capture flag for over-capture signaling Takes place when a Capture Event occurs while the CCxIF flag was already high

15 TIM2/5 TIM3/4/19 TIM12 TIM15 PWM Input Mode 15 Timer Clock IC1 and IC2 must be configured to be connected together to the PWM signal: PWM IC1 and IC2 are redirected internally to be mapped to the same external pin TI1 or TI2. PWM IC1 Counter IC2 IC1 and IC2 active edges must have opposite polarity. IC1 - DUTY CYCLE IC2 - PERIOD IC1 or IC2 is selected as trigger input and the slave mode controller is configured in reset mode. The PWM Input functionality enables the measurement of the period and the pulse width of an external waveform. 6 10

16 TIM2/5 TIM3/4/19 TIM12 TIM15 TIM13/14 TIM16/17 Output Compare Mode 16 The Output Compare is used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the capture/compare register and the counter: The corresponding output pin is assigned to the programmable Mode, it can be: Set Reset Timer Clock OC1 Interrupt Interrupt Toggle Remain unchanged Set a flag in the interrupt status register New CCR1 Generates an interrupt if the corresponding interrupt mask is set CCR1 Send a DMA request if the corresponding enable bit is set The CCRx registers can be programmed with or without preload registers

17 TIM2/5 TIM3/4/19 TIM12 TIM15 TIM13/14 TIM16/17 PWM Mode 17 Available on all channels Two PWM mode available PWM mode 1 PWM mode 2 Each PWM mode behavior (waveform shape) depends on the counting direction Edge-aligned Mode Center-aligned Mode Timer Clock AutoReload Capture Compare Update Event Timer Clock AutoReload Capture Compare Update Event OCx OCx

18 TIM2/5 TIM3/4/19 TIM12 TIM15 TIM13/14 TIM16/17 One Pulse Mode (1/2) 18 TI2 One Pulse Mode (OPM) is a particular case of Output Compare mode It allows the counter to be started in response to a stimulus and to generate a pulse With a programmable length After a programmable delay There are two One Pulse Mode waveforms selectable by software: Single Pulse Repetitive Pulse TIM_ARR TIM_CCR1 OC1REF OC1 t Delay t Pulse t

19 TIM2/5 TIM3/4/19 TIM12 TIM15 TIM13/14 TIM16/17 One Pulse Mode (2/2) 19 Exercise: How to configure One Pulse Mode to generate a repetitive Pulse in response to a stimulus? One Pulse Mode configuration steps 1. Input Capture Module Configuration: i. Map TIxFPx on the corresponding TIx. ii. iii. iv. TIxFPx Polarity configuration. TIxFPx Configuration as trigger input. TIxFPx configuration to start the counter (Trigger mode) 2. Output Compare Module Configuration: i. OCx configuration to generate the corresponding waveform. ii. iii. OCx Polarity configuration. t Delay and t Pulse definition. 3. One Pulse Module Selection: Set or Reset the corresponding bit (OPM) in the Configuration register (CR1).

20 TIM2/5 TIM3/4/19 TIM12 TIM15 Encoders are used to measure position and speed of mobile systems (either linear or angular) Encoder Interface (1/2) 20 The encoder interface mode acts as an external clock with direction selection Encoders and Microcontroller connection example: A can be connected directly to the MCU without external interface logic. The third encoder output which indicates the mechanical zero position, may be connected to an external interrupt and trigger a counter reset. Trigger Controller Controller Encoder Interface Encoder enhancement A copy of the Update Interrupt Flag (UIF) is copied into bit 31 of the counter register Simultaneous read of the Counter value and the UIF flag : Simplify the position determination TI1 TI2 Polarity Select & Edge Controller Polarity Select & Edge Controller

21 TIM2/5 TIM3/4/19 TIM12 TIM15 Exercise: Encoder Interface (2/2) 21 How to configure the Encoder interface to detect the rotation direction of a motion system? Encoder interface configuration steps: 1. Select the active edges: example counting on TI1 and TI2. 2. Select the polarity of each input: example TI1 and TI2 polarity not inverted. 3. Select the corresponding Encoder Mode. 4. Enable the counter.

22 TIM2/5 TIM3/4/19 Hall sensor Interface (1/2) 22 Hall A TI1F_ED Trigger & Slave Mode Controller Hall B Hall C TI1 XOR Input Filter & Edge detector IC1 Prescaler 16 bit Capture/Compare 1 Register TRC TI2 Input Filter & Edge detector TRC IC2 Prescaler 16 bit Capture/Compare 2 Register TI3 Input Filter & Edge detector IC3 Prescaler 16 bit Capture/Compare 3 Register TRC TI4 Input Filter & Edge detector TRC IC4 Prescaler 16 bit Capture/Compare 4 Register

23 TIM2/5 TIM3/4/19 Hall sensor Interface (2/2) 23 Hall sensors are used for: Speed detection Position sensor Brushless DC Motor Sensor How to configure the TIM to interface with a Hall sensor? Select the hall inputs for TI1: TI1S bit in the CR2 register The slave mode controller is configured in reset mode TI1F_ED is used as input trigger To measure a motor speed: Use the Capture/Compare Channel 1 in Input Capture Mode The Capture Signal is the TRC signal The captured value which correspond to the time elapsed between 2 changes on the inputs, gives an information about the motor speed

24 Gated Mode Triggered Mode TIM2/5 TIM3/4/19 TIM12 TIM15 Synchronization Mode Configuration 24 The Trigger Output can be controlled on: Counter reset Counter enable Update event OC1 / OC1Ref / OC2Ref / OC3Ref / OC4Ref signals Clock Master ARR Master CNT Master Trigger Out The slave timer can be controlled in two modes: Triggered mode : only the start of the counter is controlled Gated Mode: Both start and stop of the counter are controlled Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter Slave CNT Clock New Master CCR1 Master CCR1 Master CNT Master CC1 Slave CNT

25 TIM2/5 TIM3/4/19 TIM12 TIM15 Synchronization: Configuration examples (1/3) 25 Cascade mode: TIM3 used as master timer for TIM2 TIM2 configured as TIM3 slave, and master for TIM15 MASTER CLOCK prescaler Timer 3 Trigger Controller TRG 1 counter Update SLAVE / MASTER ITR 1 ITR 3 ITR 4 Timer 2 prescaler Trigger Controller TRG 2 SLAVE counter Update ITR0 Timer 15 ITR2 ITR 4 prescaler counter

26 TIM2/5 TIM3/4/19 TIM12 TIM15 Synchronization: Configuration examples (2/3) 26 One Master several slaves: TIM2 used as master for TIM3, TIM4 and TIM15 CLOCK prescaler counter MASTER Timer 2 Update Trigger Controller TRG1 ITR1 ITR 3 ITR 4 SLAVE 1 Timer 3 prescaler counter SLAVE 2 ITR 3 ITR 2 ITR 4 Timer 4 prescaler counter ITR3 ITR 2 ITR 4 SLAVE 3 TIM15 prescaler counter

27 TIM2/5 TIM3/4/19 TIM12 TIM15 Synchronization: Configuration examples (3/3) 27 Timers and external trigger synchronization TIM2, TIM3 and TIM4 are slaves for an external signal connected to respective Timers inputs TIM2 TIM3 TIM4 Trigger Controller TRGO Trigger Controller TRGO Trigger Controller TRGO External Trigger

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