EIE/ENE 334 Microprocessors

Transcription

1 EIE/ENE 334 Microprocessors Lecture 13: NuMicro NUC140 (cont.) Week #13 : Dejwoot KHAWPARISUTH Adapted from

2 NuMicro NUC140: Technical Ref. Page 2 Week #13 NuMicro NUC130/NUC140 Technical Reference Manual 5 FUNCTIONAL DESCRIPTION 5.1 ARM Cortex -M0 Core 5.2 System Manager 5.3 Clock Controller 5.5 General Purpose I/O (GPIO) 5.6 I2C Serial Interface Controller (Master/Slave) (I2C) 5.7 PWM Generator and Capture Timer (PWM) 5.10 Timer Controller (TMR) 5.11 Watchdog Timer (WDT)

3 NuMicro NUC140: Block Diagram Page 3 Week #13

4 Watchdog Timer (WDT) : Page 4 Week #13 - The purpose of Watchdog Timer is to perform a system reset when system runs into an unknown state - another function -> wake-up chip from power down mode. - The watchdog timer includes an 18-bit free running counter with programmable time-out intervals.

5 WDT : Timing Page 5 Week #13

6 WDT : Block Diagram - User must set WTR (WDTCR [0]) (Watchdog timer reset) high to reset the 18-bit WDT counter to avoid chip from Watchdog timer reset before the delay time expires. WTR bit is cleared automatically by hardware after WDT counter is reset. - WTRF will not be cleared by Watchdog reset. User may poll WTRF by software to recognize the reset source. Page 6 Week #13

7 WDT : WTCR Page 7 Week #13

8 WDT : Program Example Page 8 Week #13

9 Page 9 Week #13 PWM Generator and Capture Timer (PWM) : - 2 groups of PWM supports total 4 sets of PWM Generators which can be configured as 8 independent PWM outputs, PWM0~PWM7, or as 4 complementary PWM pairs, (PWM0, PWM1), (PWM2, PWM3), (PWM4, PWM5) and (PWM6, PWM7) with 4 programmable dead-zone generators - The PWM generators can be configured as one-shot mode to produce only one PWM cycle signal or auto-reload mode to output PWM waveform continuously - PWM Interrupt request synchronized with PWM period

10 PWM : PWM function Page 10 Week #13 - PWM controller is implemented with Dead Zone generator. They are built for power device protection. This function generates a programmable time gap to delay PWM rising output. User can program PPRx.DZI to determine the Dead Zone interval. - When PCR.DZEN01 is set, PWM0 and PWM1 perform complementary PWM paired function; the paired PWM period, duty and dead-time are determined by PWM0 timer and Dead-zone generator 0. Similarly, the complementary PWM pairs of (PWM2, PWM3), (PWM4, PWM5) and (PWM6, PWM7) are controlled by PWM2, PWM4 and PWM6 timers and Dead-zone generator 2, 4 and 6, respectively

11 PWM : Capture Function Page 11 Week #13 - The alternate feature of the PWM-timer is digital input Capture function (PWM output pin is switched as capture input mode) - The Capture0 and PWM0 share one timer which is included in PWM0 and the Capture1 and PWM1 share PWM1 timer, and etc. (Therefore user must setup the PWM-timer before enable Capture feature) - the capture always latched PWM-counter to Capture Rising Latch Register (CRLR) when input channel has a rising transition and latched PWM-counter to Capture Falling Latch Register (CFLR) when input channel has a falling transition - Capture channel 0 interrupt is programmable by setting CCR0.CRL_IE0[1] (Rising latch Interrupt enable) and CCR0.CFL_IE0[2]] (Falling latch Interrupt enable) to decide the condition of interrupt occur. Capture channel 1 has the same feature by setting CCR0.CRL_IE1[17] and CCR0.CFL_IE1[18]. And capture channel 2 to channel 3 on each group have the same feature by setting the corresponding control bits in CCR2. For each group, whenever Capture issues Interrupt 0/1/2/3, the PWM counter 0/1/2/3 will be reload at this moment.

12 PWM : Capture Function Page 12 Week #13 - The maximum captured frequency that PWM can capture is confined by the capture interrupt latency. - When capture interrupt occurred, software will do at least three steps: - Read PIIR to get interrupt source - Read CRLRx/CFLRx(x=0~3) to get capture value - and finally write 1 to clear PIIR to zero. - If interrupt latency will take time T0 to finish, the capture signal mustn t transition during this interval (T0). In this case, the maximum capture frequency will be 1/T0. For example: HCLK = 50 MHz, PWM_CLK = 25 MHz, Interrupt latency is 900 ns So the maximum capture frequency will is 1/900ns 1000 khz

13 PWM : Block Diagram Page 13 Week #13

14 PWM : PWM-Timer Operation Page 14 Week #13 - PWM frequency = PWMxy_CLK/[(prescale+1)*(clock divider)*(cnr+1)]; where xy, could be 01, 23, 45 or 67, depends on selected PWM channel. - Duty ratio = (CMR+1)/(CNR+1) - CMR >= CNR: PWM output is always high - CMR < CNR: PWM low width= (CNR-CMR) unit - PWM high width = (CMR+1) unit - CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit Unit = one PWM clock cycle.

15 PWM : PWM-Timer Operation Timing Page 15 Week #13

16 PWM : PWM-Timer Operation Page 16 Week #13 - PWM Timers have double buffering function the reload value is updated at the start of next period without affecting current timer operation. - The PWM counter value can be written into CNRx and current PWM counter value can be read from PDRx. - PWM0 will operate at one-shot mode if CH0MOD bit is set to 0, and operate at auto-reload mode if CH0MOD bit is set to 1. - It is recommend that switch PWM0 operating mode before set CH0EN bit to 1 to enable PWM0 counter start running because the content of CNR0 and CMR0 will be cleared to zero to reset the PWM0 period and duty setting when PWM0 operating mode is changed.

17 PWM : Timer Start Procedure Page 17 Week #13 1. Setup clock source divider select register (CSR) 2. Setup prescaler (PPR) 3. Setup inverter on/off, dead zone generator on/off, auto-reload/one-shot mode and Stop PWM-timer (PCR) 4. Setup comparator register (CMR) for setting PWM duty. 5. Setup PWM down-counter register (CNR) for setting PWM period. 6. Setup interrupt enable register (PIER) (option) 7. Setup corresponding GPIO pins as PWM function (enable POE and disable CAPENR) for the corresponding PWM channel. 8. Enable PWM timer start running (Set CHxEN = 1 in PCR) The value of CNR0 will reload to PWM0 counter when it down count reaches zero. If CNR0 is set to zero, PWM0 counter will be held. PWM1~PWM7 performs the same function as PWM0.

18 PWM : Program Example Page 18 Week #13

19 PWM : Program Example Page 19 Week #13

20 PWM : Program Example Page 20 Week #13 Ch1: GPA13=PWM1 Ch2: GPA14=PWM2

21 Page 21 Week #13 PWM : Re-Start Procedure in Single-shot mode - As PWM0 operate at one-shot mode, CMR0 and CNR0 should be written first and then set CH0EN bit to 1 to enable PWM0 counter start running. After PWM0 counter down count from CNR0 value to zero, CNR0 and CMR0 will be cleared to zero by hardware and PWM counter will be held. Software need to write new CMR0 and CNR0 value to set next one-shot period and duty. When re-start next one-shot operation, the CMR0 should be written first because PWM0 counter will auto restart counting when CNR0 is written an non-zero value. 1. Setup comparator register (CMR) for setting PWM duty. 2. Setup PWM down-counter register (CNR) for setting PWM period. After setup CNR, PWM wave will be generated.

22 PWM : Stop Procedure Page 22 Week #13 Method 1: Set 16-bit down counter (CNR) as 0, and monitor PDR (current value of 16- bit down-counter). When PDR reaches to 0, disable PWM-Timer (CHxEN in PCR). (Recommended) Method 2: Set 16-bit down counter (CNR) as 0. When interrupt request happened, disable PWM-Timer (CHxEN in PCR). (Recommended)

23 PWM : Capture Operation Page 23 Week #13 CNR is 8: 1. The PWM counter will be reloaded with CNRx when a capture interrupt flag (CAPIFx) is set. 2. The channel low pulse width is (CNR CRLR). 3. The channel high pulse width is (CNR CFLR).

24 PWM : Interrupt Architecture Page 24 Week #13

25 PWM : Capture Start Procedure Page 25 Week #13 1. Setup clock source divider select register (CSR) 2. Setup prescaler (PPR) 3. Setup channel enabled, rising/falling interrupt enable and input signal inverter on/off (CCR0, CCR2) 4. Setup auto-reload mode, Edge-aligned type and Stop PWM-timer (PCR) 5. Setup PWM down-counter (CNR) 6. Enable PWM timer start running (Set CHxEN = 1 in PCR) 7. Setup corresponding GPIO pins as capture function (disable POE and enable CAPENR) for the corresponding PWM channel.

26 PWM : Program Example Page 26 Week #13

27 PWM : Program Example Page 27 Week #13

28 PWM : Register Map Page 28 Week #13

29 I 2 C Serial Interface Controller : Page 29 Week #13 - is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices(master/slave). - There is one SCL clock pulse for each data bit with the MSB being transmitted first. An acknowledge bit follows each transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only during the low period of SCL and must be held stable during the high period of SCL.

30 I 2 C : features Page 30 Week #13 - The I2C port handles byte transfers autonomously. - To enable this port, the bit ENS1 in I2CON should be set to '1'. - The I2C H/W interfaces to the I2C bus via two pins: SDA and SCL. - Pull up resistor is needed for I2C operation as these are open drain pins. When the I/O pins are used as I2C port, user must set the pins function to I2C in advance. - Built-in a 14-bit time-out counter will request the I2C interrupt if the I2C bus hangs up and timer-out counter overflows. - Supports 7-bit addressing mode - When I2C port is enabled by setting ENS1 (I2CON [6]) to high, the internal states will be controlled by I2CON and I2C logic hardware. Once a new status code is generated and stored in I2CSTATUS, the I2C Interrupt Flag bit SI (I2CON [3]) will be set automatically. If the Enable Interrupt bit EI (I2CON [7]) is set high at this time, the I2C interrupt will be generated. The bit field I2CSTATUS[7:3] stores the internal state code, the lowest 3 bits of I2CSTATUS are always zero and the content keeps stable until SI is cleared by software. The base address is 4002_0000 and 4012_0000.

31 I 2 C : Protocol Page 31 Week #13 1) START or Repeated START signal generation 2) Slave address and R/W bit transfer 3) Data transfer 4) STOP signal generation

32 I 2 C : Register Map Page 32 Week #13

33 I 2 C : Data Register (I2CDAT) Page 33 Week #13 - contains a byte of serial data to be transmitted or a byte which just has been received. - The CPU can read from or write to this 8-bit (I2CDAT [7:0]) directly while it is not in the process of shifting a byte. when I2C is in a defined state and the serial interrupt flag (SI) is set. Data in I2CDAT [7:0] remains stable as long as SI bit is set.

34 I 2 C : Control Register (I2CON) Page 34 Week #13

35 I 2 C : Status Register (I2CSTATUS) Page 35 Week #13

36 I 2 C : I2C Clock Baud Rate Bits (I2CLK) Page 36 Week #13 - The data baud rate of I2C is determines by I2CLK [7:0] register when I2C is in a master mode. - The data baud rate of I2C setting is Data Baud Rate of I2C = (system clock) / (4x (I2CLK [7:0] +1)). If system clock = 16 MHz, the I2CLK [7:0] = 40 (28H), so data baud rate of I2C = 16 MHz/ (4x (40 +1)) = 97.5 Kbits/sec.

37 Page 37 Week #13 I 2 C : Time-out Counter Register (I2CTOC) - a 14-bit time-out counter which can be used to deal with the I2C bus hang-up. If the time-out counter is enabled, the counter starts up counting until it overflows (TIF=1) and generates I2C interrupt to CPU or stops counting by clearing ENTI to 0.

38 I 2 C : Address Registers (I2CADDR) Page 38 Week #13 - I2C port is equipped with four slave address registers I2CADDRn (n=0~3). - The I2C hardware will react if the contents of I2CADDRn are matched with the received slave address. - The I2C ports support the General Call function. If the GC bit (I2CADDRn [0]) is set the I2C port hardware will respond to General Call address (00H). Clear GC bit to disable general call function. - I2C bus controllers support multiple address recognition with four address mask registers I2CADMn (n=0~3). When the bit in the address mask register is set to one, it means the received corresponding address bit is don t-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.

39 I 2 C : Program Example Page 39 Week #13

40 I 2 C : Program Example Page 40 Week #13

41 I 2 C : Program Example Page 41 Week #13 Write_24LC64(0x temp,temp+11); // temp = 1

42 I 2 C : Program Example Page 42 Week #13 Write_24LC64(0x temp,temp+11); // temp = 1 DrvI2C_Ctrl(I2C_PORT1, 1, 0, 0, 0);//set start

43 I 2 C : Program Example Page 43 Week #13 Write_24LC64(0x temp,temp+11); // temp = 1 I2C1->I2CDAT = 0xA0; DrvI2C_Ctrl(I2C_PORT1, 0, 0, 1, 0); //clr si flag

44 I 2 C : Program Example Page 44 Week #13 Write_24LC64(0x temp,temp+11); // temp = 1 I2C1->I2CDAT = (address>>8)&0xff; DrvI2C_Ctrl(I2C_PORT1, 0, 0, 1, 1); //clr si and set ack

45 I 2 C : Program Example Page 45 Week #13 Write_24LC64(0x temp,temp+11); // temp = 1 I2C1->I2CDAT = address&0xff; DrvI2C_Ctrl(I2C_PORT1, 0, 0, 1, 1); //clr si and set ack

46 I 2 C : Program Example Page 46 Week #13 Write_24LC64(0x temp,temp+11); // temp = 1 I2C1->I2CDAT = data; DrvI2C_Ctrl(I2C_PORT1, 0, 0, 1, 1); //clr si and set ack

47 I 2 C : Program Example Page 47 Week #13 Write_24LC64(0x temp,temp+11); // temp = 1 DrvI2C_Ctrl(I2C_PORT1, 0, 1, 1, 0); //send stop

48 System Manager : Control Registers Page 48 Week #13

49 Nested Vectored Interrupt Controller: (NVIC) - Nested and Vectored interrupt support - Automatic processor state saving and restoration - Reduced and deterministic interrupt latency - The NVIC prioritizes and handles all supported exceptions. - All exceptions are handled in Handler Mode. - This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority. - All of the interrupts and most of the system exceptions can be configured to different priority levels. - When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the current running one s priority. If the priority of the new interrupt is higher than the current one, the new interrupt handler will override the current handler. - When any interrupts is accepted, the starting address of the interrupt service routine (ISR) is fetched from a vector table in memory. - While the starting address is fetched, NVIC will also automatically save processor state including the registers PC, PSR, LR, R0~R3, R12 to the stack. At the end of the ISR, the NVIC will restore the mentioned registers from stack and resume the normal execution. Page 49 Week #13

50 NVIC: Exception Model Page 50 Week #13

51 NVIC: System Interrupt Map Page 51 Week #13

52 NVIC: Control Registers Page 52 Week #13