SPI/MICROWIRE-Compatible UART and ±15kV ESD- Protected RS-232 Transceivers with Internal Capacitors PART MAX3110ECNI

Transcription

1 ; Rev ; 7/99 SPI/MICROWIRE-Compatible UART and ±15k ESD- General Description The MAX311E/MAX3111E combine a full-featured universal asynchronous receiver/transmitter (UART) with ±15k ESD-protected RS-232 transceivers and integrated charge-pump capacitors into a single 28-pin package for use in space-, cost-, and power-constrained applications. The MAX311E/MAX3111E also feature an SPI /QSPI /MICROWIRE -compatible serial interface to save additional board space and microcontroller (µc) I/O pins. A proprietary low-dropout output stage enables the 2-driver/2-receiver interface to deliver true RS-232 performance down to CC = +3 (+4.5 for MAX311E) while consuming only 6µA. The receivers remain active in a hardware/software-invoked shutdown, allowing external devices to be monitored while consuming only 1µA. Each device is guaranteed to operate at up to 23kbps while maintaining true EIA/TIA-232 output voltage levels. The MAX311E/MAX3111E s UART includes a crystal oscillator and baud-rate generator with software-programmable divider ratios for all common baud rates from 3baud to 23kbaud. The UART features an 8- word-deep receive FIFO that minimizes processor overhead and provides a flexible interrupt with four maskable sources. Two control lines (one input and one output) are included for hardware handshaking. The UART and RS-232 functions can be used together or independently since the two functions share only supply and ground connections (the MAX311E/ MAX3111E are hardware- and software-compatible with the MAX31 and MAX3222E). Applications Point-of-Sale (POS) Devices Handy-Terminals Telecom/Networking Diagnostic Ports Industrial Front-Panel Interfaces Hand-Held/Battery-Powered Equipment Pin Configuration appears at end of data sheet. Covered by U.S. Patent numbers 4,636,93; 4,679,134; 4,777,577; 4,797,899; 4,89,152; 4,897,774; 4,999,761; and other patents pending. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Features Integrated RS-232 Transceiver and UART in a Single 28-Pin Package SPI/QSPI/MICROWIRE-Compatible µc Interface Internal Charge-Pump Capacitors No External Components Required! True RS-232 Operation Down to CC = +3 (MAX3111E) ESD Protection for RS-232 I/O Pins ±15k Human Body Model ±8k IEC 1-4-2, Contact Discharge ±15k IEC 1-4-2, Air-Gap Discharge Single-Supply Operation +5 (MAX311E) +3.3 (MAX3111E) Low Power 6µA Supply Current 1µA Shutdown Supply Current with Receiver Interrupt Active Guaranteed 23kbps Data Rate Hardware/Software-Compatible with MAX31 and MAX3222E PART MAX311ECWI MAX311ECNI µp Typical Application Circuit SPI CS SCLK DIN DOUT IRQ Ordering Information TEMP. RANGE C to +7 C C to +7 C Ordering Information continued at end of data sheet. MAX311E MAX3111E RS-232 PIN- PACKAGE 28 Wide SO 28 Plastic DIP DB-9 CC () 5 5 U A R T MAX311E/MAX3111E Maxim Integrated Products 1 For free samples & the latest literature: or phone For small orders, phone

2 MAX311E/MAX3111E ABSOLUTE MAXIMUM RATINGS CC to GND (MAX311E) to +6 CC to GND (MAX3111E) to +4 + to GND (Note 1) to +7 - to GND (Note 1) to -7 + to - (Note 1) Input oltages to GND CS, X1, CTS, RX, DIN, SCLK to ( CC +.3) T_IN, SHDN to +6 R_IN...±25 Output oltage to GND DOUT, RTS, TX, X to ( CC +.3) IRQ to +6 T_OUT...±13.2 R_OUT to ( CC +.3) TX, RTS Output Current...1mA Short-Circuit Duration X2, DOUT, IRQ (to CC or GND)...Continuous T_OUT (to GND)...Continuous Continuous Power Dissipation (T A = +7 C) 28-pin Wide SO (derate 12.5mW/ C above +7 C)...1W 28-pin Plastic DIP (derate 14.3mW/ C above +7 C) W Operating Temperature Ranges MAX311_EC... C to +7 C MAX311_EE...-4 C to +85 C Storage Temperature Range C to +15 C Lead Temperature (soldering, 1sec)...+3 C Note 1: + and - can have maximum magnitudes of 7, but their absolute difference should not exceed 13. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS MAX311E ( CC = +4.5 to +5.5, T A = T MIN to T MAX, unless otherwise noted. Typical values are measured for baud rate set to 96baud at CC = +5, T A = +25 C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC CHARACTERISTICS ( CC = +5, T A = +25 C) Supply Current I CC SHDN = CC, no load.6 2 ma Supply Current with Hardware Shutdown I CCSHDN(H) SHDN = GND (Note 3).48 1 ma Supply Current with Hardware and Software Shutdown I CCSHDN(H+ S) SHDN = GND, SHDNi bit = 1 (Note 4) 3 2 µa UART OSCILLATOR INPUT (X1) Input High oltage IH1.7 CC Input Low oltage IL1.2 CC Input Current I IN1 X1 = or 5.5 SHDNi bit = 25 SHDNi bit = 1 2 µa Input Capacitance C IN1 5 pf UART LOGIC INPUTS (DIN, SCLK, CS, CTS, RX) Input High oltage IH2.7 CC Input Low oltage IL2.3 CC Input Hysteresis HYST2 25 m Input Leakage Current I LKG1 ±1 µa Input Capacitance C IN2 5 pf RS-232 LOGIC INPUTS (T_IN, SHDN) Input High oltage IH3 CC = Input Low oltage IL3.8 Transmitter Input Hysteresis HYST3 5 m Input Leakage Current I IN3 ±.1 ±1 µa 2

3 ELECTRICAL CHARACTERISTICS MAX311E (continued) ( CC = +4.5 to +5.5, T A = T MIN to T MAX, unless otherwise noted. Typical values are measured for baud rate set to 96baud at CC = +5, T A = +25 C.) (Note 2) PARAMETER RS-232 RECEIER INPUTS (R_IN) Input oltage Range Input High oltage Input Low oltage Input Hysteresis Input Resistance SYMBOL IH4 IL4 HYST4 R IN RS-232 ESD PROTECTION (R_IN, T_OUT) ESD Protection RS-232 RECEIER OUTPUTS (R_OUT) T A = +25 C CONDITIONS T A = +25 C, CC = 5 T A = +25 C, CC = 5 IEC Air Discharge IEC Contact Discharge MIN TYP MAX Output High oltage OH1 IReceivers SOURCE = disabled 1mA CC -.6 ±.5 ±1 µa Output Low oltage OL1 I SINK = 1.6mA.4 RS-232 TRANSMITTER OUTPUTS (T_OUT) Output oltage Swing 3kΩ load on all transmitter outputs 5 ±5.4 Output Resistance R O CC = + = - =, OUT = ±2 3 1M Ω Output Short-Circuit Current ±6 ma Output Leakage Current I CC = or 5.5, OUT = ±12, LKG2 ±25 µa transmitters disabled ±25 UART OUTPUTS (DOUT, TX, RTS) Output Leakage Current I LKG3 DOUT only, CS = CC ±1 µa Output High oltage OH2 I SOURCE = 5mA; DOUT, RTS CC -.5 I SOURCE = 1mA; TX only CC -.5 Output Low oltage I SINK = 4mA; DOUT, RTS.4 OL2 I SINK = 25mA; TX only.9 Output Capacitance C OUT1 5 pf UART IRQ OUTPUTS (IRQ = open drain) Output Leakage Current I LKG4 IRQ = 5.5 ±1 µa Output Low oltage OL3 I SINK = 4mA.4 Output Capacitance C OUT2 5 pf UART AC TIMING Human Body Model CS Low to DOUT alid t D C LOAD = 1pF 1 ns CS High to DOUT Tri-State t TR C LOAD = 1pF, R CS = 1kΩ 1 ns CS to SCLK Setup Time t CSS 1 ns CS to SCLK Hold Time t CSH ns SCLK Fall to DOUT alid t DO C LOAD = 1pF 1 ns ±15 ±15 ±8 UNITS m kω k MAX311E/MAX3111E 3

4 MAX311E/MAX3111E ELECTRICAL CHARACTERISTICS MAX311E (continued) ( CC = +4.5 to +5.5, T A = T MIN to T MAX, unless otherwise noted. Typical values are measured for baud rate set to 96baud at CC = +5, T A = +25 C.) (Note 2) PARAMETER DIN to SCLK Setup Time DIN to SCLK Hold Time SCLK Period SCLK High Time SCLK Low Time SCLK Rising Edge to CS Falling CS Rising Edge to SCLK Rising Edge CS High Pulse Width Output Rise Time Output Fall Time RS-232 AC TIMING SYMBOL t DS t DH t CP t CH t CL t CS t CS1 t CSW t r t f CONDITIONS TX, RTS, DOUT; C L = 1pF TX, RTS, DOUT, IRQ; C L = 1pF C L = 15pF to 25pF MIN TYP MAX UNITS ns ns ns ns ns ns Maximum Data Rate R L = 3kΩ, C L = 1pF, one transmitter switching 25 kbps Receiver Propagation Delay t PHL Receiver input to receiver output 15 t PLH C L = 15pF 15 ns Transmitter Skew t PHL - t PLH (Note 5) 1 ns Receiver Skew t PHL - t PLH 5 ns Transition-Region Slew Rate CC = 5, R L = 3kΩ to 7kΩ, T A = +25 C, measured from +3 to -3 or -3 to +3 C L = 15pF to 1pF 6 3 ns ns ns ns /µs 4

5 ELECTRICAL CHARACTERISTICS MAX3111E ( CC = +3. to +3.6, A = T MIN to T MAX, unless otherwise noted. Typical values are measured for baud rate set to 96baud at CC = +3.3, T A = +25 C.) (Note 2) PARAMETER SYMBOL CONDITIONS DC CHARACTERISTICS ( CC = 3.3, T A = +25 C) Supply Current I CC SHDN = CC, no load Supply Current with Hardware Shutdown Supply Current with Hardware and Software Shutdown UART OSCILLATOR INPUT (X1) Input High oltage Input Low oltage Input Current I CCSHDN(H) I CCSHDN(H+ S) IH1 IL1 I IN1 Input Capacitance C IN1 UART LOGIC INPUTS (DIN, SCLK, CS, RX) Input High oltage IH2 Input Low oltage IL2 Input Hysteresis HYST2 Input Leakage Current I LKG1 Input Capacitance C IN2 RS-232 LOGIC INPUTS (T_IN, SHDN) Input High oltage IH3 Input Low oltage IL3 Transmitter Input Hysteresis HYST3 Input Leakage Current I IN3 RS-232 RECEIER INPUTS (R_IN) Input oltage Range Input High oltage IH4 Input Low oltage IL4 Input Hysteresis HYST4 Input Resistance R IN RS-232 ESD PROTECTION (R_IN, T_OUT) SHDN = GND (Note 3) SHDN = GND SHDNi bit = 1 (Note 4) Human Body Model MIN TYP MAX.7 CC CC.2 CC X1 = or 3.6 SHDNi bit = 25 SHDNi bit = 1 2 µa 5 pf CC = 3.3 T A = +25 C, CC = 3.3 T A = +25 C, CC = 3.3 T A = +25 C CC ±1.8 5 ±.1 ± ESD Protection IEC Air Discharge ±15 ±15 IEC Contact Discharge ±8 UNITS ma ma µa m µa pf m µa m kω k MAX311E/MAX3111E 5

6 MAX311E/MAX3111E ELECTRICAL CHARACTERISTICS MAX3111E (continued) ( CC = +3. to +3.6, A = T MIN to T MAX, unless otherwise noted. Typical values are measured for baud rate set to 96baud at CC = +3.3, T A = +25 C.) (Note 2) PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS RS-232 RECEIER OUTPUTS (R_OUT) Output High oltage OH1 I SOURCE = 1mA CC -.6 Output Low oltage OL1 I SINK = 1.6mA.4 RS-232 TRANSMITTER OUTPUTS (T_OUT) Output oltage Swing 3kΩ load on all transmitter outputs ±5 ±5.4 Output Resistance R O CC = + = - =, OUT = ±2 3 1M Ω Output Short-Circuit Current ±6 ma Output Leakage Current I LKG2 CC = or 3.6, OUT = ±12, transmitters disabled ±25 µa UART OUTPUTS (DOUT, TX, RTS) Output Leakage Current I LKG3 DOUT only; CS = CC ±1 µa Output High oltage OH2 I SOURCE = 5mA; DOUT, RTS CC -.5 I SOURCE = 1mA, TX only CC -.5 Output Low oltage I SINK = 4mA; DOUT, RTS.4 OL2 I SINK = 25mA, TX only.9 Output Capacitance C OUT1 5 pf UART IRQ OUTPUT (IRQ = open drain) Output Leakage Current I LKG4 IRQ = 3.6 ±1 µa Output Low oltage OL3 I SINK = 4mA.4 Output Capacitance C OUT2 5 pf UART AC TIMING CS Low to DOUT alid t D C LOAD = 1pF 1 ns CS High to DOUT Tri-State t TR C LOAD = 1pF, R CS = 1kΩ 1 ns CS to SCLK Setup Time t CSS 1 ns CS to SCLK Hold Time t CSH ns SCLK Fall to DOUT alid t DO C LOAD = 1pF 1 ns DIN to SCLK Setup Time t DS 1 ns DIN to SCLK Hold Time t DH ns SCLK Period t CP 238 ns SCLK High Time t CH 1 ns SCLK Low Time t CL 1 ns SCLK Rising Edge to CS Falling t CS 1 ns CS Rising Edge to SCLK Rising Edge t CS1 2 ns CS High Pulse Width t CSW 2 ns Output Rise Time t r TX, RTS, DOUT; C LOAD = 1pF 1 ns Output Fall Time t f TX, RTS, DOUT, IRQ; C LOAD = 1pF 1 ns 6

7 ELECTRICAL CHARACTERISTICS MAX3111E (continued) ( CC = +3. to +3.6, A = T MIN to T MAX, unless otherwise noted. Typical values are measured for baud rate set to 96baud at CC = +3.3, T A = +25 C.) (Note 2) PARAMETER RS-232 AC TIMING Maximum Data Rate Receiver Propagation Delay Transmitter Skew Receiver Skew Transition-Region Slew Rate SYMBOL t PHL t PLH t PHL - t PLH t PHL - t PLH R L = 3kΩ, C L = 1pF, one-transmitter switching Receiver input to receiver output C L = 15pF (Note 5) CC = 3.3, R L = 3kΩ to 7kΩ, T A = +25 C, measured from +3 to -3 or -3 to +3 CONDITIONS C L = 15pF to 1pF C L = 15pF to 25pF MIN TYP MAX Note 2: All currents into the device are positive; all currents out of the device are negative. All voltages are referred to device ground unless otherwise noted. Note 3: I CCSHDN(H) represents a hardware-only shutdown. In hardware shutdown, the UART is in normal operation and the charge pumps for the RS-232 transmitters are shut down. Note 4: I CCSHDN(H+S) represents a simultaneous software and hardware shutdown in which the UART and charge pumps are shut down. Note 5: Transmitter skew is measured at the transmitter zero cross points UNITS kbps ns ns ns ns /µs MAX311E/MAX3111E 7

8 MAX311E/MAX3111E (T A = +25 C, unless otherwise noted.) SUPPLY CURRENT (µa) SUPPLY CURRENT (µa) UART SUPPLY CURRENT vs. TEMPERATURE MHz CRYSTAL 9 TRANSMITTING AT 115.2kbps MAX311E, CC = +5 MAX3111E, CC = TEMPERATURE ( C) UART SUPPLY CURRENT vs. EXTERNAL CLOCK FREQUENCY MAX311E CC = +5 MAX3111E CC = +3.3 MAX311E-1 MAX311E-4 SHUTDOWN CURRENT (µa) OUTPUT SINK CURRENT (ma) UART SHUTDOWN CURRENT vs. TEMPERATURE MHz CRYSTAL TEMPERATURE ( C) Typical Operating Characteristics MAX3111E, CC = +3.3 MAX311E, CC = +5 MAX311E TX, RTS, DOUT OUTPUT CURRENT vs. OUTPUT LOW OLTAGE ( CC = +5) RTS DOUT TX MAX311E-2 MAX311E-6 SUPPLY CURRENT (µa) OUTPUT SINK CURRENT (ma) MHz CRYSTAL UART SUPPLY CURRENT vs. BAUD RATE MAX311E +3 TRANSMITTING +5 TRANSMITTING MAX3111E +5 STANDBY +3 STANDBY 1 1 1k 1k 1M BAUD RATE (bps) MAX3111E TX, RTS, DOUT OUTPUT CURRENT vs. OUTPUT LOW OLTAGE ( CC = +3.3) RTS DOUT TX MAX311E-3 MAX311E EXTERNAL CLOCK FREQUENCY (MHz) OLTAGE () OLTAGE () TRANSMITTER OUTPUT OLTAGE () RS-232 TRANSMITTER OUTPUT OLTAGE vs. LOAD CAPACITANCE TRANSMITTER 1 AT 25kbps TRANSMITTER 2 AT 15.6kbps 3kΩ + C L OUT+ OUT- MAX311E/TOC7 SUPPLY CURRENT (ma) RS-232 TRANSCEIER SUPPLY CURRENT vs. LOAD CAPACITANCE TRANSMITTER 1 AT DATA RATE TRANSMITTER 2 AT DATA RATE 3kΩ + C L 16 25kbps 12kbps 2kbps MAX311E/TOC9 SLEW RATE (/µs) RS-232 TRANSMITTER SLEW RATE vs. LOAD CAPACITANCE -SLEW TRANSMITTER 1 AT 25kbps 3kΩ + C L +SLEW MAX311E/TOC LOAD CAPACITANCE (pf) LOAD CAPACITANCE (pf) LOAD CAPACITANCE (pf) 8

9 PIN NAME R2IN R2OUT T2IN T1IN R1OUT R1IN T1OUT CC X2 X1 CTS RTS RS-232 Receiver Input 2 RS-232 Receiver Output 2, TTL/CMOS RS-232 Transmitter lnput 2, TTL/CMOS RS-232 Transmitter lnput 1, TTL/CMOS RS-232 Receiver Output 1, TTL/CMOS RS-232 Receiver Input 1 RS-232 Transmitter Output 1 Positive Supply oltage FUNCTION Pin Description UART Crystal Connection. Leave X2 unconnected when using an external CMOS clock. See the Crystals, Oscillators, and Ceramic Resonators section. UART Crystal Connection. X1 also serves as an external CMOS clock input. See the Crystals, Oscillators, and Ceramic Resonators section. UART Clear-to-Send Active-Low Input. Read via the CTS bit. UART Request-to-Send Active-Low Output. Controlled by the RTS bit. Also used to control the driver enable in RS-485 networks. MAX311E/MAX3111E 13 RX UART Asynchronous Serial-Data (receiver) Input. The serial information received from the RS-232 receiver. A transition on RX while in shutdown generates an interrupt (Table 1). 14 TX UART Asynchronous Serial-Data (transmitter) Output 15 DIN SPI/MICROWIRE Serial-Data Input. Schmitt-trigger Input. 16 DOUT SPI/MICROWIRE Serial-Data Output. High impedance when CS is high. 17 SCLK SPI/MICROWIRE Serial-Clock Input. Schmitt-trigger input. 18 CS UART Active-Low Chip-Select Input. DOUT goes high impedance when CS is high. IRQ, TX, and RTS are always active. Schmitt-trigger input. 19 IRQ UART Active-Low Interrupt Output. Open-drain interrupt output to microprocessor. 2 SHDN Hardware Shutdown Input. Drive SHDN low to shut down the RS-232 transmitters and charge pump. Drive high for normal operation generated by the internal charge pump. Do not make any connection to this terminal. 22 C1+ Positive terminal of the internal voltage-doubler charge-pump capacitor. Do not make any connection to this terminal. 23 C1- Negative terminal of the internal voltage-doubler charge-pump capacitor. Do not make any connection to this terminal. 24 C2+ Positive terminal of internal inverting charge-pump capacitor. Do not make any connection to this terminal. 25 C2- Negative terminal of internal inverting charge-pump capacitor. Do not make any connection to this terminal generated by the internal charge pump. Do not make any connection to this terminal. 27 GND Ground 28 T2OUT RS-232 Transmitter Output 2 9

10 MAX311E/MAX3111E T2IN T1IN R2OUT R1OUT C1+ C1- C2+ C2- CC Pr INTERNAL INTERNAL RX BUFFER 9 CHARGE PUMP INTERNAL 5k 5k INTERNAL MAX311E/MAX3111E T2OUT T1OUT R2IN R1IN + GND - SHDN 9 9 Pr RX FIFO INTERRUPT LOGIC IRQ RX Pr 9 RX SHIFT REGISTER 9 DOUT X2 X1 TX CTS RTS Pt Pt I/O BAUD-RATE GENERATOR TX SHIFT REGISTER 9 TX BUFFER 9 4 SPI INTERFACE SCLK CS DIN Figure 1. MAX311E/MAX3111E Functional Diagram Detailed Description The MAX311E/MAX3111E contain an SPI/QSPI/MICROWIREcompatible UART and an RS-232 transceiver with two drivers and two receivers. The UART is compatible with SPI and QSPI for CPOL = and CPHA =. The UART supports data rates up to 23kbaud for standard UART bit streams as well as IrDA and includes an 8-word receive FIFO. Also included is a 9-bit-address recognition interrupt. The RS-232 transceiver has electrostatic discharge (ESD) protection on the transmitter outputs and the receiver inputs. The internal charge-pump capacitors minimize the number of external components required. The RS-232 transceivers meet EIA/TIA-232 specifications for CC down to the minimum supply voltage and are guaranteed to operate for data rates up to 25kbps. The UART and RS-232 functions operate as one device or independently since the two functions share only supply and ground connections. UART The universal asynchronous receiver transmitter (UART) interfaces the SPI/QSPI/MICROWIRE-compatible synchronous serial data from a microprocessor (µp) to asynchronous, serial-data communication ports (RS- 232, IrDA). Figure 1 shows the MAX311E/MAX3111E functional diagram. Included in the UART function is an SPI/QSPI/MICROWIRE interface, a baud-rate generator, and an interrupt generator. 1

11 SPI Interface The MAX311E/MAX3111E are compatible with SPI, QSPI (CPOL =, CPHA = ), and MICROWIRE serialinterface standards (Figure 2). The MAX311E/ MAX3111E have a unique full-duplex-only architecture that expects a 16-bit word for DIN and simultaneously produces a 16-bit word for DOUT regardless of which read/write register is used. The DIN stream is monitored for its first two bits to tell the UART the type of data transfer being executed (see the Write Configuration Register, Read Configuration Register, Write Data Register, and Read Data Register sections). DIN (MOSI) is latched on SCLK s rising edge. DOUT (MISO) should be read into the µp on SCLK s rising edge. The first bit (bit 15) of DOUT transitions on CS s falling edge, and bits 14 transition on SCLK s falling DIN MSB LSB DOUT MSB LSB edge. Figure 3 shows the detailed serial timing specifications for the synchronous SPI port. Only 16-bit words are expected. If CS goes high in the middle of a transmission (any time before the 16th bit), the sequence is aborted (i.e., data does not get written to individual registers). Most operations, such as the clearing of internal registers, are executed only on CS s rising edge. Every time CS goes low, a new 16-bit stream is expected. An example of using the Write Configuration Register is shown in Figure 4. Table 1 describes the bits located in the Write Configuration, Read Configuration, Write Data, and Read Data Registers. This table also describes whether the bit is a read or a write bit and the power-on reset state (POR) of the bits. Figure 5 shows an example of parity and word-length control. MAX311E/MAX3111E CS SCLK SCLK SCLK SCLK (CPOL =, CPHA = ) (CPOL =, CPHA = 1) (CPOL = 1, CPHA = ) (CPOL = 1, CPHA = 1) COMPATIBLE WITH MAX311E/MAX3111E NOT COMPATIBLE WITH MAX311E/MAX3111E Figure 2. Compatible CPOL and CPHA Timing Modes CS SCLK t CSO t CSS t CL t DS t DH t CH t CSH t CS1 DIN t D t DO t TR DOUT Figure 3. Detailed Serial Timing Specifications for the Synchronous SPI Port 11

12 MAX311E/MAX3111E CS SCLK DIN DOUT FEN SHDN TM RM PM RAM IR ST PE L B3 B2 B1 B R T Figure 4. Write Configuration Register Example DATA UPDATED IDLE IDLE IDLE IDLE TIME PE =, L = START D D1 D2 D3 D4 D5 D6 D7 STOP STOP IDLE PE =, L = 1 START D D1 D2 D3 D4 D5 D6 STOP STOP IDLE PE = 1, L = START D D1 D2 D3 D4 D5 D6 D7 Pt STOP STOP IDLE PE = 1, L = 1 START D D1 D2 D3 D4 D5 D6 Pt STOP STOP IDLE SECOND STOP BIT IS OMITTED IF ST =. Figure 5. Parity and Word-Length Control 12

13 Table 1. Bit Descriptions BIT NAME POR STATE DESCRIPTION B B3 write Baud-Rate Divisor Select Bits. Sets the baud clock s value (Table 6). B B3 read Baud-Rate Divisor Select Bits. Reads the 4-bit baud clock value assigned to these registers. CTS Dt D7t Dr D7r IR read Reads the value of the IR bit. L BIT TYPE read write read write No change XXXXXXXX L read Reads the value of the L bit. Clear-to-Send-Input. Records the state of the CTS pin (CTS bit = implies CTS pin = logic high). Transmit-Buffer Register. Eight data bits written into the transmit-buffer register. D7t is ignored when L = 1. Eight data bits read from the receive FIFO or the receive-buffer register. When L = 1, D7r is always. FEN write FIFO Enable. Enables the receive FIFO when FEN =. When FEN = 1, FIFO is disabled. FEN read FIFO-Enable Readback. FEN s state is read. IR write Enables the IrDA timing mode when IR = 1. Bit to set the word length of the transmitted or received data. L = results in 8-bit words (9-bit words if PE = 1) (see Figure 5). L = 1 results in 7-bit words (8-bit words if PE = 1). MAX311E/MAX3111E Pt write X Transmit-Parity Bit. This bit is treated as an extra bit that is transmitted if PE = 1. In 9-bit networks, the MAX311E/MAX3111E do not calculate parity. If PE =, then this bit (Pt) is ignored in transmit mode (see the 9-Bit Networks section). Pr read X Receive-Parity Bit. This bit is the extra bit received if PE = 1. Therefore, PE = 1 results in 9-bit transmissions (L = ). If PE =, then Pr is set to. Pr is stored in the FIFO with the receive data (see the 9-Bit Networks section). PE write Parity-Enable Bit. Appends the Pt bit to the transmitted data when PE = 1, and sends the Pt bit as written. No parity bit is transmitted when PE =. With PE = 1, an extra bit is expected to be received. This data is put into the Pr register. Pr = when PE =. The MAX311E/MAX3111E do not calculate parity. PE read Reads the value of the Parity-Enable bit. PM write Mask for Pr bit. IRQ is asserted if PM = 1 and Pr = 1 (Table 7). PM read Reads the value of the PM bit (Table 7). R read Receive Bit or FIFO Not Empty Flag. R = 1 means new data is available to be read or is being read from the receive register or FIFO. If performing a Read Data or Write Data operation, the R bit will clear on the falling edge of SCLK's 16th pulse if no new data is available. RM write Mask for R bit. IRQ is asserted if RM = 1 and R = 1 (Table 7). RM read Reads the value of the RM bit (Table 7). RAM write Mask for RA/FE bit. IRQ is asserted if RAM = 1 and RA/FE = 1 (Table 7). RAM read Reads the value of the RAM bit (Table 7). RTS write Request-to-Send Bit. Controls the state of the RTS output. This bit is reset on power-up (RTS bit = sets the RTS pin = logic high). 13

14 MAX311E/MAX3111E Table 1. Bit Descriptions (continued) BIT NAME BIT TYPE POR STATE DESCRIPTION RA/FE read Receiver-Activity/Framing-Error Bit. In shutdown mode, this is the RA bit. In normal operation, this is the FE bit. In shutdown mode, a transition on RX sets RA = 1. In normal mode, a framing error sets FE = 1. A framing error occurs if a zero is received when the first stop bit is expected. FE is set when a framing error occurs, and cleared upon receipt of the next properly framed character independent of the FIFO being enabled. When the device wakes up, it is likely that a framing error will occur. This error is cleared with a Write Configuration. The FE bit is not cleared on a Read Data operation. When an FE is encountered, the UART resets itself to the state where it is looking for a start bit. SHDNi write Software-Shutdown Bit. Enter software shutdown with a Write Configuration where SHDNi = 1. Software shutdown takes effect after CS goes high, and causes the oscillator to stop as soon as the transmitter becomes idle. Software shutdown also clears R, T, RA/FE, Dr D7r, Dt D7t, Pr, Pt, and all data in the receive FIFO. RTS and CTS can be read and updated while in shutdown. Exit software shutdown with a Write Configuration where SHDNi =. The oscillator restarts typically within 5ms of CS going high. RTS and CTS are unaffected. Refer to the Pin Description for hardware shutdown (SHDN input). SHDNo read Shutdown Read-Back Bit. The Read Configuration register outputs SHDNo = 1 when the UART is in shutdown. Note that this bit is not sent until the current byte in the transmitter is sent (T = 1). This tells the processor when it may shut down the RS-485/RS-422 driver. This bit is also set immediately when the device is shut down through the SHDN pin. ST write Transmit-Stop Bit. One stop bit will be transmitted when ST =. Two stop bits will be transmitted when ST = 1. The receiver only requires one stop bit. ST read Reads the value of the ST bit. T read 1 Transmit-Buffer-Empty Flag. T = 1 means that the transmit buffer is empty and ready to accept another data word. TE write Transmit-Enable Bit. If TE = 1, then only the RTS pin is updated on CS s rising edge. The contents of RTS, Pt, and Dt D7t transmit on CS s rising edge when TE =. TM write Mask for T Bit. IRQ is asserted if TM = 1 and T = 1 (Table 7). TM read Reads the value of the TM bit (Table 7). Notice to High-Level Programmers: The UART follows the SPI convention of providing a bidirectional data path for writes and reads. Whenever the data is written, data is also read back. This speeds operation over the SPI bus, and the UART needs this speed advantage when operating at high baud rates. In most high-level languages, such as C, there are commands for writing and reading stream I/O devices such as the console or serial port. In C specifically, there is a PUTCHAR command that transmits a character and a GETCHAR command that receives a character. If programmers were to write direct write and read commands in C with no underlying driver code, they would notice that a PUTCHAR command is really a PUTGETCHAR command. These C commands assume some form of BIOS-level support for these commands. The proper way to implement these commands is to write driver code, usually in the form of an assembly-language interrupt-service routine and a callable routine used by high-level routines. This driver handles the interrupts and manages the receive and transmit buffers for the MAX311E/MAX3111E. When a PUTCHAR executes, this driver is called and it safely buffers any characters received when the current character is transmitted. When a GETCHAR executes, it checks its own receive buffer before getting data from the UART. See the C-language Outline of a MAX311E/ MAX3111E Software Driver in Listing 1, which appears at the end of this data sheet. Listing 1 is a C-language outline of an interrupt-driven software driver that interfaces to a MAX311E/ MAX3111E, providing an intermediate layer between the bit-manipulation subroutine and the familiar PUTCHAR/GETCHAR subroutines. The user must supply code for managing the transmit and receive queues as well as the low-level hardware interface itself. The interrupt control hardware must be initialized before this driver is called. 14

15 Write Configuration Register (D15, D14 = 1, 1) Configure the UART by writing a 16-bit word to the write configuration register, which programs the baud rate, data word length, parity enable, and enable of the 8- word receive FIFO. In this mode, bits 15 and 14 of the DIN configuration word are both required to be 1 in order to enable the write configuration mode. Bits 13 of the DIN configuration word set the configuration of the UART. Table 2 shows the bit assignment for the write configuration register. The write configuration register allows selection between normal UART timing and IrDA timing, provides shutdown control, and contains four interrupt mask bits. Using the write configuration register clears the receive FIFO and the R, T, RA/FE, Dr D7r, Dt D7t, Pr, and Pt registers. RTS and CTS remain unchanged. The new configuration is valid on CS s rising edge if the transmit buffer is empty (T = 1) and transmission is over. If the latest transmission has not been completed (T = ), the registers are updated when the transmission is over. The write configuration register bits (FEN, SHDNi, IR, ST, PE, L, B3 B) take effect after the current transmission is over. The mask bits (TM, RM, PM, RAM) take effect immediately after SCLK s 16th rising edge. Bits 15 and 14 of the DOUT write configuration (R and T) are sent out of the MAX311E/MAX3111E along with 14 trailing zeros. The use of the R and T bits is optional, but ignore the 14 trailing zeros. Warning! The UART requires stable crystal oscillator operation before configuration (typically ~25ms after power-up). Upon power-up, compare the write configuration bits with the read configuration bits in a software loop until both match. This ensures that the oscillator is stable and that the UART is configured correctly. Read Configuration Mode (D15, D14 =, 1) The read configuration mode is used to read back the last configuration written to the UART. In this mode, bits 15 and 14 of the DIN configuration word are required to be and 1, respectively, to enable the read configuration mode. Bits 13 1 of the DIN word should be zeros, and bit is the test bit to put the UART in test mode (see the Test Mode section). Table 3 shows the bit assignment for the read configuration register. Test Mode The device enters a test mode if bit of the DIN configuration word equals one when doing a read configuration. In this mode, if CS =, the RTS pin transmits a clock that is 16-times the baud rate. The TX pin is low as long as CS remains low while in test mode. Table 3 shows the bit assignment for the read configuration register. Write Data Register (D15, D14 = 1, ) Use the write data register for transmitting to the TXbuffer and receiving from the RX buffer (and RX FIFO when enabled). When using this register, the DIN and DOUT write data words are used simultaneously, and bits for both the DIN and DOUT write data words are meaningless zeros. The DIN write data word contains the data that is being transmitted, and the DOUT write data word contains the data that is being received from the RX FIFO. Table 4 shows the bit assignment for the write data mode. To change the RTS pin s output state without transmitting data, set the TE bit high. If performing a write data operation, the R bit will clear on the falling edge of SCLK s 16th clock pulse if no new data is available. Read Data Register (D15, D14 =, ) Use the read data register for receiving data from the RX FIFO. When using this register, bits 15 and 14 of DIN are both required to be. Bits 13 of the DIN read-data word should be zeros. Table 5 shows the bit assignments for the read data mode. Reading data clears the R bit and interrupt IRQ. If performing a read data operation, the R bit will clear on the falling edge of SCLKs 16th clock pulse if no new data is available. MAX311E/MAX3111E 15

16 MAX311E/MAX3111E Table 2. Write Configuration (D15, D14 = 1, 1) BIT DIN 1 DOUT R 1 T 13 FEN 12 SHDNi 11 TM D15 is present at DOUT on CS s falling edge. Consecutive bits are clocked out on SCLK s falling edge. 1 RM Notes: bit 15: DOUT R = 1, Data is available to be read or is being read from the receive register or FIFO. R =, Receive register and FIFO are empty. bit 14: DOUT T = 1, Transmit buffer is empty. T =, Transmit buffer is full. bits 13 : DOUT Zeros 9 PM 8 RAM 7 IR 6 ST 5 PE 4 L bits 15, 14: DIN 1,1 = Write Configuration bit 13: DIN FEN =, FIFO is enabled. FEN = 1, FIFO is disabled. bit 12: DIN SHDNi = 1, Enter software shutdown. SHDNi =, Exit software shutdown. bit 11: DIN TM = 1, Transmit buffer empty interrupt is enabled. TM =, Transmit buffer empty interrupt is disabled. bit 1: DIN RM = 1, Data available in the receive register or FIFO interrupt is enabled. RM =, Data available in the receive register or FIFO interrupt is disabled. bit 9: DIN PM = 1, Parity bit high received interrupt is enabled. PM =, Parity bit received interrupt is disabled. bit 8: DIN RAM = 1, Receiver-activity (shutdown mode)/framing-error (normal operation) interrupt is enabled. RAM =, Receiver-activity (shutdown mode)/framing-error (normal operation) interrupt is disabled. bit 7: DIN IR = 1, IrDA mode is enabled. IR =, IrDA mode is disabled. bit 6: DIN ST = 1, Transmit two stop-bits. ST =, Transmit one stop-bit. bit 5: DIN PE = 1, Parity is enabled for both transmit (state of Pt) and receive. PE =, Parity is disabled for both transmit and receive. bit 4: DIN L = 1, 7-bit words (8-bit words if PE = 1) L =, 8-bit words (9-bit words if PE = 1) bits 3 : DIN B3 B = XXXX, Baud-Rate Divisor Select Bits (see Table 6) 3 B3 2 B2 1 B1 B 16

17 Table 3. Read Configuration (D15, D14 =, 1) BIT DIN 1 DOUT R T FEN SHDNo TM RM PM RAM IR ST PE L B3 B2 D15 is present at DOUT on CS s falling edge. Consecutive bits are clocked out on SCLK s falling edge. Notes: bit 15: DOUT R = 1, Data is available to be read or is being read from the receive register or FIFO. R =, Receive register and FIFO are empty. bit 14: DOUT T = 1, Transmit buffer is empty. T =, Transmit buffer is full. bit 13: DOUT FEN =, FIFO is enabled. FEN = 1, FIFO is disabled. bit 12: DOUT SHDNo = 1, Software shutdown is enabled. SHDNo =, Software shutdown is disabled. bit 11: DOUT TM = 1, Transmit buffer empty interrupt is enabled. TM =, Transmit buffer empty interrupt is disabled. bit 1: DOUT RM = 1, Data available in the receive register or FIFO interrupt is enabled. RM =, Data available in the receive register or FIFO interrupt is disabled. bit 9: DOUT PM = 1, Parity bit high received interrupt is enabled. PM =, Parity bit received interrupt is disabled. bit 8: DOUT RAM = 1, Receiver-activity (shutdown mode)/framing-error (normal operation) interrupt is enabled. RAM =, Receiver-activity (shutdown mode)/framing-error (normal operation) interrupt is disabled. bit 7: DOUT IR = 1, IrDA mode is enabled. IR =, IrDA mode is disabled. bit 6: DOUT ST = 1, Transmit two stop-bits. ST =, Transmit one stop-bit. bit 5: DOUT PE = 1, Parity is enabled for both transmit (state of Pt) and receive. PE =, Parity is disabled for both transmit and receive. bit 4: DOUT L = 1, 7-bit words (8-bit words if PE = 1) L =, 8-bit words (9-bit words if PE = 1) bits 3 : DOUT B3 B = XXXX Baud-Rate Divisor Select Bits (see Table 6) bit 15, 14: DIN,1 = Read Configuration bits 13 1: DIN Zeros bit : DIN If TEST = 1 and CS =, then RTS =16xBaudCLK TEST =, Disables test mode 1 B1 TEST B MAX311E/MAX3111E 17

18 MAX311E/MAX3111E Table 4. Write Data (D15, D14 = 1, ) BIT DIN 1 TE RTS Pt D7t D6t D5t D4t D3t D2t DOUT R T RA/FE CTS Pr D7r D6r D5r D4r D3r D2r D15 is present at DOUT on CS s falling edge. Consecutive bits are clocked out on SCLK s falling edge. Notes: bit 15: DOUT R = 1, Data is available to be read or is being read from the receive register or FIFO. R =, Receive register and FIFO are empty. bit 14: DOUT T = 1, Transmit buffer is empty. T =, Transmit buffer is full. bits 13 11: DOUT Zeros bit 1: DOUT RA/FE = Receive-Activity (Uart shutdown)/framing-error (Normal Operation) bit bit 9: DOUT CTS = CTS input state. If CTS =, then CTS = 1 and vice versa. bit 8: DOUT Pr = Received Parity Bit. This is only valid if PE = 1. bits 7 : DOUT D7t Dt = Received Data Bits. D7r = for L = 1. bits 15, 14: DIN 1, = Write Data bits 13 11: DIN Zeros bit 1: DIN TE = 1, Disables transmit and only RTS will be updated. TE =, Enables transmit. bit 9: DIN RTS = 1, Configures RTS = (logic low). RTS =, Configures RTS = 1 (logic high). bit 8: DIN Pt = 1, Transmit parity bit is high. If PE = 1, a high parity bit will be transmitted. If PE =, then no parity bit will be transmitted. Pt =, Transmit parity bit is low. If PE = 1, a low parity bit will be transmitted. If PE =, then no parity bit will be transmitted. bits 7 : DIN D7t Dt = Transmitting Data Bits. D7t is ignored when L = 1. 1 D1t D1r Dt Dr 18

19 Table 5. Read Data (D15, D14 =, ) BIT DIN DOUT 15 R 14 T 13 D15 is present at DOUT on CS s falling edge. Consecutive bits are clocked out on SCLK s falling edge. Notes: bits 15: DOUT R = 1, Data is available to be read or is being read from the receive register or FIFO. R =, Receive register and FIFO are empty. bit 14: DOUT T = 1, Transmit buffer is empty. T =, Transmit buffer is full. bits 13 11: DOUT Zeros bit 1: DOUT RA/FE = Receive-Activity (UART shutdown)/framing-error (Normal Operation) Bit RA/FE 9 CTS 8 Pr 7 D7r 6 D6r bits 15, 14: DIN, = Read Data bits 13 : DIN Zeros 5 D5r 4 D4r 3 D3r 2 D2r 1 D1r Dr MAX311E/MAX3111E bit 9: DOUT CTS = CTS input state. If CTS =, then CTS = 1 and vice versa. bit 8: DOUT Pr = Received parity bit. This is only valid if PE = 1. bits 7 : DOUT D7t Dt = Received Data Bits. D7r = for L = 1. 19

20 MAX311E/MAX3111E Baud-Rate Generator The baud-rate generator determines the rate at which the transmitter and receiver operate. Bits B3 B in the write configuration register determine the baud-rate divisor (BRD), which divides the X1 oscillator frequency. The on-board oscillator operates with either a MHz or a MHz crystal or is driven at X1 with a 45% to 55% duty-cycle square wave. Table 6 shows baud-rate divisors for given input codes as well as the baud rate for MHz and 3.684MHz crystals. The generator s clock is 16-times the baud rate. Interrupt Sources and Masks Using the Read Data or Write Data register clears the interrupt IRQ, assuming the conditions that initiated the interrupt no longer exist. Table 7 gives the details for each interrupt source. Figure 6 shows the functional diagram for the interrupt sources and mask blocks. Following are two examples of setting up an IRQ for the MAX311E/MAX3111E: Example 1. Set up only the transmit buffer-empty interrupt. Send the 16-bit word below into DIN of the MAX311E/MAX3111E using the Write Configuration register. This 16-bit word configures the MAX311E/ MAX3111E for 96bps, 8-bit words, no parity, and one stop bit with a MHz crystal. Table 6. Baud-Rate Selection* BAUD B3 B2 B1 B ** DIISION RATIO BAUD RATE (f OSC = MHz) 115.2k** 57.6k 28.8k 14.4k k 19.2k BAUD RATE (f OSC = MHz) 23.4k** 115.2k 57.6k 28.8k 14.4k k 38.4k 19.2k binary HEX C8A *Standard baud rates shown in bold **Default baud rate Example 2. Set up only the data-available (or databeing-read) interrupt. Send the 16-bit word below into DIN of the MAX311E/MAX3111E using the Write Configuration register. This 16-bit word configures the MAX311E/ MAX3111E for 96bps, 8-bit words, no parity, and one stop bit with a MHz crystal. binary HEX C4A IRQ N Q RM MASK Q TM MASK Q S R S R S R PM MASK NEW DATA AAILABLE DATA READ TRANSMIT BUFFER EMPTY DATA READ PE = 1 AND RECEIED PARITY BIT = 1 PE = OR RECEIED PARITY BIT = Receive FIFO The MAX311E/MAX3111E contain an 8-word receive FIFO for data received by the UART to minimize processor overhead. Using the UART-software shutdown clears the receive FIFO. Upon power-up, the receive FIFO is enabled. To disable the receive FIFO, set the FEN bit high when writing to the Write Configuration register. To check whether the FIFO is enabled or disabled, read back the FEN bit using the Read Configuration. TRANSITION ON RX SHUTDOWN RAM MASK FRAMING ERROR SHUTDOWN RAM MASK Figure 6. Functional Diagram for Interrupt Sources and Mask Blocks 2

21 Table 7. Interrupt Sources and Masks Bit Descriptions BIT NAME Pr R RA/FE MASK BIT PM RM RAM MEANING WHEN SET Received parity bit = 1 Data available Transition on RX when in shutdown; framing error when not in shutdown DESCRIPTION The Pr bit reflects the value in the word currently in the receive-buffer register (oldest data available). The Pr bit is set when parity is enabled (PE = 1) and the received parity bit is 1. The Pr bit is cleared either when parity is not enabled (PE = ) or when parity is enabled and the received bit is. An interrupt is issued based on the oldest Pr value in the receiver FIFO. The oldest Pr value is the next value read by a Read Data operation. The R bit is set when new data is available to be read or when data is being read from the receive register/fifo. FIFO is cleared when all data has been read. An interrupt is asserted as long as R = 1 and RM = 1. This is the RA (RX-transition) bit in shutdown, and the framing-error (FE) bit in operating mode. RA is set if there has been a transition on RX since entering shutdown. RA is cleared when the MAX311E/MAX3111E exits shutdown. IRQ is asserted when RA is set and RAM = 1. FE is determined solely by the currently received data and is not stored in FIFO. The FE bit is set if a zero is received when the first stop bit is expected. FE is cleared upon receipt of the next properly framed character. IRQ is asserted when FE is set and RAM = 1. MAX311E/MAX3111E T TM Transmit buffer is empty The T bit is set when the transmit buffer is ready to accept data. IRQ is asserted low if TM = 1 and the transmit buffer becomes empty. This source is cleared on the rising edge of SCLK s 16th clock pulse when using a Read Data or Write Data operation. CS s rising edge during a Read Data operation. Although the interrupt is cleared, poll T to determine transmit-buffer status. UART Software Shutdown When in software shutdown, the UART s oscillator turns off to reduce power dissipation. The UART enters shutdown by a software command (SHDNi bit = 1). The software shutdown is entered upon completing the transmission of the data in both the Transmit register and the Transmit-Buffer register. The SHDNo bit is set when the UART enters shutdown. The microcontroller (µc) monitors the SHDNo bit to determine when the UART is shut down and then shuts down the RS-232 transceivers. Software shutdown clears the receive FIFO, R, RA/FE, Dr D7r, Pr, and Pt registers and sets the T bit high. Configuration bits (RM, TM, PM, RAM, IR, ST, PE, L, B B3, and RTS) are programmable when SHDNo = 1 and CTS is also readable. Although RA is reset upon entering shutdown, it goes high when any transitions are detected on the RX pin. This allows the UART to monitor activity on the receiver when in shutdown. When taking the part out of software shutdown (SHDNi = ), the oscillator turns on when CS goes high. After CS goes high, the oscillator typically takes about 25ms to stabilize. Configure the UART after the oscillator has stabilized by using a write configuration that clears all registers but RTS and CTS. If a framing error occurs, you may have not waited long enough for the oscillator to stabilize. The hardware shutdown affects only the RS-232 transceiver, and the software shutdown affects only the UART. See the RS-232 Transceiver Hardware Shutdown section. Dual Charge-Pump oltage Converter The internal power supply consists of a regulated dual charge pump that provides output voltages of +5.5 (doubling charge pump) and -5.5 (inverting charge pump), using a +3.3 supply (MAX3111E) or a +5 supply (MAX311E). The charge pump operates in discontinuous mode; if the output voltages are less than 5.5, the charge pump is enabled, and if the output voltages exceed 5.5, the charge pump is disabled. Each charge pump includes internal flying capacitors and reservoir capacitors to generate the + and - supplies. 21

22 MAX311E/MAX3111E RS-232 Transmitters The transmitters are inverting-level translators that convert CMOS-logic levels to ±5. EIA/TIA-232 levels. The transmitters guarantee a 23kbps data rate with worstcase loads of 3kΩ in parallel with 1pF, providing compatibility with PC-to-PC communication software (such as LapLink ). Transmitters can be paralleled because the outputs are forced into a high-impedance state when the device is in hardware shutdown (SHDN = GND). The MAX311E/MAX3111E permit the outputs to be driven up to ±12 while in shutdown. The transmitter inputs do not have pull-up resistors. Connect unused inputs to GND or CC. RS-232 Receivers The receivers convert RS-232 signals to CMOS-logic output levels. The MAX311E/MAX3111E receivers have inverting outputs and are always active, even when the part is in hardware (or software) shutdown. RS-232 Transceiver Hardware Shutdown Supply current falls to I CCSHDN(H) when in hardware shutdown mode (SHDN = low). When shut down, the device s charge pumps are turned off, + is pulled down to CC, - is pulled to ground, and the transmitter outputs are disabled (high impedance). The time required to exit shutdown is typically 1µs, as shown in Figure 7. Connect SHDN to CC if the shutdown mode is not used. The UART software shutdown does not affect the RS-232 transceiver. ±15k ESD Protection As with all Maxim devices, ESD-protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly. The driver outputs and receiver inputs of the MAX311E/MAX3111E have extra protection against static electricity. Maxim s engineers have developed state-of-the-art structures to protect these pins against ESD of ±15k without damage. The ESD structures withstand high ESD in all states: normal operation, shutdown, and powered down. After an ESD event, the MAX311E/MAX3111E keep working without latchup, whereas competing RS-232 products can latch and must be powered down to remove latchup. ESD protection is tested in various ways; the transmitter outputs and receiver inputs devices are characterized for protection to the following limits: ±15k using the Human Body Model ±8k using the Contact-Discharge Method specified in IEC ±15k using the Air-Gap Method specified in IEC /div 2/div CC = 3.3 4µs/div SHDN T2OUT T1OUT Figure 7. MAX3111E Transmitter Outputs Exiting Shutdown or Powering Up ESD Test Conditions ESD performance depends on a variety of conditions. Contact Maxim s Quality Assurance (QA) group for a reliability report that documents test setup, methodology, and results. Human Body Model Figure 8a shows the Human Body Model, and Figure 8b shows the current waveform it generates when discharged into a low impedance. This model consists of a 1pF capacitor charged to the ESD voltage of interest, which is then discharged into the test device through a 1.5kΩ resistor. IEC The IEC standard covers ESD testing and performance of finished equipment; it does not specifically refer to integrated circuits. The MAX311E/ MAX3111E help you design equipment that meets Level 4 (the highest level) of IEC without the need for additional ESD-protection components. The major difference between tests done using the Human Body Model and IEC1-4-2 is higher peak current in IEC 1-4-2, because series resistance is lower in the IEC model. Hence, the ESD that withstands voltage measured to IEC is generally lower than that measured using the Human Body Model. Figure 9a shows the IEC model, and Figure 9b shows the current waveform for the ±8k IEC Level 4 ESD contact-discharge test. LapLink is a trademark of Traveling Software. 22

23 HIGH- OLTAGE DC SOURCE R C 1M CHARGE-CURRENT LIMIT RESISTOR Cs 1pF R D 15Ω DISCHARGE RESISTANCE STORAGE CAPACITOR Figure 8a. Human Body ESD Test Model R C 5M to 1M R D 33Ω DEICE UNDER TEST AMPERES I P 1% 9% 36.8% 1% t RL TIME t DL CURRENT WAEFORM Figure 8b. Human Body Model Current Waveform I 1% 9% Ir PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) MAX311E/MAX3111E CHARGE-CURRENT LIMIT RESISTOR DISCHARGE RESISTANCE IPEAK HIGH- OLTAGE DC SOURCE Cs 15pF STORAGE CAPACITOR DEICE UNDER TEST 1% tr =.7ns to 1ns 3ns t 6ns Figure 9a. IEC ESD Test Model Figure 9b. IEC ESD Generator Current Waveform The air-gap test involves approaching the device with a charged probe. The contact-discharge method connects the probe to the device before the probe is energized. Machine Model The Machine Model for ESD tests all pins using a 2pF storage capacitor and zero discharge resistance. Its objective is to emulate the stress caused by contact that occurs with handling and assembly during manufacturing. Of course, all pins require this protection during manufacturing, not just RS-232 inputs and outputs. Therefore, after PC board assembly, the Machine Model is less relevant to I/O ports. Applications Information Crystals, Oscillators, and Ceramic Resonators The MAX311E/MAX3111E include an oscillator circuit derived from an external crystal oscillator for baud-rate generation. For standard baud rates, use a MHz or MHz crystal. The MHz crystal results in lower operating current; however, the MHz crystal may be more readily available in surface mount. 23

24 MAX311E/MAX3111E Ceramic resonators are low-cost alternatives to crystals and operate similarly, although the Q and accuracy are lower. Some ceramic resonators are available with integral load capacitors, which can further reduce cost. The tradeoff between crystals and ceramic resonators is in initial-frequency accuracy and temperature drift. Keep the total error in the baud-rate generator below 1% for reliable operation with other systems. This is accomplished easily with a crystal and, in most cases, is achieved with ceramic resonators. Table 8 lists different types of crystals and resonators and their suppliers. The MAX311E/MAX3111E s oscillator supports parallel-resonant mode crystals and ceramic resonators or can be driven from an external clock source. Internally, the oscillator consists of an inverting amplifier with its input, X1, tied to its output, X2, by a bias network that self-biases the inverter at approximately CC /2. The external feedback circuit, usually a crystal from X2 to X1, provides 18 of phase shift, causing the circuit to oscillate. As shown in the Standard Application Circuit, the crystal or resonator is connected between X1 and X2, with the load capacitance for the crystal being the series combination of C1 and C2. For example, for a MHz crystal with a specified load capacitance of 11pF, use capacitors of 22pF on either side of the crystal to ground. Series-resonant mode crystals have a slight frequency error, typically oscillating.3% higher than specified series-resonant frequency when operated in parallel mode. Note: It is very important to keep crystal, resonator, and load-capacitor leads and traces as short and direct as possible. Make the X1 and X2 trace lengths and ground tracks short, with no intervening traces. This helps minimize parasitic capacitance and noise pickup in the oscillator, and reduces EMI. Minimize capacitive loading on X2 to minimize supply current. The MAX311E/ MAX3111E s X1 input can be driven directly by an external CMOS clock source. The trip level is approximately equal to CC /2. Make no connection to X2 in this mode. If a TTL or non-cmos clock source is used, ACcouple it with a 1nF capacitor to X1. A 2 peak-topeak swing on the input is required for reliable operation. RS-232 Transmitter Outputs Exiting Shutdown Figure 7 shows two RS-232 transmitter outputs exiting shutdown mode. As they become active, the two transmitter outputs are shown going to opposite RS-232 levels (one transmitter input is high; the other is low). Each transmitter is loaded with 3kΩ in parallel with 25pF. The transmitter outputs display no ringing or undesirable transients as they come out of shutdown. Note that the transmitters are enabled only when the magnitude of - exceeds approximately 3. Table 8. Component and Supplier List DESCRIPTION FREQUENCY (MHz) TYPICAL C1, C2 (pf) SUPPLIER PART NUMBER PHONE NUMBER Through-Hole Crystal (HC-49/U) ECS International, Inc. ECS Through-Hole Ceramic Resonator Murata North America CSA1.84MG Through-Hole Crystal (HC-49/US) ECS International, Inc. ECS SMT Crystal ECS International, Inc. ECS P SMT Ceramic Resonator None (integral) AX/Kyocera PBRC-3.68B