ECE 4510/5530 Microcontroller Applications Week 6 Lab 5

Transcription

1 Microcontroller Applications Week 6 Lab 5 Dr. Bradley J. Bazuin Associate Professor Department of Electrical and Computer Engineering College of Engineering and Applied Sciences

2 Lab 5 Element Hardware Development Enhanced Capture Timer (ECT) (Chap. 8) Input Capture (external event timing) Pulse Width Modulator (PWM) (Chap. 8) Serial Communication Interface (SCI) (Chap. 9) RS-232 Transceiver Software Development Smoothing (filtering) measured data

3 SCI0/1 AND RS-232 3

4 The RS232 Standard Was the most widely used physical level interface for data communication Specifies 25 interchange circuits for DTE/DCE use Was established in 1960 by Electronics Industry Association (EIA) Was revised into RS232C in 1969 Was revised into RS232D in 1987 Was revised to RS232E in 1991/1992 and renamed as EIA/TIA-232-E It has been superseded by TIA-232-F (Sept 1997) Four aspects: electrical, functional, procedural, and mechanical

5 The EIA-232E Electrical Specifications (1 of 3) The interface is rated at a signal rate of < 20 kbps. The signal can transfer correctly within 15 meters. Voltage of Physical Layer Output The maximum driver output voltage (with circuit open) is -25 V to +25 V. The minimum driver output voltage (loaded output) is -25 V to -5 V and +5 V to +25 V. The minimum driver output resistance when power is off is 300. Voltage of Physical Layer Input The receiver input voltage range is -25 V to +25 V. The receiver output is high when input is open circuit. A voltage more negative than -3 V at the receiver input is interpreted as a logic 1. A voltage more positive than +3 V at the receiver input is interpreted as a logic 0.

6 The EIA-232E Electrical Specifications (2 of 3) 6

7 The EIA-232E Electrical Table 9.1 Functions of EIA-232-E signals Specifications (3 of 3) Pin No. Circuit Description 1 - Shield 2 BA Transmitted data 3 BB Received data 4 CA/CJ Request to send/ready for receiving 1 5 CB Clear to send 6 CC DCE ready 7 AB Signal common 8 CF Received line signal detector 9 - (reserved for testing) 10 - (reserved for testing) 11 - unassigned 3 12 SCF/CI Secondary received line signal detection/data rate selector (DCE source) 2 13 SCB Secondary clear to send 14 SBA Secondary transmitted data 15 DB Transmitter signal element timing (DCE source) 16 SBB Secondary received data 17 DD Receiver signal element timing 18 LL Local loopback 19 SCA Secondary request to send 20 CD DTE ready 21 RL/CG Remote loopback/signal quality detector 22 CE Ring indicator 23 CH/CI Data signal rate selector (DTE/DCE source) 2 24 DA Transmitter signal element timing (DTE source) 25 TM Test mode 25 pin definition 1. When hardware flow control is required, circuit CA may take on the functionality of circuit CJ. This is one change from the former EIA For designs using interchange circuit SCF, interchange circuits CH and CI are assigned to pin 23. If SCF is not used, CI is assigned to pin Pin 11 is unassigned. It will not be assigned in future versions of EIA-232. However, in international standard ISO 2110, this pin is assigned to select transmit frequency.

8 Interfacing SCI with EIA-232-E The SCI uses 0 V and 5 V to represent 0 and 1. The EIA-232 signal Tx cannot be driven by the SCI TxD signal without translation. The EIA-232 signal Rx cannot drive the SCI RxD signal without translation. Voltage level translation is required for the SCI signals to drive and be driven by the EIA-232 signals. Examples of EIA-232 driver chips include: LT1080/1081 from Linear technology ST232 from SGS Thompson ICL232 from Intersil MAX232 from MAXIM (parts kit device) DS14C232 from National Semiconductor These chips are pin-compatible. The DS14C232 from National Semiconductor will be used in the following illustration.

9 Typical RS-232 Transceiver IC 1.0 F +5 V V - + C4 C1 C2 1.0 F 1.0 F TTL/CMOS inputs TTL/CMOS inputs C1+ V+ 3 C1-4 C2+ V- DC-to-DCConverter 5 C2- +5 V T1 IN T2 IN +5 V D1 D2 V CC T1 OUT T2 OUT 2 6 C F EIA-232-E outputs Textbook example transceiver p. 465 TTL/CMOS outputs TTL/CMOS outputs 12 9 R1 OUT R2 OUT R1 R2 R1 IN 5K R2 IN 5K 13 8 EIA-232-E inputs GND 15 Figure 9.18 Pin assignments and connections of the DS14C232

10 Parts Kit RS-232 Transceiver IC MAX232IN Meets or Exceeds TIA/EIA-232-F and ITU Recommendation V.28 Operates From a Single 5-V Power Supply With 1.0-uF Charge-Pump Capacitors Operates Up To 120 kbit/s Two Drivers and Two Receivers ±30-V Input Levels Low Supply Current... 8 ma Typical ESD Protection Exceeds JESD V Human-Body Model (A114-A) Upgrade With Improved ESD (15- kv HBM) and 0.1-uF Charge-Pump Capacitors is Available With the MAX202 Applications TIA/EIA-232-F, Battery-Powered Systems, Terminals, Modems, and Computers 10

11 Interfacing with the Transceiver Interfacing the HCS12 SCI0 to the EIA-232 using the DS14C232 chip and implements the NULL modem connection so that this connection can talk to a PC directly. DS14C232 1 DCD 6 DSR PS1/TxD 11 T1IN T1OUT 14 2 RxD CTS* 10 T2IN R2IN 8 7 RTS PS0/RxD 12 R1OUT R1IN 13 3 TxD RTS* 9 R2OUT T2OUT 7 8 CTS Note: Both CTS and RTS are jumpered to an I/O pin in case hardware handshake is needed DTR RI GND DB9 connector Figure 9.19 Diagram of SCI and EIA232 DB9 connector wiring in SSE256 demo board

12 RS-232 Transceivers Sunseeeker board-to-board connection RTS/CTS hardware signaling connected A null modem cable used for board to board communications. Intersil ICL3222CB 18 pin SOIC 12

13 EIA-232-E Mechanical Specification (1 of 2) Specifies a 25-pin connector (DB25) Specifies exact dimensions of each pin Signal Direction Signal Name Signal Name Signal Direction to DCE to DTE to DTE to DTE to DCE to DCE to DTE to DTE Both to DCE Secondary transmitted data Transmit clock Secondary received data Receiver clock Unassigned Secondary request to send Data terminal ready Signal quality detect Ring indicator Data rate select Transmit clock Unassigned Protective ground Transmitted data Received data Request to send Clear to send Data set ready Signal ground Carrier detect Reserved Reserved Unassigned Secondary carrier detect Secondary clear to send Both to DCE to DTE to DCE to DTE to DTE Both to DTE to DTE to DTE Figure 9.1 EIA-232-E connector and pin assignment 13

14 EIA-232-E Mechanical Specification (2 of 2) Only a small subset of the 25 pins are actually used in most data communications. Nine-pin is introduced to reduce the size and cost of the connector. (DB9 ) Old back panel PC Com port connectors Another connector was the old PC mouse and keyboard circular connectors. 14

15 EIA-232-E Procedural Specification (1 of 2) Define the sequence of events that occurs during data transmission. Examples: Case 1. Two DTEs connected via a point-to-point link using a modem Signal ground (GND) (Voltage reference for other pins) Transmitted data (Tx) (output from up, serial data transmission) Received data (Rx) (input to up, serial data received) Hardware Handshaking Request to send (RTS) (output from up, connect to CTS if not used) Clear to send (CTS) (input to up, connect to RTS if not used) State of the DTEs and what the line is doing Data set ready (DSR) (input to up, set high if not used) DTE Ready (DTR) (output from up, pair with DSR, set high if not used) Carrier detect (CD) (input to up, the phone/modem is ringing) Ring Indicator (RI) (input to up, the phone is ringing, not required)

16 EIA-232-E Procedural Specification (2 of 2) Computer (DTE) Modem (DCE) Modem (DCE) Computer (DTE) TxD RxD CD CTS TxD RxD CD CTS Direct link TxD RxD CD CTS TxD RxD CD CTS RTS DSR GND RTS DSR GND RTS DSR GND RTS DSR GND Figure 9.2 Point-to-point asynchronous connection Null modem cable: Computer to Computer 16

17 Sequence of Events Occurred During Data Transmission Over Dedicated Link Local 1. DCE asserts DSR 2. DTE asserts RTS 3. DCE asserts CTS Time Remote 4. DTE starts to send data (to local DCE) 5. DCE sends out a carrier and then the modulated data 6. DCE asserts CD 7. DTE waits for arrival of data 8. DCE sends out demodulated received data 9. DTE receives demodulated data

18 EIA-232-E Procedural Specification Example 2 (1 of 2) Case 2. Two DTEs (data terminal equipment) exchange data through a public phone line. EIA-232-E signals involved: Signal ground (GND) Transmitted data (Tx) Received data (Rx) Request to send (RTS) Clear to send (CTS) Data set ready (DSR) Carrier detect (CD) Data terminal ready (DTR) Ring indicator (RI) The signal DTR is used by the DTE to indicate its intention to make a call or accept a call. The signal RI is used by the DCE to indicate that there is an incoming call.

19 EIA-232-E Procedural Specification Example 2 (2 of 2) Computer (DTE) Modem (DCE) Modem (DCE) Computer (DTE) TxD RxD RI CD CTS RTS DSR DTR GND TxD RxD RI CD CTS RTS DSR DTR GND Phone line TxD RxD RI CD CTS RTS DSR DTR GND TxD RxD RI CD CTS RTS DSR DTR GND Figure 9.3 Asynchronous connection over public phone line 19

20 Sequence of Events During Data Transmission Over Public Phone Line (1 of 2) Local (transmission side) time Remote (receiving side) Connection establishment phase 1. DTE asserts DTR 2. DCE dials the phone number 3. DCE detects the ring and asserts RI 4. DTE asserts DTR to accept the call 6. DCE asserts DSR and CD and also sends out a carrier for full duplex operation 5. DCE sends out a carrier and asserts DSR 7. DCE asserts CD (full duplex operation)

21 Sequence of Events During Data Transmission Over Public Phone Line (2 of 2) Data transmission phase Local (transmission side) time Remote (receiving side) 1. DTE asserts RTS 2. DCE asserts CTS 3. DTE sends out data to DCE 4. DCE modulates data and sends it out 5. DCE demodulates data and forwards the data to DTE 6. DTE receives data Disconnection phase 1. DTE drops RTS 2. DCE drops CTS and drops the carrier 3. DCE deasserts CD & DSR 4. DTE deasserts DTR

22 Data Format for Asynchronous Data Communication Data is transmitted character by character bit-serially. A character consists of one start bit (0) 7 to 8 data bits (often, an ASCII character plus a parity bit) an optional parity bit one, or one and a half, or two stop bits (1) least significant bit is transmitted first most significant bit is transmitted last Note: Transceivers invert the signal to the appropriate logical and voltage levels of the physical layer.

23 Example: How to Detect the Arrival of Start Bit Use a clock signal with frequency at least 16 times that of the data rate to sample the RxD signal. When the RxD pin is idle (high) for at least three sampling times and a falling edge follows, the SCI circuit checks the third, fifth, and seventh samples after the first sample. If the majority of them are low, then the start bit is considered detected. 23

24 Example: How to Determine the Logic Value of a Data Bit Use a clock signal with frequency at least 16 times that of the data rate to sample the incoming data. Take the majority function of the eighth, ninth, and tenth samples. If the majority of them are 1s, then the logic value is determined to be 1. 24

25 Example 9.1 Sketch the output of the letter g when it is transmitted using the format of one start bit, 8 data bit, and 1 stop bit. Solution: The ASCII code of letter g is $67 or % This code will be followed by a stop bit. The output from the DTE should be: (a) output waveform on microcontroller interface (b) output waveform on EIA-232-E interface Figure 9.6 Data format for letter g

26 Data Transmission Errors Framing error A character is not properly framed by a stop bit Receiver overrun One or more characters received, but not read by the CPU Parity error Odd number of bits change value

27 Null Modem Connection Signal Name FG (frame ground) TD (transmit data) RD (receive data) RTS (request to send) CTS (clear to send) SG (signal ground) DSR (data set ready) CD (carrier detect) DTR (data terminal ready) DTR (data terminal ready) DB25 pin DTE 1 DTE 2 DB9 pin DB9 pin Figure 9.7 Null Modem connection DB25 pin Signal Name FG RD TD CTS RTS SG DTR DTR CD DSR Null modem cable: Computer to Computer

28 The HCS12 SCI Subsystem (1 of 3) An HCS12 device may have one or two serial communication interface. These two SCI interfaces are referred to as SCI0 and SCI1. Use the data format of one start, eight or nine data bits, and one stop bit. The collection of the start bit, eight or nine data bits, and the stop bit is called a frame. The SCI function supports parity checking. This option requires the use of 9-bit data format. One SCI channel uses two signal pins from Port S. SCI0 shares the use of PS0 (RxD0) and PS1 (TxD0) SCI1 shares the use of PS2 (RxD1) and PS3 (TxD1).

29 The HCS12 SCI Subsystem (2 of 3) The SCI has the capability to send break to attract the attention of the other party of communications. A break is defined as the transmission or reception of logic 0 for a frame or longer time. The SCI supports hardware parity for transmission and reception. The SCI supports idling line and address mark wakeup, which is useful in multi-drop environment to reduce the software overhead.

30 The HCS12 SCI Subsystem (3 of 3) RxD SCI data register Receive shift register Interrupt generation Idle IRQ RDRF/OR IRQ Registers Outlined in red Receive and wake up control Bus clock BAUD generator 16 Data format control Transmit control Transmit shift register SCI data register Interrupt generation TDRE IRQ TC IRQ O R I N G IRQ to CPU Status Register 1 Status Register 2 TxD Figure 9.8 HCS12 SCI block diagram 30

31 Baud Rate Generation (1 of 2) The HCS12 SCI module uses a 13-bit counter to generate this clock signal. The baud rate generator divides down the E clock to derive the clock signal for reception and transmission. The user writes an appropriate value into the SCIxBDH and SCIxBDL (x = 0 or 1) register pair to set the baud rate SBR12 SBR11 SBR10 SBR9 SBR8 reset: (a) SCI baud rate control register high (SC0BDH/SC1BDH) SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 reset: (b) SCI baud rate control register low (SC0BDL/SC1BDL) Figure 9.9 SCI baud rate control register 31

32 Baud Rate Generation (2 of 2) The 13-bit value to be written into the baud rate generator register is the rounding of the following expression: SBR f E Clk 16 Baud _ Rate Table 9.2 Baud rate generation Desired SCI baud rate Baud rate divisor for f E = 16 MHz Baud rate divisor for f E = 24 MHz ,400 19,200 38,

33 Baud Rate Generator Count E-Clock Desired Rate Ratio Remainder Use Actual Rate Error % % % % % % % % % % % % 33

34 SCI1 Initialization void init_sci1(void) { // SCI1BD = round( ECLK / (16 x baud_rate) ) SCI1BD = data_rate_here; // 24 MHz E-clock, XXXX bps desired (0.16% error) } SCI1CR1 = SCISWAI WAKE ILT ; SCI1CR1 &= ~(M PE PT) ; SCI1CR2 = TE RE; //SCISWAI, wakeup to mark, idle line after stop // 8-bit data, parity disabled, even parity // transmitter enable, receiver enable, // no interrupts enabled, not a break bit, not wake up 34