Power Management in modern-day SoC

Size: px

Start display at page:

Download "Power Management in modern-day SoC"

Darlene Whitehead
5 years ago
Views:

1 Power Management in modern-day SoC C.P. Ravikumar Texas Instruments, India C.P. Ravikumar, IIT Madras 1 Agenda o Motivation o Power Management in the Signal Chain o Low-Power Design Flow Technological considerations Architectural Considerations Algorithmic Considerations Communication Standard Cell Design and Memories Logic Synthesis Verification Test C.P. Ravikumar, IIT Madras 2 1

2 Energy Efficiency o Battery life, heat dissipation, reliability Mobile applications Sensor networks o Green Electronics o Eco-friendly design C.P. Ravikumar, IIT Madras 3 mw/mmacs Gene Franz s law for Power scaling 1, Power Dissipation Energy scavenging mw/cm 3 Brain Gene's Law: Power dissipation will decrease by half every 18 months Gene s Law DSP Power Mobile Phone Year C.P. Ravikumar, IIT Madras 4 2

3 Energy Harvesting/Scavenging o Solar energy o Temperature Difference o Wind energy o Kinetic energy o RF energy from transmissions (cochlear implants) o Wireless charging C.P. Ravikumar, IIT Madras 5 Temperature Difference o Thermoelectric power generation caused by heat flux through a thermoelectric element The heat flux is due to the temperature difference Voltage proportional to temperature difference o Thermogenerator has a large number of thermoelectric elements C.P. Ravikumar, IIT Madras 6 3

Example - Micropelt o Micropelt thermogenerators o Hundreds of elements o Voltage in the range of 0.

4 Example - Micropelt o Micropelt thermogenerators o Hundreds of elements o Voltage in the range of Volt o Sufficient energy to drive a low-power wireless applications Remote sensors, data loggers and small actuators C.P. Ravikumar, IIT Madras 7 Ultra low-power electronics o Cochlear implants Power/Area tradeoff between Digital/Analog implementations What do you implement before and after an ADC? Big-A/Small-D, Big-D/Small-A C.P. Ravikumar, IIT Madras 8 4

Power Management in Signal Chain The Real World

Position Speed Flow Humidity Sound Power Management

o Economics o Reliability o Green Electronics = ultra

5 Power Management in Signal Chain The Real World Amplifier Data Converter Logic Temperature Pressure Position Speed Flow Humidity Sound Power Management Digital Signal Processor Light Amplifier Data Converter Interface C.P. Ravikumar, IIT Madras 9 Minimizing Power o Environment o Economics o Reliability o Green Electronics = ultra low-power products + energy harvesting o Case Study : MSP430 microcontroller C.P. Ravikumar, IIT Madras 10 5

6 Software must be power-aware o Operating system Put the CPU is sleep mode if process queue is empty o Compilation can be power-aware Instruction reordering to reduce switching activity Register renaming Reduce data movement C.P. Ravikumar, IIT Madras 11 Compiler and Power [Lizy Kurian John, UT Austin] A Cycle 1 A E A Cycle 1 B C E Cycle 2 B C B C Cycle 2 E D Cycle 3 D D Cycle 3 F Cycle 4 F F Cycle 4 DDG Peak Power = 3 Energy = 6 Peak Power = 2 Energy = 6 C.P. Ravikumar, IIT Madras 12 6

7 Design Flow Technological considerations o Power and Power Density scaling Gene s law o Alternate sources of power Solar, RF, wind, motion, 1, mw/mmacs Energy scavenging mw/cm 3 Brain C.P. Ravikumar, IIT Madras Year Design Flow Architectural considerations o Multicore o IP selection Performance/Power/Area tradeoffs o Floorplanning o Packaging o Data-path Modules C.P. Ravikumar, IIT Madras 14 7

Design Flow Algorithmic considerations o Task allocation to processors o Compiler optimizations o Use of on-chip memory/cache o Low-power modes o Power-aware

8 Design Flow Algorithmic considerations o Task allocation to processors o Compiler optimizations o Use of on-chip memory/cache o Low-power modes o Power-aware OS/Software C.P. Ravikumar, IIT Madras 15 Design Flow Communication o Low Power RF communication o Wireless Sensor Networks Power-aware protocols C.P. Ravikumar, IIT Madras 16 8

9 Design Flow Standard Cell Design/Memory Design o Low VDD operation, Voltage Domains o Transistor sizing and Multi Vt design o Body Bias o Sleep transistors o Split word-line C.P. Ravikumar, IIT Madras 17 Design Flow Logic Synthesis C pin = C 1 C pin = C 1 toggle rate =.4 a toggle rate =.8 d b c f b c f d toggle rate =.8 a toggle rate =.4 C pin = 1.5C 1 C pin = 1.5C 1 f1 = b(a + c) + cd f2 = ab + c (b + d) a c b c d f a b c b d f C.P. Ravikumar, IIT Madras 18 b is a high-activity net 9

10 Design Flow Power Verification o Will assumptions fail when we integrate IP? Cores may use different power management techniques Multiple Voltage Islands need level shifters C.P. Ravikumar, IIT Madras 19 Design Flow Test for Low Power Design o Scan shift power o Scan capture power o Leakage Power C.P. Ravikumar, IIT Madras 20 10

11 Range of Voltage-Control Techniques 1.2V OFF 1.2V RET 1.2V 1.0V 0.9V 1.0V 0.9V 1.0V 0.9V Multi-Vdd (MV) MTCMOS power gating (shut down) Power gating with State Retention PWR PWR CTRL V VDDB A Z 0.6V 1.0V 0.9V VSSB 1.2V Dynamic or Adaptive Voltage Frequency Scaling (DVS, DVFS, AVS, AVFS) Variable V TH (Back Bias P/N) 1.0V 0.9V Low-VDD Standby C.P. Ravikumar, IIT Madras 21 V1 Power Management increases verification complexity enormously CPU in CPU in Normal HP Standby Mode Mode Display Display in in Display in Normal OFF Mode Standby HP Mode Mode with Power Switches Tx/Rx Tx/Rx in in Normal Standby Mode V2 Level Shifters Isolation Cells V3 Audio in Audio OFF Mode in Normal with Mode Power Switches PMU Video in Video OFF in Mode Normal with Mode Power Switches Correct Verification Multiple implementation power must now states, understand of transitions LP specific voltage and design Phone Call sequences elements PDA values must be happen verified Standby C.P. Ravikumar, IIT Madras 22 11

12 Verification needed to ensure things don t go wrong Isolation/Level Shifting Bugs Control Sequencing bugs Retention scheme/control errors Retention selection errors Electrical Problems like memory corruption Power Sequencing/Voltage Scheduling errors Hardware-Software deadlock Power Gating collapse/dysfunction Power On Reset/bring up problems Thermal runaway/ Overheating These are not traditional functional bugs! C.P. Ravikumar, IIT Madras 23 Design Flow Thermal considerations o Silicon is not a good conductor of heat High power density leads to higher temperature Higher temperature leads to higher leakage o Positive feedback loop can lead to thermal runaway o Example repeated access to registers in a register file can cause a hot spot C.P. Ravikumar, IIT Madras 24 12

Solar Energy Harvesting Kit o Efficient solar energy harvesting module for the ez430-rf2500 o Battery-less operation o Works in low ambient light o 400+ transmissions in dark o Adaptable to any RF

13 Solar Energy Harvesting Kit o Efficient solar energy harvesting module for the ez430-rf2500 o Battery-less operation o Works in low ambient light o 400+ transmissions in dark o Adaptable to any RF network or sensor input o Inputs available for external harvesters (thermal, piezo, 2nd solar panel, etc.) o USB debugging and programming interface with application backchannel to PC o 18 available analog and communications input/output pins o Highly integrated, ultra-low-power MSP430 MCU with 16-MHz performance o Two green and red LEDs for visual feedback o Interruptible push button for user feedback C.P. Ravikumar, IIT Madras 25 Summary o Software must be power-aware Operating system Application software o Hardware must support power management Low-power modes o Active Power minimization voltage scaling o Standby Power minimization back-bias, multi-vt, power gating, o Power must be factored into all aspects of design flow C.P. Ravikumar, IIT Madras 26 13

EDA Challenges for Low Power Design. Anand Iyer, Cadence Design Systems

EDA Challenges for Low Power Design Anand Iyer, Cadence Design Systems Agenda Introduction ti LP techniques in detail Challenges to low power techniques Guidelines for choosing various techniques Why is