STM RH-ASIC capability

Transcription

1 STM RH-ASIC capability JAXA 24 th MicroElectronic Workshop 13 th 14 th October 2011 Prepared by STM Crolles and AeroSpace Unit

2 Deep Sub Micron (DSM) is strategic for Europe Strategic importance of European DSM access / Support: Scientific satellites and probes require more and more low power RH Computing capability Same trend for Observation satellites Commercial Telecomm satellites progressively move from «listen & retransmit» birds to complex re-programming, signal reconstitution and so on: Computer power needed Business for Telecomm Operators and Satellite makers must strategically not depend from abroad technology sources. European Community (FP-7 Plans) recognized this major risk since 2006 CNES and ESA do technically and financially support this initiative since 2007 RH 65nm STm technology selected in 2009 after successful Reliability and Radiation performance evaluation contracts. European Satellite makers Industry also joined the team STM a 55,000 people advanced technology Company supports European goals This Presentation focuses upon RH, RH Library and Design tools 2

3 ST 65nm CMOS selected by European Space Agencies 21 ST qualification circuits in CMOS 130/90/65/45/40 jointly irradiated by ESA and ST-Crolles since 2005 with heavy ions, protons and gamma rays using ESA certified beam facilities & test standards >1,000,000 test data collected over the past 5 years High intrinsic radiation hardness measured with heavy ions and protons no latch-up nor permanent fails ESA newton spacecraft 2014 Quasi intrinsic immunity to gamma rays no longer need for costly edgeless transistors, rings, Validation of new specific rad-hard solutions and telecom circuits in progress joint work with European satellite makers 3

4 ST System-on-Chip approach Memories Digital Logic Data Converters Clock Generator Links & Interfaces Sensors, Regulators Design Methodologies & Design Flows Silicon Validation & Qualification 4

5 Design Flow Overview Common Setup Architecture Power estimation and budgeting Chip RTL RTL to Gate Synthesis/DFT Insertion Top level Prototyping & Floorplan Physical Units Implementation Chip Level Assembly Sign-Off Subsystem Packaging infrastructure GDS2 5

6 Analog / Full Custom Design Flow Overview Design Kit Create schematic Pre-layout simulation Physical Design Kit, analog design Layout creation Layout verification Post layout simulation Custom Methodologies for design robustness, parametric yield enhancement DFM Analysis & Correction Design productivity enhancement Layout finishing

7 Radiation Hardening Design Solutions Expertise covering radiation testing, modeling, hardening Test Chips Modeling Accelerated Rad Test (Crolles) FIT simulation Radiation Hardening Offer Fault Injection platform Real Time Rad Test (Pic de Bure) Rad-hard libraries Radiations Safety and Security Several M$ investments (Y99-11 / 130nm-32nm) Soft Error Simulations at SoC Level Medical Network Automotive Space HDD Printer Mobile Computer 10 team members at ST-Crolles 7

8 Radiation Robust ensured during IP Qualification IP radiation performances mastered with advanced simulations and irradiations Radiation qualification part of IP certification, ST differentiation for automotive, network, medical applications Highest Robustness with patented Rad-Hard Technology Specific design platform for space built-up for several years Chip under irradiation SRAM Fault Injection 8

9 Rard-Hard DSM CMOS65LP schedule Validated Rad-Hard Platform for key Users : Mid First Part: Hardening methodology validated Std cells & Memory in Fab, Second Part, PLL and HSSL : Characterization : 1Q12 Library availability : 2Q12 Completion of equiv-to-20year Reliability Test : 3Q12 Key Open Point : High pin count Packaging 9

10 Conclusions on STM RH-ASIC capability Expertise in testing +50 circuits already characterized over 10 technology nodes 250nm - 28nm state-of-the-art test system and test algorithms compliant with international radiation test standards: ESA-SCC / JEDEC Original & Proprietary analysis solutions to master IP radiation performances in production flow to optimize hardening strategy before silicon State-of-the-art Rad-hard Design Platform CMOS65LP coming up extended corners for space (20 C), several VT flavors rad-hard IO s and PLL high performance standard cells ECC/EDAC-protected SRAM and ROM Leading-Edge Space Cell Libraries (HSSL) 10