Low-power carbon nanotube-based integrated circuits that can be transferred to biological surfaces

Transcription

1 SUPPLEMENTARY INFORMATION Articles In the format provided by the authors and unedited. Low-power carbon nanotube-based integrated circuits that can be transferred to biological surfaces Li Xiang, Heng Zhang, Guodong Dong, Donglai Zhong, Jie Han, Xuelei Liang, Zhiyong Zhang, Lian-Mao Peng and Youfan Hu * Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics, Peking University, Beijing, China. * youfanhu@pku. edu.cn Nature Electronics Macmillan Publishers Limited, part of Springer Nature. All rights reserved.

2 Supplementary Note Supplementary Note 1. Detailed fabrication process of the CNT-based electronics with bio-integration capability. The detailed fabrication steps are illustrated as below: 1. Spin-coat polyimide at 4000rpm (Sigma Aldrich) or sputtered Cu (100nm) layer on the silicon wafer. 2. Deposit SiO 2 (300nm) using plasma-enhanced chemical vapor deposition (PECVD) at E-beam evaporate 3nm Yttrium and oxidized at 240 for 1 hour and repeat Yttrium evaporation and oxidation again. The resulting oxidized Yttrium is ~10nm thick. 4. Photolithography to define the gate electrodes. E-beam evaporation of Ti / Au (5nm/30nm) followed by lift-off in REMOVER PG (MicroChem Corp). 5. Deposit 20nm HfO 2 using atomic layer deposition at Surface functionalization with hexamethyldisilazane (HMDS) monolayer: place the wafer in a glass desiccator filled with desiccant along with a 2 ml solution of HMDS (Sigma Aldrich) in an open glass vial. Then the desiccator was evacuated using house vacuum and put un an oven at 150 C for desired deposition time. 7. Carbon nanotube network (CNT) deposition. (a) To avoid the liquid erosion between the sacrificial layer and silicon wafer, we use a dip-machine to make the substrate lowered into the CNT solution and withdrawn at a controlled speed for 15 cycles for quick CNT deposition.

3 (b) The substrate was baked at 120 C for 30 mins at atmosphere by a hot plate to remove surfactant residures. 8. Pattern the CNT network as the active channel region by photolithography and inductively couple plasma (ICP) is used to remove the unwanted CNTs. 9. Photolithography to define the source/drain electrodes. E-beam evaporation of Ti / Pd / Au (0.5nm/40nm/30nm) followed by lift-off in REMOVER PG (MicroChem Corp). 10. Transfer the devices onto target substrate. (a-d) represent the wet etching process and the (e-f) represent the dry etching process. (a). Immerse a thermal release tape in DI water for half hour. Adhere the tape against the devices on silicon wafer. (b).soak the tape with the devices in FeCl 3 (sigma Aldrich) solution for 3 hour to remove the Cu sacrificial layer. (c). Gently rinse the tape with devices in DI water and dry under Nitrogen. (d). Press the tape against the target substrate on a hot plate (100 ) for 3 minutes to release the tape and complete the transfer procedure. (e). Mount the target substrate on a stamp of poly(dimethylsiloxane) (PDMS, Dow Corning Co., Ltd) with a moist surface. (f). Peel the polyimide with devices off the silicon wafer and transfer onto the target substrate. (g). Remove the polyimide using inductively couple plasma (ICP) to complete the transfer procedure.

4 Supplementary Figure Supplementary Figure 1. Detailed fabrication processes. a, Device fabrication on a silicon wafer with a sacrificial layer. b, Device transferring processes via a wet or a dry approach to the target substrate.

5 Supplementary Figure 2. Spatial layout of the electronic devices on the PVA substrate. a, Optical microscope image of the electronics on PVA. The magnified view of b, Transistor area, c, NAND, NOR, inverter area, and d, IC area. Scale bar in a, b, c, d represent 1 mm, 100 μm, 100 μm and 200 μm, respectively.

6 Supplementary Figure 3. Disintegrating behavior of the CNT-based electronics on PVA. Optical images in a time sequence of the electronics on the PVA substrate when immersed in DI water at room temperature. Because the PVA is a kind of water-soluble substrate, it will slowly dissolved when immersed in water, therefore, the devices and circuits on the substrates will physically disintegrate. Scale bar represent 5 mm.

7 Supplementary Figure 4. Conformal contact realized by the transfer method. Image shows the electronic devices and circuits still exhibit excellent conformal contact with the plant leaf even after the leaf become withered.

8 Supplementary Figure 5. Threshold voltage calculation. a, The V th is calculated by the intercept of the line extrapolated at the point of maximum transconductance. b, Linear scale transfer characteristics for 100 TFTs for V th calculation.

9 Supplementary Figure 6. C-V measurement setup and characteristics. a, C-V measurement setup in this work. The gate of the transistor is connected to the HIGH terminal while the source and drain electrodes connected to the LOW terminal of a semiconductor analyzer (4200-SCS, Keithley). b, C-V characteristic of a typical transistor obtained by using the wet etching process (measured at 10 khz). c, C-V characteristic of a typical transistor obtained by using the dry etching process (measured at 10 khz). The gate capacitances of the TFTs are obtained at a gate voltage V g = - 2 V, where the TFTs are at accumulation region. Therefore, the capacitance for calculating the carrier mobility can be used by normalizing the capacitance.

10 Supplementary Figure 7. Performance testing of the transferred devices/circuits on a curved leaf. A leaf with transferred devices/circuits on its surface was fixed on a bending stage to introduce deformation during electrical characterization. Images shown electrical measurements of transferred devices when the leaf was bent at a curvature radius, R, of a, 0.98 cm b, 0.87 cm c, 0.42 cm and d, 0.25 cm. The scale bars represent 1 cm.

11 Supplementary Figure 8. Voltage transfer characteristics, gain and noise margin of inverters. a, Voltage transfer characteristics (VTC) measured under different V dd of 1 V, 1.5 V and 2 V. b, Corresponding inverter gain of the inverter. c, Noise margin (NM) under different V dd. In this work, the operating voltage window is defined as input voltage from 0 V to V dd. For noise margin calculation, the points in VTC whose inverter gain equals -1 are defined as V IL and V IH, and the points whose gain equals -1 in the mirrored curve of VTC are defined as V OL and V OH, respectively. Therefore, the noise margin can be calculated as NM H =V OH -V IH and NM L =V IL -V OL. For switching threshold voltage (V sth ) calculation, the points with largest inverter gain are defined as the V sth.

12 Supplementary Figure 9. Uniformity of inverters. a, Output voltage of the inverters under the bias of V dd = 2 V. b, Noise margin of the inverters. All the parameters are calculated from the VTCs of 100 TFTs in Fig. 4c.

13 Supplementary Figure 10. Power consumption of a typical inverter. Power consumption characteristic of a typical inverter under a V dd of 2 V. It is calculated by the formula P = V dd I GND. The peak power consumption is occurred at the switch threshold voltage, where V in = V sth. And the lowest static power consumption is the minimum power consumption near the input voltage of 2 V.

14 Supplementary Figure 11. Characteristics of a half adder. a, Optical image (before and after transfer), b, Circuits diagram and c, Input-output characteristics of a half adder. Scale bars represent 200 μm.

15 Supplementary Figure 12. Characteristics of a 5-stage ring oscillator. a, Optical image (before and after transfer), b, circuit diagram and c, output waveform of a 5-stage ring oscillator after transfer. Scale bars represent 200 μm.

16 Supplementary Figure 13. A full adder and a ROM before transfer. Optical images of a, a full adder; b, a ROM. Scale bars represent 100 μm and 200 μm in a and b, respectively.

17 Supplementary Table Supplementary Table 1. Comparison of flexible ICs using CNTs.