Room-Temperature-Processed Flexible Amorphous InGaZnO Thin Film Transistor
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1 Supporting Information Room-Temperature-Processed Flexible Amorphous InGaZnO Thin Film Transistor Xiang Xiao 1, Letao Zhang 1, Yang Shao 1, Xiaoliang Zhou 2, Hongyu He 1, and Shengdong Zhang 1,2 * 1 School of Electronics and Computer Engineering, Shenzhen Graduate school, Peking University, Shenzhen 51855, China 2 Institute of Microelectronics, Peking University, Beijing 1871, China zhangsd@pku.edu.cn S-1
2 1 st Photolithography and Gate deposition Lift-off (c) Gate anodization (d) and depostion (f) anodization (e) 2 nd photolithography Anode Cathode Pt (g) 3 rd photolithography and wet-etching (h) tartrate acid: H 2 O: ammonium solution (25%): ethylene glycol= 6 g: 25 ml: 6 ml: 75 ml, PH= 7 Completed device Source Drain Source Drain Figure S1. Process flow of the full room-temperature flexible TFT. 1 st photolithography and (Gate) deposition by DC sputtering. Gate patterning by lift-off. (c) gate dielectric formation by anodization at room-temperature. (d) Deposition of and by DC sputtering in succession. (e) 2 nd photolithography. (f) In-situ localized anodization for passivation formation at S-2
3 J ( 1-8 A/cm 2 ) V anode V anode room-temperature. (g) 3 rd photolithography and wet-etching of and. (h) Final completed TFT on substrate. 14 CC mode CV mode Al 2 O 3 gate dielectric Anodization Time (s) CC mode CV mode Al 2 O 3 passivation layer Anodization Time (s) Figure S2. Evolution of anode voltage (Vanode) with the anodization time. a) Anodic formation of gate dielectric. b) In-situ anodic formation of passivation layer. (CC: Constant current, CV: Constant voltage) Electric Field (MV/cm) Voltage C ox (nf/cm 2 ) frequency:1 khz t ox = 18 nm r = Voltage 3 Figure S3. Properties of anodized dielectric. Breakdown characteristic. Capacitancevoltage characteristic. S-3
4 J leakage ( 1-8 A/cm 2 ) 3 25 Anodized (RT) PECVD SiO2 (15 C) PECVD SiO2 (3 C) Electric Field (MV/cm) Figure S4. Comparison of leakage current density between anodized and PECVD SiO2. (i) Ra = 3.62 nm Figure S5. (a~h) SEM images of sputtered and anodized with different power. (i) Atomic force microscope (AFM) image of the anodized. S-4
5 =.5V, 1V W=1 m L=36 m tartrate acid ammonium citric acid V TH SS (V/dec) Figure S6. IDS-VGS characteristic of the TFT with different anodization electrolyte during the anodization of passivation layer W=1 m L=16 m =1V Va= 55V, 61V, 65V, 7V, 8V FE (cm 2 /Vs) FE V TH SS Va Figure S7. Electrical performances of the TFT with different anodization voltage (Va) during the anodization of the passivation layer. IDS-VGS characteristics. Electrical parameters versus Va. S-5
6 SiO 2 Atmosphere Stress voltage =2V, RT W=5 m L=2 m =1V s 1s 1s 5s 1s 2s 3s SiO 2 Vacuum Stress voltage =2V, RT W=5 m L=2 m =1V s 1s 1s 5s 1s 2s 3s Figure S8. Positive gate-bias stress (PBS) stability of the PECVD SiO2 passivated BCE TFT on glass measured at room temperature, in atmosphere and in vacuum environment. The stress voltage is VGS = 2 V, VD = VS = V SiO 2 Atmosphere Stress voltage =-2V, RT W=5 m L=2 m =1V s 1s 1s 5s 1s 2s 3s SiO 2 Vacuum 1-5 Stress voltage 1-6 =-2V, 1-7 RT 1-8 W=5 m L=2 m 1-9 =1V s 1s 1s 5s 1s 2s 3s Figure S9. Negative gate-bias stress (NBS) stability of the PECVD SiO2 passivated BCE TFT on glass measured at room temperature, in atmosphere and in vacuum environment. The stress voltage is VGS = 2 V, VD = VS = V. S-6
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