Challenges and Requirements for Flexible Displays and Microelectronics

Transcription

1 Challenges and Requirements for Flexible Displays and Microelectronics Paul Wickboldt The Center for Advanced Microelectronics Manufacturing (CAMM), Binghamton Univ. AIMCAL Presentation October 25, 2006

2 Flexible Microelectronics is: Integrated circuits formed on flexible substrates Lines/interconnects, devices (passive and active) are formed together Additive or subtractive processes Direct or transfer processing Thick or thin films Organic or inorganic semiconductor films

3 Analogies to packaging R C 1. PCB to Flex R 2. Embedding passives C Embedded passives D R R C C Flexible microelectronics T S

4 Some of the efforts in this area:

5 Close to production in batch mode: Philips TFT backplanes by EPLaR: Electronics on Plastic by Laser Release 1.E-03 VDS = 10 V 1.E-04 1.E-05 VDS = V Isd (A) 1.E-06 1.E-07 1.E-08 W/L = 36 / 6 µm 1.E-09 µlin = 0.55 cm2/v.s µsat = 0.80 cm2/v.s 1.E-10 50mm x 50mm a-si:h TFT array on 3um thick polyimide 1.E-11 1.E-12 1.E Vgs (V) Being fabricated in the Thales Avionics LCD factory

6 Flexible AM displays are a DRIVER for development OLED Display Construciton Motivations AM Backplane Flexibility Form factor Light weight Rugged Proven large market (~$60B) but is it a killer application?

7 What will drive commercialization? Motivation AM Displays Flex Embedded passives Flexible X X Form Factor X Users may not pay X premium X for these. Weight X Many customers expect X lower cost!? Ruggedness X X Assembly Costs? However, premium is X inevitable for new technology. X? Production Costs X? X Roll-to-Roll Production?

8 Three Pathways to RTR: I. Low Performance/High Speed Factory Based on existing flexographic technologies High speed (>3meter/min.) Low performance (e.g. passive, L/S ~ 15mm) II. High Performance (matches typical AMLCD) a. Conventional Process Methods Based on conventional AM backplane processing Low Speed (~0.5 m/min) b. New technologies Achieve high performance with high-speed processing

9 I. Low Performance/High Speed Factory Basic Parameters Feature size ³ 15 microns Defects 5 micron managable Speed > 3 meters/min. Use existing tooling Low cost (<$0.10/sq.inch) Low performance (Passive, Reflective, Electrophoretic)

10 I. Low Performance/High Speed Factory Tools are available today: Coat/Bake Lithography OLEC AX28R Flex Circuit Photoaligner 610mm wide ~3m/min ~15 to 20 um Anvik HexScan 3100SRE 610 mm wide ~1 m/min ~10 um Frontier Industrial DynaCoat Slot-Die Coater Wet Clean/Etch Surface FinishingTechnology MP200 Stripper/Electroplate

11 I. Low Performance/High Speed Factory Tools are available today: Vacuum Deposition CHA Mark mm Sputter Evaporation PECVD Applied Films Smartweb 800 mm Modular 3 sputter guns/module Load-locked Bobst/General Vacuum Optilab 550 mm 3 sputter guns/module

12 I. Fully Integrated/Low Performance HOWEVER Barrier: needs a volume market! Example: ~$50M factory 300 mm web 3 meter/min >500,000 m2/yr Difficult to insert into market: competes with paper Investors must wait for market & infrastructure to develop

13 IIa. High Performance Conventional Methods Basic Parameters Assumes process available (e.g. a-si TFT on plastic) Feature size 4 micron Defects ³ 1 micron problematic Impurities critical Speed ~ 0.6 meters/min. Yield targets >95% Cost targets ~$1.00/sq. inch

14 IIa. High Performance Conventional Processing Several models predict ~2X or greater cost savings Modeled by JEM: Conventional TFT Backplane Process Conventional LTPS or a-si TFT backplane process 1.20 Gen2 Batch 1.00 Web length = 300 meter Cost/Area (Normalized) Roll-to-Roll Optimized, high capacity lines 0.80 Gen Speeds from 0.6 to 3 meter/min. Gen Gen5 Gen6 Gen7 Gen8 Similar results by AGI 0.20 Conservative estimate of cost advantage Width (mm)

15 IIa. High Performance Conventional Processing How is cost reduced? Equipment utilization improved Example: Equipment costs reduced Gen 7 TFT backplane Labor reduced Reduced handling Batch Total: $0.57/sq. inch Total: $0.33/sq. inch RTR $0.11 $0.23 MATERIALS LABOR $0.28 $0.17 FACILITIES EQUIPMENT $0.04 $0.02 $0.01 $0.04

16 IIa. High Performance Conventional Processing Approach: RTR as an extension of conventional cost reduction curve Batch RTR substrate size

17 Challenges for High Performance: Yeild Substrate Distortion Particles & Defects Impurities/contamination Bending/film stress Tool Set

18 Yeild Issue : Substrate Distortion Overlay requirement can be ±1 um across > 1meter! Thermal expansion Moisture absorption Film tension Particular problem for all plastics Can be avoided with metal foils Distortion compensation required in lithography By careful process management, can be kept below (100 to 200) ppm

19 Yeild Issue: Particles & Defects Dust, flakes, scratches, pinholes, cracks, etc. Typical FPD specification: Defect Size Density 0.5 to 1 <0.1 cm-2 1 to 4 < 0.05 cm-2 >4-0- Avoid front surface contact. Use of interleaf. Very different regime than for conventional converting Requires new tools to inspect and learn issues

20 Yeild Issue: Impurities & Contamination 1 In process: Semiconductors effected by ppm contamination, esp. metals Ø Vaccuum processing: 1E-7 Torr or better base desired Ø Continous processing of critical interfaces desired Ø Understand compatibility of tool materials Ø Management of outgassing!

21 Yeild Issue: Impurities & Contamination 2 Surface Contact: Critical interfaces damaged by air exposure and contact Use of interleaf to control surface contact Avoid surface contact

22 Yeild Issue: Bending/Film stress Stresses due to: Bending As-grown intrinsic film stress Substrate distortion s µ 1/R R Can cause structural failures: Cracking Delamination Significant issue for ITO! bubbles, etc. Ø Entirely process dependent Ø Much experience from converting industry (AIMCAL Defect Lexicon, etc.)

23 Challenges for High Performance:\ Tool set Tool Vacuum Deposition-PVD Vacuum Deposition-PECVD Status Not available to specification Photolithography Defect Inspection-optical Defect Inspection-electrical Available-not qualified Wet clean Wet Etch Wet Coat & bake Dry Etch Available & Close to qualification

24 High Performance Toolset New tools being developed: USDC/CAMM RTR Lithography System: Installation at CAMM in Nov Existing Azores 5500 Batch System Azores 6600 web lithography system 4um L/S (2.5um I-line) 200 to 610 mm webs 230 to 760 mm/min 400 ppm distortion compensation

25 High Performance Toolset: New tools being developed USDC/CAMM RTR High Vacuum System CHA Industries Mark 80 Mark 50 Used for Flex circuit, Packaging USDC development contract Focus on precision & yield for display manufacture

26 CHA Industries USDC funded Will be installed at CAMM in 07 Primary Specifications 8, 12 and 24 wide webs No front surface contact Up to five isolated process zones (modular) Source well for variety of sources Base <3E-7Torr Interleaf option Core/Roller dia. = 6 Skewing/Cross-web tension control

27 High Performance Toolset: New tools being developed: USDC Sencera LLC Linear high density plasma for CVD & Etch 1.2 meters High Density Plasma Source Modular design for insertion into coaters Argon, 2 mtorr, 2600 Watts. Density (x 1018 m-3) 6E+11 Plasma densities mid 1011 cm-3 at ~1mtorr (10% dissoc.) 5E+11 4E+11 3E+11 2E+11 Uniformity ±2% over 950mm 1E

28 High Performance Toolset: New tools being developed: USDC High Density Plasma Source Proven Electronic-Grade Dielectrics for TFTs Extremely low damage to films ECR properties over any length Capacitance (Farads) To be installed in FDC for batch mode processing As Deposited Charge Defect Density: 6 X 1010 cm-2 Applied Potential (V)

29 High Performance Toolset: New tools being developed: USDC/CAMM Defect/Particle Inspection ECD & Integral Vision Detection limit: 3 microns or less Web speed: 2 fpm or greater Generate defect maps Identify/classify images Delivery to CAMM in Spring 07

30 IIa. High Performance New Technologies Basic Parameters Feature size 4 micron Critical impurities control of ppm levels Speeds > 3 m/min Yield targets >95% Cost targets < $0.10/sq.inch.

31 IIa. High Performance New Technologies HP Labs SAIL: USDC-supported Self-Aligned-Imprint-Lithography 1: coated substrate 2: coat with polymer 3: emboss Self-compensates for distortions in substrate RTR Compatible 4: cure with UV Speed: demonstrated RTR at 20fpm Allows continous fabrication of full TFT stack (minimized interface issues) 5: release 6: etch

32 Imprinting: R2R Implementation Imprinting Roller Gravure Coater UV Lamp Cooling Air Supply Roll Take-up Roll 2 mm

33 Converging interests from other developing industries: Large Area Solid State Lighting Flex Circuit Packaging Low cost production of OLED panels Reduce L/S < 15um Embedded actives, passives Integrated passives, active High precision RTR electronics manufacturing Thin Film Photovoltaics Reduce cost Low Cost RFID New TFT technologies Improve yield Opportunity: pool resources and knowledge

34 CAMM (Center for Advanced Microelectronics Manufacturing) Located at Binghamton University (New York State) Launched in Jan 2005 Develop and demonstrate advanced integrated RTR manufacture of microelectronics Test site for USDC RTR projects Facilities provided by Endicott Interconnects Signing Ceremony Jan 05

35 CAMM Facility ELECTRICAL CABINET 22" X 12'6" ELECTRICAL CABINET 22" X 12'6" 24" pass thru lab analysis samples ~ 64,000 square feet per floor Lab -- 53,000 sq ft lab & Service Core sq ft

36 CAMM s Toolset Y Baseline Equipment/Process Conventional Wet Cleaning & Marking Azores Lithography Tool Wet Spray Chemical Process Precision Coat (Vendor) 14" UHV Coater (ITO - Metals) 24" UHV Coater Sputter Metals & ITO Dielectrics (Si & SiO2) PE-CVD (a-si) Evaporate Metals Particle Inspection Feature Inspection Precision Wet Coat / Bake Web Storage & Handling Low Resolution Lithography(conv.) For Development: Novel Equipment / Process Precision Cleaning Dry Etch (Si / Dielectrics) Dry Etch (metals) High throughput Lithography OLED Evaporation Y Y Underway. Clean room completion this month. Planning Forward Looking Setup/Test Qualified

37 The CAMM Will focus on building the physical and intellectual infrastructure to enable roll-to-roll electronics manufacturing Is initiating its program with $10M+ in tooling and facilities in a world class, R&D environment Hosted by Binghamton University, is strongly supported by Cornell University, Endicott Interconnect Technologies and USDC

38 Member Benefits Access to unique R2R tool set and processes Additional unique capabilities, e.g., system integration, micro-systems packaging, system reliability Reduces risk of investment in unique tool set Commercialize intellectual property Leverage university research and other federally funded work Binghamton University, Cornell University and other academic partner resources High ROI on membership due to pooling of resources Joint venture possibilities Business to Business Access to world-class faculty and students

39 CAMM Revenue Sources USDC equipment awards -- $10 million BU / NY State HTCC startup funds -- $ 2 million Federal and NY State peer reviewed grants Directed Federal and NY State grants Industrial Memberships: projected at 8 Full Partners and 12 to 15 Participating Members (number of full memberships limited so as to maintain focus) Industrial specific projects and test-beds

40 Joining the CAMM is the Right Strategic Move! R2R manufacturing will revolutionize many sectors of the electronics industry The CAMM will enable the R2R transition The CAMM offers a valuable set of opportunities for industrial partners Unique infrastructure of tools and processes IP development and commercialization Access to leading researchers Build Business to Business relationships Members will shape the technical and business structure of the CAMM