Innovative Technologies for RF & Power Applications

Transcription

1 Innovative Technologies for RF & Power Applications > Munich > Nov 14,

2 Key Technologies Key Technologies Veeco Market Focus Advanced Packaging, MEMS & RF Lighting, Display & Power Electronics Lithography Single Wafer Wet Etch and Clean Ion Beam Etch Scientific & Industrial Ion Beam Etch & Deposition MBE ALD Diamond-Like Carbon 34% 18% 14% 34% MOCVD Lithography Single Wafer Wet Etch and Clean Front-End Semiconductor Laser Spike Anneal 3D Inspection Ion Beam Etch Key Technologies Key Technologies 2

3 MOCVD and Metal Lift off steps in RF/Power devices RF/Power Amplifier Power Stack Metal Lift-Off MOCVD 3

4 RF & Power Electronics Solutions Key Veeco Technology Propel WaferStorm/WaferEtch Single-wafer reactor technology enables efficient, GaN-based power devices Single Wafer Metal lift off, PR Strip, Clean, and Etch processes for RF and Power Electronics Applications 4

5 MOCVD: Propel Single Wafer Technology 5

6 Propel Single Wafer Technology: Multiple Proven HVM Use Cases Power Si (6, 8 ) UV-LED Si nanowires RF SiC (4, 6 ) Si (8 ) Fine Pitch Saph. (6, 8 ) Si (8 ) Laser Diode GaN: (2 ) 6

7 Propel Single Wafer MOCVD Extendible to New Applications 1 st Semi style single wafer cluster tool for MOCVD GaN Power: Competitiveness over Si Lowest HVM epi costs with 8 wafers Tighter device parametrics distribution (Yield) Enable GaN integrated circuits GaN RF: GaN on Si & SiC for 5G Platforms Low loss buffer on SiC and high resistivity Si Low sheet resistance (< 200 W/sq) 10 GHz 100 GHz capable power amplifiers Best in class 8 performance Extendible to 300 mm wafers 300 mm Extendibility: New Applications GaN on Si for RF MMICs GaN on Si for Blue/Green Fine Pitch LEDs GaAs on Si for lower cost VCSELs InP / InGaAs on Si for integrated RF modules 7

8 Propel: RF & Power 8

9 What does GaN Epi have to deliver? Device Requirements Hi hi voltage Low harmonic distortion Low transmission loss Reliability Compact form factor Low cost Epi Requirements for GaN-SiC/Si Low R sh (< 250 Ω/ ) High saturation velocity High 2DEG (> 2x10 13 /cm 2 ) Low charge trapping Additional Epi Requirements for GaN-Si Low loss buffer Crystal quality (< 400 arc sec) 9

10 InAlN Helps Reduce Rsh for RF devices R sh 210 Ω/ ; < 2% 1σ Thickness Control: Max- Min: < 1% on 8 % In Control: Max- Min: <0.8% on 8 Extremely uniform temperature control helps achieve high uniform InAlN Good structural quality with well defined layer peak & fringes 10

11 Propel Provides Sharp Interfaces & No Memory Effects Sharp InAlN/GaN interface, <100ppm Ga carry-over Rapid turn-on / turn-off for Fe Established Protocol to Avoid Fe Carryover Dopant profile control for Mg in pgan is critical for Power devices & LEDS 11

12 Epi challenges for high voltage Power devices AlGaN Barrier GaN Channel C doped blocking layer High breakdown voltage & low leakages requires thicker stacks that result in: Long process times => Cost Wafer Stress => Edge artifacts Super Lattice Buffer layers AlN layer 8 Si (111) Propel Single Wafer provides : Wider process window Fast transition between steps Hot transfer & Turbo ramp Wafer edge stress management Full stack uniformity 0.88%, 1 (C-doped 8% AlGaN) 12

13 Single Wafer Technology Improves Power Devices CoO 5,5 5 4,5 4 3,5 3 2,5 2 CoO improvement with faster recipes Batch 8hr Recipe 4.5hr Recipe 4hr Recipe Wafer stress reduction for 725um Si 550V 660V 610V Propel Epi helps GaN become cost competitive to Si super junction at device level 13

14 Single Wafer MOCVD Lowers Epi Costs for 200 mm Wafers CoO Building Blocks High Productivity: >30 WPD (650V) High Uptime: >95% Low Parts & Gas Consumption Cluster: Capital & Footprint Efficiency Thick Stacks (> 4.5µm) > 650V Power Devices 1X Thin Stacks (< 2µm) 200V Power Devices & RF 0.6X 1X 0.5X 14

15 Precision Surface Processing (PSP) 15

16 Material Lift off (MLO) for RF & Power Applications Key Challenges Effective removal of difficult to etch material MLO Layers: Emitter metal Ti/Pt Base metal Pt/Ti Collector Metal Au/Ge/Ni Thin Film Resistor NiCr Metal0 Ti/Pt/Au MIM metal Ti/Pt/Au Material removal without damaging substrate Electrostatic discharge Substrate scratches Reduce cost (capital cost and chemistry usage) 16

17 ImmJET Metal Lift-Off Process Sequence IMMERSION STEP Lift-Off Polymer with negative angle Metal Deposited PR Solvent penetrates underlying photo resist Photo resist swells, breaks up and dissolves HIGH PRESSURE SPRAY STEP Flow of solvent will remove residual PR and lift metal off surface Clean metal pattern remains * Force required to completely remove PR influenced by Solubility of PR, Thickness of PR and Metal, Lift-Off structure angle 17

18 ImmJET for Material Lift-Off with NMP or DMSO ImmJET 6 Chamber Tool Combination Batch Immersion and Single Wafer Spray Wafer Input Immersion 1 HPC 1 SRD 1 Immersion 2 HPC 2 SRD 2 Immersion in Inert Environment Single Wafer Soak Processing Solvent Wet Wafer Transfers Solvent High Pressure Spray Heated, Re- Circulated Solvents Precision control of time, agitation, other required steps Maintain Solvent Film with 4-Blade Robot Heated, Recirculated with Flow Rate Control 18

19 Material Lift off (MLO) for RF & Power Applications WaferStorm Metal Lift Off: 2x throughput versus competitor single wafer technology 5x lower chemistry usage vs wet bench Single Wafer Metal lift off, PR Strip & Clean Industry leader in removing difficult to lift off materials Over 500 systems installed at major power electronics and RF manufacturers Successful Lift off in < 1um L/S features Pre Post 19

20 Summary Propel Single Wafer Reactor leverages semi standard design to deliver: > Best Film properties across broad application portfolio with Run to run stability 1. WiW uniformity with run to run stability and longest campaigns 2. Enabling technologies like InAlN with Minimal memory effects > Lowest Epi Cost due to 1. Highest productivity with lowest recipe times 2. Lowest consumables WaferStorm Single Wafer system leverages ImmJet TM technology to deliver > Best material removal performance without causing surface damage > Lowest Cost of Ownership 1. 5x lower chemistry usage than batch systems 2. 2x higher throughput versus other single wafer systems 20

21 Thank You 21