State-of-The-Art Dielectric Etch Technology

Transcription

1 State-of-The-Art Dielectric Etch Technology Koichi Yatsuda Product Marketing Manager Etch System Business Unit November 5 th, 2010 TM

2 Outline Dielectric Etch Challenges for State-of-The-Art Devices Control Parameters of CCP Basic Components of Dielectric Etch Chamber Physical Effects of DC Superposition and Etch Applications DC Superimposed CCP with RF Pulsing Potential Solutions toward Plasma Induced Material Damage Self-limiting Chemical Dry Etch Summary 2

3 Dielectric Etch Challenges for State-of-The-Art Devices TM

4 FEOL Dielectric Etch Challenges FinFET Sidewall Transfer LWR/LER Channel CD Trim Sel. to Mask Epitaxial growth for Source/Drain Iso/Dense CD Bias Recess Etch Recess Control Low Cristal Damage FinFET requires minimum LWR/LER and ultra low Si crystal damage with reproducible etch amount for dielectric etch. 4

5 Contact Etch Challenges guard ring CD Shrink short line/trench circle oval dual stress liner nickel silicide Sel. to CESL Sel. to NiSi & SiO2 Striation vs. GR Residue Defect Uniformity As scaling down CDs, RIE needs to compensate the narrow lithography margin, and also needs to deal with new materials and new device structures. 5

6 BEOL Dielectric Etch Challenges Tri-layer/resist scheme challenges Low-k damage Common challenges Defect Metal hard mask scheme challenges Sel. to Ti/TiN Striation Trench Depth, Uniformity Metal sputtering Reproducibility Sel. to ESL Trench surface roughness Cu (alloy) damage Sel. to Cu (alloy) Cu (alloy) damage Etch control parameters changes, depending on the dual damascene scheme. VFTL (Tri-layer resist scheme): low-k damage, striation, trench depth TFVL (Metal hard mask scheme): sel. to MHM, reproducibility, trench depth 6

7 HAR Dielectric Etch Challenges Sel. to Mask Distortion/Twisting Contact area variation Bowing Leakage between capacitors Sel. to ESL Bottom CD Etch Rate Uniformity Ref.: M. Wang (M. Kushner), AVS 2008 As scaling down CDs, new plasma control techniques need to be implemented into high aspect ratio dielectric etch. 7

8 Control Parameters of CCP TM

9 Basic Components of Dielectric Etch Chamber Multiple zone gas supply for radical distribution control Source RF power Option: Frequency selection Wafer edge ring for electron density uniformity ESC for wafer clamping Source RF power Option: Frequency selection Bias RF power Option: Frequency selection, single or dual 9

10 DC Superimposed CCP Negative DC Voltage Plasma generation Source RF Source RF Bias RF Bias RF Ion energy control Negative DC Potential control Negative DC voltage can control potential difference between the upper electrode and plasma. Superimposed DC voltage controls ion bombardments at the upper electrode, which change F* density and generate ballistic electrons. Superimposed DC voltage is another plasma process parameter. 10

11 Significance of Voltage Control of Upper Electrode Effect of interaction between Si-electrode and fluorocarbon plasma Negative DC Voltage Source RF Bias RF F, Si, CF, CF2, and CF3 radical density change as a function of Top Vdc applied to UEL. 98 GEC & ICRP: Sekine, et al. Potential difference between the upper electrode and plasma varies F/CF x radical ratio, which determines selectivity and etch profile. It is important to control potential between plasma and upper electrode for dielectric etch. 11

12 Mechanism of The Ballistic Electron s Generation Wafer Superimposed Negative DC UEL Collide Acc. Emitted Secondary e - Positive ions Acc. Ballistic electron beam Positive ions are accelerated towards the upper electrode by superimposed negative DC, and collides with the upper electrode. As a result, secondary electrons are emitted from the surface, and are accelerated in the sheath on the upper electrode. Consequently, ballistic electron beam is generated. 12

13 Ballistic Electron Effect nm Resist Cross-sectional SEM images of the 193 nm resist blanket wafers processed with various DC voltages Without DC DC = V DC = V DC = V 0 nm (0 nm) 22 nm (18 nm) 83 nm (61 nm) 173 nm (119 nm) Modified layer thickness Modified layer (nm) thickness [nm] Modified layer Deposition subtraction CF4, 100 mt, 5 x cm 3, Vpp = 70 V, 60 sec. Modified layer becomes thicker as DC voltage increases. Increase in total film thickness indicates polymer deposition. Thus, modified layer should consist of polymer and actual resist modification. Applied DC voltage Voltage [V] (V) 13

14 Verification of e-beam Effect Suspended electron ratio (%) Calculated suspended electron ratio in the bulk resist with various accelerated voltage 停止した電子の割合 (%) V 1000V 1500V Energy(keV) 0.5keV 1keV 1.5keV 2keV 電子が停止した深さ (nm) Depth of suspended electron (nm) Modified layer thickness of the experiment (nm) Correlation between modified layer thickness and the e - suspended depth in the bulk resist y = x R 2 = e - suspended depth in the bulk resist calculated by MC simulation (nm) The actual modified layer, subtracting polymer deposition thickness, agreed with the Monte-Carlo simulation results. 14

15 Ballistic Electron Effect 2 HAR Dielectric For DRAM hp 3x and beyond, high aspect ratio etching > 40:1 is required. HAR etching without distortion and twisting is the most difficult challenge. Ref: M.Wang, M.Kushner et al. 55 th AVS (2008) secondary electron e ESC e - + DC RF Ballistic electrons contribute to neutralizing positively charged dielectric surface, and prevent etch profile from twisting. 15

16 Motivation of RF Pulsing for DC Superimposed CCP V bias = 0 V V bias = 1000 V The population of ballistic electron onto wafer decreases with high bias power. 16

17 Potential Solutions towards Plasma Induced Material Damage Self-limiting Chemical Dry Etch TM

18 Performance of Self-limiting Etch 25.0 Etching (nm) mT 10mT Etching time (min) Blanket Th-Ox Process recipe can control the maximum etch amount. 18

19 Summary Control Parameters of CCP Basic Components of Dielectric Etch Chamber source frequency, bias frequency, dual bias Physical Effects of DC Superposition and Etch Applications resist hardening, high aspect ratio dielectric etch, BEOL dielectric etch with metal hard mask DC Superimposed CCP with RF Pulsing enhancement of dumping current Potential Solutions towards Plasma Induced Material Damage Self-limiting Chemical Dry Etch no silicon crystal damage with precise etch amount control 19