Wireless Metrology in Semiconductor Manufacturing

Size: px
Start display at page:

Download "Wireless Metrology in Semiconductor Manufacturing"

Transcription

1 1 Wireless Metrology in Semiconductor Manufacturing Costas J. Spanos Seminar

2 2 Outline Historical perspective Hardware and software applications Breakthroughs that have yet to be realized Distributed control and diagnostics Hardware requirements

3 3 Past And Present Ideas and even patents circulated in the industry since the early 90s. No known implementation since UCB work started in late 1997 Commercialized in 2000 by OnWafer Technologies Founders from UCB and LAM Research BakeTemp for Post Exposure Bake PlasmaTemp An expanding software applications suite

4 4 Smart Sensor Wafers In-situ sensor array, with integrated power and telemetry Applications: process control, calibration, diagnostics & monitoring, process design

5 5 Sacrificial, On-wafer Sensors Temperature Compensated Design of Etch Rate Sacrificial Sensor Each sensor has a buried temperature reference I I Exposed Buried V temp V th

6 6 Wired Proof of Concept Implementation 100mm

7 7 Results - bakeplate Wafer placed on bakeplate, R s measured for both sensors

8 8 Results - XF 2 Etch Temperature-induced offset cancelled 13Å average

9 9 Wireless Prototype ~1999 Off-the Shelf Components, Ni on Al, Solder Paste Mount LED batteries PIC voltage regulator thermistor resistor capacitors 4 Sensors 4 o C Accuracy 2 o C Precision 1 oo C Resolution Primary Batteries No Memory Fixed Behavior ~15grams/ 100mm 5mm

10 10 Thermal Stress Tests on Calibrated Plate

11 11 Autonomous Passage Through Wafer Track Wafer arrives at at chill chill plate Non-uniform bake Non-uniform cooling Wafer leaves bake plate

12 12 RF isolation of wafer; isn t it ugly? Standard temperature wafer covered with layer of epoxy Epoxy is transparent to infrared: LED can be used for data transmission

13 13 Test results in plasma: RF 50W, 0.76 Torr, O 2 sensor 1 sensor 2 Word s first Wireless Plasma Monitoring Late 1999! sensor 3 sensor 4

14 14 Test results in plasma: RF 100W, 0.76 Torr, O 2 sensor 1 sensor 2 Word s first Wireless ~High Power Plasma Monitoring! sensor 3 sensor 4

15 15 A Commercial Smart Dummy? (Sept 2000) Courtesy of OnWafer Technologies, Inc.

16 16 Outline Historical perspective Hardware and software applications Breakthroughs that have yet to be realized Distributed control and diagnostics that go beyond lithography and etch Hardware requirements

17 17 Today: The BakeTemp Sensor Wafer polyimid SiO Sensors Sensors 4 o C Accuracy 0.05 o C Accuracy 2 o C Precsion 0.02 o C Precision 1 oo C Resolution oo C Resolution Primary Batteries Secondary module Batteries No Memory Memory Fixed Behavior Programmable/Adaptive Behavior ~15grams/ Courtesy 5mm OnWafer Technologies ~1.5grams/ 3mm

18 18 Much more than you ever wanted to know about Post Exposure Bake Overshoot Steady Heating Cooling 200mm ArF 90nm 130 o C 60sec Courtesy OnWafer Technologies Chill

19 19 Today: The PlasmaTemp Sensor Wafer Demonstrated in up to 7,000W Chambers Reusable Clean and safe enough to be adopted by all the top tier fabs

20 20 On-Wafer Plasma Monitoring 200mm Poly Etching Routine He Reduced He main etch pre-etch over etch de-chuck

21 21 Cool chuck - 200mm Poly Etching main etch Temperature fluctuations during main etch

22 22 Can see rotating magnetic field! phase delay in temp fluctuation Can calculate B-field period Can see rotation is clockwise

23 23 What are the Killer Apps? Temperature Monitoring has intuitive diagnostic value for some users. To expand use from Pilot to Production, we must address different, routine needs. Calibration Acceptance SPC/SQC

24 24 Post Exposure Bake Track Equipment Complexity is Increasing 10 Years of Product Evolution Single Zone Control Multi-Zone Control PEB Evolved from a Single Zone to Multi-Zone Control System Why?

25 25 PEB Hotplate Thermal Profile Optimization System Plate Type Specific Thermal Profile Modeling Engine AutoCal Baseline Thermal Profile Condition Input Input BakeTemp & OnView Offset Generator Engine Output OnWafer Technologies Offset Values Optimized for Both Within-Plate and Plate-to-Plate Thermal Profile Uniformities

26 26 PEB Temp Control Before After Target = 120 o C o C o C 16 plates, 120 ºC Target OnWafer Technologies

27 27 Spatial PEB/CD Distribution Correlation Plotting both the bake plate temperature trajectory and R 2 from temperature-cd correlation against bake time: Max R 2 during the transient heating period Continued high R 2 during steady state due to poor temperature control in single-zone plate design

28 28 PEB Hotplate Critical Dimension Optimization System Plate Type Specific Thermal Profile Modeling Engine AutoCal Resist & Litho Cell Specific CD Modeling Engine AutoCD Baseline Thermal Profile Condition Input Input BakeTemp & OnView Offset Generator Engine Input Input Output Baseline CD Profiles per Plate Offset Values Optimized for Both Within-Plate and Plate-to-Plate Critical Dimensions Uniformities Customer Provided OnWafer Technologies

29 29 CDU Improvement AutoCD AutoCal 1 POR Across Plate OnWafer Technologies Plate to Plate AutoCal AutoCD POR

30 30 What we learned about Lithography Weight / Form Factor module electronics, height, wafer flatness Precision Speed Equipment Compatibility Contamination COST OF OWNERSHIP Lifetime Ease of Use

31 31 Killer Lithography Applications 0 Monitor/Diagnose Multi-zone plates, complex exhaust systems, precise transport timing and placement. Plate C is still stabilizing before after 0 0 W1 W2 W3 Avg W1 W2 W3 Avg W1 W2 W3 Avg Plate A Plate B Plate C Plate response errors.

32 32 What we learned from Plasma RF/heat tolerance Arcing resistance Shape/size Contamination Lifetime and reliability

33 33 Killer Plasma Apps Temperature monitoring Automatic Calibration/Diagnosis??? Equipment Compatibility Power Range RF Tolerance Chemistry Contamination Arcing Tolerance

34 34 Outline Historical perspective Hardware and software applications Breakthroughs that have yet to be realized Distributed control and diagnostics Hardware requirements

35 35 The limitations Shape, Size and Weight Surface mount electronics min ~2mm Needs thin film wafer interconnect to achieve ~10µm flatness Integrated (in Si) electronics still prohibitive for a consumable product Lifetime Battery Films (Plasma, CMP) Performance Envelope Battery up to 200 o C Electronics up to 300 o C

36 36 Shape Size and Weight Zero Footprint Wafer Data Transmission Dielectric Layer as Optical Window Photo-/RF Transmitter Metrology wafer to monitor and map optical reflectance and interference of surface layers Prototyping a zero-footprint optical metrology wafer for real-time monitoring of dielectric film deposition/etching, resist curing/development and metal etch end-pointing Si Battery Professor Nathan Cheung and Students Data Acquisition Unit 500µm

37 37 Batteries Lifetime Button cell secondary commercial solutions not available above 80 o C. Primary solutions are a bit bulky but can go up to 140 o C. Lithium-based thin film technologies still immature, not focused on high temp applications. Temporary solution: screen commercial batteries, make them field replaceable (160 o C ceiling, 10s of hours of operation) Long term solution: wait for high temperature cathode thin film batteries (~200 o C ceiling, 100s of hours) Films Inherent Limitation in Etch just make it thick and provide visible thread wear marks. Might be replaceable in CMP

38 38 Performance Envelope High Temperature Electronics Off the shelf electronics (surface mount or hybrid) ~ 180 o C. Off the shelf electronics with custom clocking ~240 o C. High Temperature Batteries will probably not happen above 200 o C Parasitic power sources / caps

39 39 Expanding Aerial Image Chemical Mechanical Planarization Wet processing Ion Beam PVD CVD RTP??? Automatic Deployment

40 40 Aerial Image Sensor Concept Data acquisition process: Aperture Mask Photodetector High spatial frequency aerial image Aperture mask transmission ( m + n) P + x x Low spatial frequency detector signal

41 41 Choosing Aperture Width & Thickness (cont.) Near-Field Simulation: ( m+ n) P+ x x Illumination phase shift o o Aperture groups phase moving at max min position

42 42 Outline Historical perspective Hardware and software applications Breakthroughs that have yet to be realized Distributed control and diagnostics Hardware requirements

43 PA Bake Spin Exposure HMDS PEB Thin Thin Film Film FB/FF FB/FF Control Control Develop PD Bake 43 Pattern Transfer Control Aerial Image Temperature Etch Feed-forward control control Poly Etch Etch System Temperature, Temperature, Plasma Plasma Voltage, Voltage, Ion Ion Current Current FF/FB FF/FB Control, Control, chuck chuck diagnostics diagnostics Etch Scatterometry Feedback Control Photoresist Removal Scatterometry FB/FF Control Scatterometry Profile Inversion Feedback Control Electrical Testing

44 44 Outline Historical perspective Hardware and software applications Breakthroughs that have yet to be realized Distributed control and diagnostics Hardware requirements

45 45 Automatic Deployment Wireless Wafers must resemble real wafers as much as possible. In a 300mm factory, they must reside in FOUPs and move around via overhead transport. Deployment, data collection, analysis and resulting actions must be automated.

46 46 Batteries! Other Breakthroughs Needed Or, maybe, parasitic power sources full-wafer gate cap is 2 orders of magnitude too small RF pickup coils in plasma have almost unlimited power High temperature electronics! Silicon Carbide Devices about 250 o C Or, maybe thermal isolation for limited time

47 47 Conclusion Wireless Semiconductors Metrology has gone a long way since we started in 1998 Three vendors Officially Adopted by Fabs and Tool Makers Best Known Method (BKM) in several applications Target processes remain in Lithography and Etch, but others are not too far behind Next generation of zero footprint metrology is likely to expand the application base even more

Feature-level Compensation & Control

Feature-level Compensation & Control Feature-level Compensation & Control 2 Sensors and Control Nathan Cheung, Kameshwar Poolla, Costas Spanos Workshop 11/19/2003 3 Metrology, Control, and Integration Nathan Cheung, UCB SOI Wafers Multi wavelength

More information

( 2) ρ π V. Index Terms Sensor wafer, autonomous operation, in-situ data acquitsition, wireless communication INTRODUCTION

( 2) ρ π V. Index Terms Sensor wafer, autonomous operation, in-situ data acquitsition, wireless communication INTRODUCTION Real Time In-Situ Data Acquisition Using Autonomous On-Wafer Sensor Arrays Mason Freed, Michiel Krüger, Kameshwar Poolla, and Costas Spanos BCAM-Group, Univeristy of California at Berkeley, 5105 Etcheverry

More information

Kalman Filtering Methods for Semiconductor Manufacturing

Kalman Filtering Methods for Semiconductor Manufacturing Kalman Filtering Methods for Semiconductor Manufacturing Kameshwar Poolla Mechanical Engineering Electrical Engineering University of California Berkeley Outline Kalman Filtering Overview Ingredients Applications

More information

Feature-level Compensation & Control. Sensors and Control September 15, 2005 A UC Discovery Project

Feature-level Compensation & Control. Sensors and Control September 15, 2005 A UC Discovery Project Feature-level Compensation & Control Sensors and Control September 15, 2005 A UC Discovery Project 2 Current Milestones Integrated sensor platform development 2 (M26 YII.16) Gather CMP and etching rate

More information

Section 2: Lithography. Jaeger Chapter 2 Litho Reader. The lithographic process

Section 2: Lithography. Jaeger Chapter 2 Litho Reader. The lithographic process Section 2: Lithography Jaeger Chapter 2 Litho Reader The lithographic process Photolithographic Process (a) (b) (c) (d) (e) (f) (g) Substrate covered with silicon dioxide barrier layer Positive photoresist

More information

IWORID J. Schmitz page 1. Wafer-level CMOS post-processing Jurriaan Schmitz

IWORID J. Schmitz page 1. Wafer-level CMOS post-processing Jurriaan Schmitz IWORID J. Schmitz page 1 Wafer-level CMOS post-processing Jurriaan Schmitz IWORID J. Schmitz page 2 Outline Introduction on wafer-level post-proc. CMOS: a smart, but fragile substrate Post-processing steps

More information

Section 2: Lithography. Jaeger Chapter 2 Litho Reader. EE143 Ali Javey Slide 5-1

Section 2: Lithography. Jaeger Chapter 2 Litho Reader. EE143 Ali Javey Slide 5-1 Section 2: Lithography Jaeger Chapter 2 Litho Reader EE143 Ali Javey Slide 5-1 The lithographic process EE143 Ali Javey Slide 5-2 Photolithographic Process (a) (b) (c) (d) (e) (f) (g) Substrate covered

More information

Lithography. 3 rd. lecture: introduction. Prof. Yosi Shacham-Diamand. Fall 2004

Lithography. 3 rd. lecture: introduction. Prof. Yosi Shacham-Diamand. Fall 2004 Lithography 3 rd lecture: introduction Prof. Yosi Shacham-Diamand Fall 2004 1 List of content Fundamental principles Characteristics parameters Exposure systems 2 Fundamental principles Aerial Image Exposure

More information

Part 5-1: Lithography

Part 5-1: Lithography Part 5-1: Lithography Yao-Joe Yang 1 Pattern Transfer (Patterning) Types of lithography systems: Optical X-ray electron beam writer (non-traditional, no masks) Two-dimensional pattern transfer: limited

More information

Photolithography I ( Part 1 )

Photolithography I ( Part 1 ) 1 Photolithography I ( Part 1 ) Chapter 13 : Semiconductor Manufacturing Technology by M. Quirk & J. Serda Bjørn-Ove Fimland, Department of Electronics and Telecommunication, Norwegian University of Science

More information

Semiconductor Manufacturing Technology. Semiconductor Manufacturing Technology. Photolithography: Resist Development and Advanced Lithography

Semiconductor Manufacturing Technology. Semiconductor Manufacturing Technology. Photolithography: Resist Development and Advanced Lithography Semiconductor Manufacturing Technology Michael Quirk & Julian Serda October 2001 by Prentice Hall Chapter 15 Photolithography: Resist Development and Advanced Lithography Eight Basic Steps of Photolithography

More information

Photolithography Technology and Application

Photolithography Technology and Application Photolithography Technology and Application Jeff Tsai Director, Graduate Institute of Electro-Optical Engineering Tatung University Art or Science? Lind width = 100 to 5 micron meter!! Resolution = ~ 3

More information

Section 2: Lithography. Jaeger Chapter 2. EE143 Ali Javey Slide 5-1

Section 2: Lithography. Jaeger Chapter 2. EE143 Ali Javey Slide 5-1 Section 2: Lithography Jaeger Chapter 2 EE143 Ali Javey Slide 5-1 The lithographic process EE143 Ali Javey Slide 5-2 Photolithographic Process (a) (b) (c) (d) (e) (f) (g) Substrate covered with silicon

More information

Photolithography II ( Part 2 )

Photolithography II ( Part 2 ) 1 Photolithography II ( Part 2 ) Chapter 14 : Semiconductor Manufacturing Technology by M. Quirk & J. Serda Saroj Kumar Patra, Department of Electronics and Telecommunication, Norwegian University of Science

More information

CMOS Digital Integrated Circuits Lec 2 Fabrication of MOSFETs

CMOS Digital Integrated Circuits Lec 2 Fabrication of MOSFETs CMOS Digital Integrated Circuits Lec 2 Fabrication of MOSFETs 1 CMOS Digital Integrated Circuits 3 rd Edition Categories of Materials Materials can be categorized into three main groups regarding their

More information

EE143 Fall 2016 Microfabrication Technologies. Lecture 3: Lithography Reading: Jaeger, Chap. 2

EE143 Fall 2016 Microfabrication Technologies. Lecture 3: Lithography Reading: Jaeger, Chap. 2 EE143 Fall 2016 Microfabrication Technologies Lecture 3: Lithography Reading: Jaeger, Chap. 2 Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1-1 The lithographic process 1-2 1 Photolithographic

More information

Contrast Enhancement Materials CEM 365HR

Contrast Enhancement Materials CEM 365HR INTRODUCTION In 1989 Shin-Etsu Chemical acquired MicroSi, Inc. including their Contrast Enhancement Material (CEM) technology business*. A concentrated effort in the technology advancement of a CEM led

More information

immersion optics Immersion Lithography with ASML HydroLith TWINSCAN System Modifications for Immersion Lithography by Bob Streefkerk

immersion optics Immersion Lithography with ASML HydroLith TWINSCAN System Modifications for Immersion Lithography by Bob Streefkerk immersion optics Immersion Lithography with ASML HydroLith by Bob Streefkerk For more than 25 years, many in the semiconductor industry have predicted the end of optical lithography. Recent developments,

More information

Process Optimization

Process Optimization Process Optimization Process Flow for non-critical layer optimization START Find the swing curve for the desired resist thickness. Determine the resist thickness (spin speed) from the swing curve and find

More information

UV Nanoimprint Stepper Technology: Status and Roadmap. S.V. Sreenivasan Sematech Litho Forum May 14 th, 2008

UV Nanoimprint Stepper Technology: Status and Roadmap. S.V. Sreenivasan Sematech Litho Forum May 14 th, 2008 UV Nanoimprint Stepper Technology: Status and Roadmap S.V. Sreenivasan Sematech Litho Forum May 14 th, 2008 Overview Introduction Stepper technology status: Patterning and CD Control Through Etch Alignment

More information

Applications of Maskless Lithography for the Production of Large Area Substrates Using the SF-100 ELITE. Jay Sasserath, PhD

Applications of Maskless Lithography for the Production of Large Area Substrates Using the SF-100 ELITE. Jay Sasserath, PhD Applications of Maskless Lithography for the Production of Large Area Substrates Using the SF-100 ELITE Executive Summary Jay Sasserath, PhD Intelligent Micro Patterning LLC St. Petersburg, Florida Processing

More information

200mm and 300mm Test Patterned Wafers for Bonding Process Applications SKW ASSOCIATES, INC.

200mm and 300mm Test Patterned Wafers for Bonding Process Applications SKW ASSOCIATES, INC. C M P C h a r a c t e r I z a t I o n S o l u t I o n s 200mm and 300mm Test Patterned Wafers for Bonding Process Applications SKW ASSOCIATES, INC. 2920 Scott Blvd., Santa Clara, CA 95054 Tel: 408-919-0094,

More information

Hermetic Packaging Solutions using Borosilicate Glass Thin Films. Lithoglas Hermetic Packaging Solutions using Borosilicate Glass Thin Films

Hermetic Packaging Solutions using Borosilicate Glass Thin Films. Lithoglas Hermetic Packaging Solutions using Borosilicate Glass Thin Films Hermetic Packaging Solutions using Borosilicate Glass Thin Films 1 Company Profile Company founded in 2006 ISO 9001:2008 qualified since 2011 Headquarters and Production in Dresden, Germany Production

More information

Device Fabrication: Photolithography

Device Fabrication: Photolithography Device Fabrication: Photolithography 1 Objectives List the four components of the photoresist Describe the difference between +PR and PR Describe a photolithography process sequence List four alignment

More information

FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag

FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag FABRICATION OF CMOS INTEGRATED CIRCUITS Dr. Mohammed M. Farag Outline Overview of CMOS Fabrication Processes The CMOS Fabrication Process Flow Design Rules Reference: Uyemura, John P. "Introduction to

More information

Lecture 7. Lithography and Pattern Transfer. Reading: Chapter 7

Lecture 7. Lithography and Pattern Transfer. Reading: Chapter 7 Lecture 7 Lithography and Pattern Transfer Reading: Chapter 7 Used for Pattern transfer into oxides, metals, semiconductors. 3 types of Photoresists (PR): Lithography and Photoresists 1.) Positive: PR

More information

Micro-sensors - what happens when you make "classical" devices "small": MEMS devices and integrated bolometric IR detectors

Micro-sensors - what happens when you make classical devices small: MEMS devices and integrated bolometric IR detectors Micro-sensors - what happens when you make "classical" devices "small": MEMS devices and integrated bolometric IR detectors Dean P. Neikirk 1 MURI bio-ir sensors kick-off 6/16/98 Where are the targets

More information

Critical dimension sensitivity to post-exposure bake temperature variation in EUV photoresists

Critical dimension sensitivity to post-exposure bake temperature variation in EUV photoresists Critical dimension sensitivity to post-exposure bake temperature variation in EUV photoresists Jason P. Cain, a* Patrick Naulleau, b Costas J. Spanos a a Department of Electrical Engineering and Computer

More information

Contrast Enhancement Materials CEM 365iS

Contrast Enhancement Materials CEM 365iS INTRODUCTION In 1989 Shin-Etsu Chemical acquired MicroSi, Inc. and the Contrast Enhancement Material (CEM) technology business from General Electric including a series of patents and technologies*. A concentrated

More information

Holistic View of Lithography for Double Patterning. Skip Miller ASML

Holistic View of Lithography for Double Patterning. Skip Miller ASML Holistic View of Lithography for Double Patterning Skip Miller ASML Outline Lithography Requirements ASML Holistic Lithography Solutions Conclusions Slide 2 Shrink Continues Lithography keeps adding value

More information

PHGN/CHEN/MLGN 435/535: Interdisciplinary Silicon Processing Laboratory. Simple Si solar Cell!

PHGN/CHEN/MLGN 435/535: Interdisciplinary Silicon Processing Laboratory. Simple Si solar Cell! Where were we? Simple Si solar Cell! Two Levels of Masks - photoresist, alignment Etch and oxidation to isolate thermal oxide, deposited oxide, wet etching, dry etching, isolation schemes Doping - diffusion/ion

More information

Fabrication Techniques of Optical ICs

Fabrication Techniques of Optical ICs Fabrication Techniques of Optical ICs Processing Techniques Lift off Process Etching Process Patterning Techniques Photo Lithography Electron Beam Lithography Photo Resist ( Microposit MP1300) Electron

More information

Pattern Transfer CD-AFM. Resist Features on Poly. Poly Features on Oxide. Quate Group, Stanford University

Pattern Transfer CD-AFM. Resist Features on Poly. Poly Features on Oxide. Quate Group, Stanford University Resist Features on Poly Pattern Transfer Poly Features on Oxide CD-AFM The Critical Dimension AFM Boot -Shaped Tip Tip shape is optimized to sense topography on vertical surfaces Two-dimensional feedback

More information

CMP for More Than Moore

CMP for More Than Moore 2009 Levitronix Conference on CMP Gerfried Zwicker Fraunhofer Institute for Silicon Technology ISIT Itzehoe, Germany gerfried.zwicker@isit.fraunhofer.de Contents Moore s Law and More Than Moore Comparison:

More information

Sensors and Metrology - 2 Optical Microscopy and Overlay Measurements

Sensors and Metrology - 2 Optical Microscopy and Overlay Measurements Sensors and Metrology - 2 Optical Microscopy and Overlay Measurements 1 Optical Metrology Optical Microscopy What is its place in IC production? What are the limitations and the hopes? The issue of Alignment

More information

Application-Based Opportunities for Reused Fab Lines

Application-Based Opportunities for Reused Fab Lines Application-Based Opportunities for Reused Fab Lines Semicon China, March 17 th 2010 Keith Best Simax Lithography S I M A X A L L I A N C E P A R T N E R S Outline Market: Exciting More than Moore applications

More information

A Laser-Based Thin-Film Growth Monitor

A Laser-Based Thin-Film Growth Monitor TECHNOLOGY by Charles Taylor, Darryl Barlett, Eric Chason, and Jerry Floro A Laser-Based Thin-Film Growth Monitor The Multi-beam Optical Sensor (MOS) was developed jointly by k-space Associates (Ann Arbor,

More information

Chapter 3 Fabrication

Chapter 3 Fabrication Chapter 3 Fabrication The total structure of MO pick-up contains four parts: 1. A sub-micro aperture underneath the SIL The sub-micro aperture is used to limit the final spot size from 300nm to 600nm for

More information

Major Fabrication Steps in MOS Process Flow

Major Fabrication Steps in MOS Process Flow Major Fabrication Steps in MOS Process Flow UV light Mask oxygen Silicon dioxide photoresist exposed photoresist oxide Silicon substrate Oxidation (Field oxide) Photoresist Coating Mask-Wafer Alignment

More information

450mm patterning out of darkness Backend Process Exposure Tool SOKUDO Lithography Breakfast Forum July 10, 2013 Doug Shelton Canon USA Inc.

450mm patterning out of darkness Backend Process Exposure Tool SOKUDO Lithography Breakfast Forum July 10, 2013 Doug Shelton Canon USA Inc. 450mm patterning out of darkness Backend Process Exposure Tool SOKUDO Lithography Breakfast Forum 2013 July 10, 2013 Doug Shelton Canon USA Inc. Introduction Half Pitch [nm] 2013 2014 2015 2016 2017 2018

More information

64 Channel Flip-Chip Mounted Selectively Oxidized GaAs VCSEL Array

64 Channel Flip-Chip Mounted Selectively Oxidized GaAs VCSEL Array 64 Channel Flip-Chip Mounted Selectively Oxidized GaAs VCSEL Array 69 64 Channel Flip-Chip Mounted Selectively Oxidized GaAs VCSEL Array Roland Jäger and Christian Jung We have designed and fabricated

More information

Enabling Areal Density Growth

Enabling Areal Density Growth Shrinking the Magnetic Spacing for Advanced PMR Heads Diskcon Asia 2007 Enabling Areal Density Growth Shrinking the magnetic spacing remains one of the biggest levers for areal density growth! Areal Density

More information

Real time plasma etch control by means of physical plasma parameters with HERCULES

Real time plasma etch control by means of physical plasma parameters with HERCULES Real time plasma etch control by means of physical plasma parameters with HERCULES A. Steinbach 1) S. Bernhard 1) M. Sussiek 4) S. Wurm 2) Ch. Koelbl 3) D. Knobloch 1) Siemens, Dresden Siemens at International

More information

Lecture 0: Introduction

Lecture 0: Introduction Lecture 0: Introduction Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): bucketloads! Complementary Metal Oxide Semiconductor Fast, cheap, low power

More information

Lecture: Integration of silicon photonics with electronics. Prepared by Jean-Marc FEDELI CEA-LETI

Lecture: Integration of silicon photonics with electronics. Prepared by Jean-Marc FEDELI CEA-LETI Lecture: Integration of silicon photonics with electronics Prepared by Jean-Marc FEDELI CEA-LETI Context The goal is to give optical functionalities to electronics integrated circuit (EIC) The objectives

More information

Etching Small Samples and the Effects of Using a Carrier Wafer STS ICP-RIE

Etching Small Samples and the Effects of Using a Carrier Wafer STS ICP-RIE Etching Small Samples and the Effects of Using a Carrier Wafer STS ICP-RIE This note is a brief description of the effects of bonding pieces to a carrier wafer during the etch process on the STS ICP-RIE.

More information

MeRck. AZ nlof technical datasheet. Negative Tone Photoresist for Single Layer Lift-Off APPLICATION TYPICAL PROCESS. SPIN CURVE (150MM Silicon)

MeRck. AZ nlof technical datasheet. Negative Tone Photoresist for Single Layer Lift-Off APPLICATION TYPICAL PROCESS. SPIN CURVE (150MM Silicon) MeRck technical datasheet AZ nlof 5510 Negative Tone Photoresist for Single Layer Lift-Off APPLICATION AZ nlof 5510 i-line photoresist is engineered to simplify the historically complex image reversal

More information

MEMS in ECE at CMU. Gary K. Fedder

MEMS in ECE at CMU. Gary K. Fedder MEMS in ECE at CMU Gary K. Fedder Department of Electrical and Computer Engineering and The Robotics Institute Carnegie Mellon University Pittsburgh, PA 15213-3890 fedder@ece.cmu.edu http://www.ece.cmu.edu/~mems

More information

ISMI Industry Productivity Driver

ISMI Industry Productivity Driver SEMATECH Symposium Japan September 15, 2010 Accelerating Manufacturing Productivity ISMI Industry Productivity Driver Scott Kramer VP Manufacturing Technology SEMATECH Copyright 2010 SEMATECH, Inc. SEMATECH,

More information

MeRck. nlof 2000 Series. technical datasheet. Negative Tone Photoresists for Single Layer Lift-Off APPLICATION TYPICAL PROCESS

MeRck. nlof 2000 Series. technical datasheet. Negative Tone Photoresists for Single Layer Lift-Off APPLICATION TYPICAL PROCESS MeRck technical datasheet AZ Negative Tone Photoresists for Single Layer Lift-Off APPLICATION AZ i-line photoresists are engineered to simplify the historically complex image reversal and multilayer lift-off

More information

Innovation to Advance Moore s Law Requires Core Technology Revolution

Innovation to Advance Moore s Law Requires Core Technology Revolution Innovation to Advance Moore s Law Requires Core Technology Revolution Klaus Schuegraf, Ph.D. Chief Technology Officer Silicon Systems Group Applied Materials UC Berkeley Seminar March 9 th, 2012 Innovation

More information

1.6 Beam Wander vs. Image Jitter

1.6 Beam Wander vs. Image Jitter 8 Chapter 1 1.6 Beam Wander vs. Image Jitter It is common at this point to look at beam wander and image jitter and ask what differentiates them. Consider a cooperative optical communication system that

More information

i- Line Photoresist Development: Replacement Evaluation of OiR

i- Line Photoresist Development: Replacement Evaluation of OiR i- Line Photoresist Development: Replacement Evaluation of OiR 906-12 Nishtha Bhatia High School Intern 31 July 2014 The Marvell Nanofabrication Laboratory s current i-line photoresist, OiR 897-10i, has

More information

Application Note AN-1011

Application Note AN-1011 AN-1011 Board Mounting Application Note for 0.800mm Pitch Devices For part numbers IRF6100, IRF6100PBF, IR130CSP, IR130CSPPBF, IR140CSP, IR140CSPPBF, IR1H40CSP, IR1H40CSPPBF By Hazel Schofield and Philip

More information

UV LED ILLUMINATION STEPPER OFFERS HIGH PERFORMANCE AND LOW COST OF OWNERSHIP

UV LED ILLUMINATION STEPPER OFFERS HIGH PERFORMANCE AND LOW COST OF OWNERSHIP UV LED ILLUMINATION STEPPER OFFERS HIGH PERFORMANCE AND LOW COST OF OWNERSHIP Casey Donaher, Rudolph Technologies Herbert J. Thompson, Rudolph Technologies Chin Tiong Sim, Rudolph Technologies Rudolph

More information

Setting up and Using Digital Micrometer Controlled Lapping Fixtures

Setting up and Using Digital Micrometer Controlled Lapping Fixtures Setting up and Using Digital Micrometer Controlled Lapping Fixtures Purpose polishing fixtures are commonly used in materials preparation labs around the world. Lapping fixtures provide stability, precision,

More information

420 Intro to VLSI Design

420 Intro to VLSI Design Dept of Electrical and Computer Engineering 420 Intro to VLSI Design Lecture 0: Course Introduction and Overview Valencia M. Joyner Spring 2005 Getting Started Syllabus About the Instructor Labs, Problem

More information

MICRO AND NANOPROCESSING TECHNOLOGIES

MICRO AND NANOPROCESSING TECHNOLOGIES MICRO AND NANOPROCESSING TECHNOLOGIES LECTURE 4 Optical lithography Concepts and processes Lithography systems Fundamental limitations and other issues Photoresists Photolithography process Process parameter

More information

UVISEL. Spectroscopic Phase Modulated Ellipsometer. The Ideal Tool for Thin Film and Material Characterization

UVISEL. Spectroscopic Phase Modulated Ellipsometer. The Ideal Tool for Thin Film and Material Characterization UVISEL Spectroscopic Phase Modulated Ellipsometer The Ideal Tool for Thin Film and Material Characterization High Precision Research Spectroscopic Ellipsometer The UVISEL ellipsometer offers the best combination

More information

Design Rules for Silicon Photonics Prototyping

Design Rules for Silicon Photonics Prototyping Design Rules for licon Photonics Prototyping Version 1 (released February 2008) Introduction IME s Photonics Prototyping Service offers 248nm lithography based fabrication technology for passive licon-on-insulator

More information

Image sensor combining the best of different worlds

Image sensor combining the best of different worlds Image sensors and vision systems Image sensor combining the best of different worlds First multispectral time-delay-and-integration (TDI) image sensor based on CCD-in-CMOS technology. Introduction Jonathan

More information

HOTBAR REFLOW SOLDERING

HOTBAR REFLOW SOLDERING HOTBAR REFLOW SOLDERING Content 1. Hotbar Reflow Soldering Introduction 2. Application Types 3. Process Descriptions > Flex to PCB > Wire to PCB 4. Design Guidelines 5. Equipment 6. Troubleshooting Guide

More information

MICROBUMP LITHOGRAPHY FOR 3D STACKING APPLICATIONS

MICROBUMP LITHOGRAPHY FOR 3D STACKING APPLICATIONS MICROBUMP LITHOGRAPHY FOR 3D STACKING APPLICATIONS Patrick Jaenen, John Slabbekoorn, Andy Miller IMEC Kapeldreef 75 B-3001 Leuven, Belgium millera@imec.be Warren W. Flack, Manish Ranjan, Gareth Kenyon,

More information

Soft Electronics Enabled Ergonomic Human-Computer Interaction for Swallowing Training

Soft Electronics Enabled Ergonomic Human-Computer Interaction for Swallowing Training Supplementary Information Soft Electronics Enabled Ergonomic Human-Computer Interaction for Swallowing Training Yongkuk Lee 1,+, Benjamin Nicholls 2,+, Dong Sup Lee 1, Yanfei Chen 3, Youngjae Chun 3,4,

More information

EE C245 ME C218 Introduction to MEMS Design

EE C245 ME C218 Introduction to MEMS Design EE C45 ME C18 Introduction to MEMS Design Fall 008 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 9470 Lecture 7: Noise &

More information

Novel laser power sensor improves process control

Novel laser power sensor improves process control Novel laser power sensor improves process control A dramatic technological advancement from Coherent has yielded a completely new type of fast response power detector. The high response speed is particularly

More information

EUV Light Source The Path to HVM Scalability in Practice

EUV Light Source The Path to HVM Scalability in Practice EUV Light Source The Path to HVM Scalability in Practice Harald Verbraak et al. (all people at XTREME) 2011 International Workshop on EUV and Soft X-ray Sources Nov. 2011 Today s Talk o LDP Technology

More information

EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng

EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng EE4800 CMOS Digital IC Design & Analysis Lecture 1 Introduction Zhuo Feng 1.1 Prof. Zhuo Feng Office: EERC 730 Phone: 487-3116 Email: zhuofeng@mtu.edu Class Website http://www.ece.mtu.edu/~zhuofeng/ee4800fall2010.html

More information

MEMS for RF, Micro Optics and Scanning Probe Nanotechnology Applications

MEMS for RF, Micro Optics and Scanning Probe Nanotechnology Applications MEMS for RF, Micro Optics and Scanning Probe Nanotechnology Applications Part I: RF Applications Introductions and Motivations What are RF MEMS? Example Devices RFIC RFIC consists of Active components

More information

Module 11: Photolithography. Lecture11: Photolithography - I

Module 11: Photolithography. Lecture11: Photolithography - I Module 11: Photolithography Lecture11: Photolithography - I 1 11.0 Photolithography Fundamentals We will all agree that incredible progress is happening in the filed of electronics and computers. For example,

More information

Results of Proof-of-Concept 50keV electron multi-beam Mask Exposure Tool (emet POC)

Results of Proof-of-Concept 50keV electron multi-beam Mask Exposure Tool (emet POC) Results of Proof-of-Concept 50keV electron multi-beam Mask Exposure Tool (emet POC) Elmar Platzgummer *, Christof Klein, and Hans Loeschner IMS Nanofabrication AG Schreygasse 3, A-1020 Vienna, Austria

More information

Photoresist erosion studied in an inductively coupled plasma reactor employing CHF 3

Photoresist erosion studied in an inductively coupled plasma reactor employing CHF 3 Photoresist erosion studied in an inductively coupled plasma reactor employing CHF 3 M. F. Doemling, N. R. Rueger, and G. S. Oehrlein a) Department of Physics, University at Albany, State University of

More information

Advanced Plasma Technology. High precision film thickness trimming for the TFH industry. Roth & Rau AG September 2009

Advanced Plasma Technology. High precision film thickness trimming for the TFH industry. Roth & Rau AG September 2009 Advanced Plasma Technology High precision film thickness trimming for the TFH industry Roth & Rau AG September 2009 Product Overview IonScan Equipment for ultra-precise Surface Processing IonScan 800 Wafer

More information

Synthesis of Silicon. applications. Nanowires Team. Régis Rogel (Ass.Pr), Anne-Claire Salaün (Ass. Pr)

Synthesis of Silicon. applications. Nanowires Team. Régis Rogel (Ass.Pr), Anne-Claire Salaün (Ass. Pr) Synthesis of Silicon nanowires for sensor applications Anne-Claire Salaün Nanowires Team Laurent Pichon (Pr), Régis Rogel (Ass.Pr), Anne-Claire Salaün (Ass. Pr) Ph-D positions: Fouad Demami, Liang Ni,

More information

Measurement of Microscopic Three-dimensional Profiles with High Accuracy and Simple Operation

Measurement of Microscopic Three-dimensional Profiles with High Accuracy and Simple Operation 238 Hitachi Review Vol. 65 (2016), No. 7 Featured Articles Measurement of Microscopic Three-dimensional Profiles with High Accuracy and Simple Operation AFM5500M Scanning Probe Microscope Satoshi Hasumura

More information

State-of-The-Art Dielectric Etch Technology

State-of-The-Art Dielectric Etch Technology State-of-The-Art Dielectric Etch Technology Koichi Yatsuda Product Marketing Manager Etch System Business Unit November 5 th, 2010 TM Outline Dielectric Etch Challenges for State-of-The-Art Devices Control

More information

EG2605 Undergraduate Research Opportunities Program. Large Scale Nano Fabrication via Proton Lithography Using Metallic Stencils

EG2605 Undergraduate Research Opportunities Program. Large Scale Nano Fabrication via Proton Lithography Using Metallic Stencils EG2605 Undergraduate Research Opportunities Program Large Scale Nano Fabrication via Proton Lithography Using Metallic Stencils Tan Chuan Fu 1, Jeroen Anton van Kan 2, Pattabiraman Santhana Raman 2, Yao

More information

1. Exceeding these limits may cause permanent damage.

1. Exceeding these limits may cause permanent damage. Silicon PIN Diode s Features Switch & Attenuator Die Extensive Selection of I-Region Lengths Hermetic Glass Passivated CERMACHIP Oxide Passivated Planar s Voltage Ratings to 3000V Faster Switching Speed

More information

State-of-the-art device fabrication techniques

State-of-the-art device fabrication techniques State-of-the-art device fabrication techniques! Standard Photo-lithography and e-beam lithography! Advanced lithography techniques used in semiconductor industry Deposition: Thermal evaporation, e-gun

More information

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices Christopher Batten School of Electrical and Computer Engineering Cornell University http://www.csl.cornell.edu/courses/ece5950 Simple Transistor

More information

Silicon Photonics: A Platform for Integration, Wafer Level Assembly and Packaging

Silicon Photonics: A Platform for Integration, Wafer Level Assembly and Packaging Silicon Photonics: A Platform for Integration, Wafer Level Assembly and Packaging M. Asghari Kotura Inc April 27 Contents: Who is Kotura Choice of waveguide technology Challenges and merits of Si photonics

More information

CD-SEM for 65-nm Process Node

CD-SEM for 65-nm Process Node CD-SEM for 65-nm Process Node 140 CD-SEM for 65-nm Process Node Hiroki Kawada Hidetoshi Morokuma Sho Takami Mari Nozoe OVERVIEW: Inspection equipment for 90-nm and subsequent process nodes is required

More information

Processes for Flexible Electronic Systems

Processes for Flexible Electronic Systems Processes for Flexible Electronic Systems Michael Feil Fraunhofer Institut feil@izm-m.fraunhofer.de Outline Introduction Single sheet versus reel-to-reel (R2R) Substrate materials R2R printing processes

More information

Enabling Parallel Testing at Sort for High Power Products

Enabling Parallel Testing at Sort for High Power Products Enabling Parallel Testing at Sort for High Power Products Abdel Abdelrahman Tim Swettlen 2200 Mission College Blvd. M/S SC2-07 Santa Clara, CA 94536 Abdel.Abdelrahman@intel.com Tim.Swettlen@intel.com Agenda

More information

Integrated Circuits: FABRICATION & CHARACTERISTICS - 4. Riju C Issac

Integrated Circuits: FABRICATION & CHARACTERISTICS - 4. Riju C Issac Integrated Circuits: FABRICATION & CHARACTERISTICS - 4 Riju C Issac INTEGRATED RESISTORS Resistor in a monolithic IC is very often obtained by the bulk resistivity of one of the diffused areas. P-type

More information

SAMPLE SLIDES & COURSE OUTLINE. Core Competency In Semiconductor Technology: 2. FABRICATION. Dr. Theodore (Ted) Dellin

SAMPLE SLIDES & COURSE OUTLINE. Core Competency In Semiconductor Technology: 2. FABRICATION. Dr. Theodore (Ted) Dellin & Digging Deeper Devices, Fabrication & Reliability For More Info:.com or email Dellin@ieee.org SAMPLE SLIDES & COURSE OUTLINE In : 2. A Easy, Effective, of How Devices Are.. Recommended for everyone who

More information

Plasma diagnostic in an inductively coupled plasma using chlorine chemistry

Plasma diagnostic in an inductively coupled plasma using chlorine chemistry Plasma diagnostic in an inductively coupled plasma using chlorine chemistry H. Steinmetz, J. Strobl, N. Rohn and T. Werner, Lam Research GmbH M. Klick, W. Rehak, M. Kammeyer, and D. Suchland, Adolf-Slaby-Institute

More information

Wafer-scale 3D integration of silicon-on-insulator RF amplifiers

Wafer-scale 3D integration of silicon-on-insulator RF amplifiers Wafer-scale integration of silicon-on-insulator RF amplifiers The MIT Faculty has made this article openly available. Please share how this access benefits you. Your story matters. Citation As Published

More information

Fault Diagnosis Algorithms Part 2

Fault Diagnosis Algorithms Part 2 Fault Diagnosis Algorithms Part 2 By Christopher Henderson Page 1 Fault Diagnosis Algorithms Part 2 Page 5 Technical Tidbit Page 8 Ask the Experts Figure 4. Circuit schematic. This is an example of a circuit

More information

EMERGING SUBSTRATE TECHNOLOGIES FOR PACKAGING

EMERGING SUBSTRATE TECHNOLOGIES FOR PACKAGING EMERGING SUBSTRATE TECHNOLOGIES FOR PACKAGING Henry H. Utsunomiya Interconnection Technologies, Inc. Suwa City, Nagano Prefecture, Japan henryutsunomiya@mac.com ABSTRACT This presentation will outline

More information

PicoMaster 100. Unprecedented finesse in creating 3D micro structures. UV direct laser writer for maskless lithography

PicoMaster 100. Unprecedented finesse in creating 3D micro structures. UV direct laser writer for maskless lithography UV direct laser writer for maskless lithography Unprecedented finesse in creating 3D micro structures Highest resolution in the market utilizing a 405 nm diode laser Structures as small as 300 nm 375 nm

More information

Chapter 6. Photolithography

Chapter 6. Photolithography Chapter 6 Photolithography 2006/4/10 1 Objectives List the four components of the photoresist Describe the difference between +PR and PR Describe a photolithography process sequence List four alignment

More information

Silicon wafer thickness monitor

Silicon wafer thickness monitor Silicon wafer thickness monitor SIT-200 Alnair Labs Corporation 2016.04.20 Principle of Measurement Silicon wafer Optical fiber Sensor head Wavelength tunable laser PD PD Interference signal Power monitor

More information

Studies on MCM D interconnections

Studies on MCM D interconnections Studies on MCM D interconnections Speaker: Peter Gerlach Department of Physics Bergische Universität Wuppertal D-42097 Wuppertal, GERMANY Authors: K.H.Becks, T.Flick, P.Gerlach, C.Grah, P.Mättig Department

More information

Growing a NASA Sponsored Metrology Project to Serve Many Applications and Industries. James Millerd President, 4D Technology

Growing a NASA Sponsored Metrology Project to Serve Many Applications and Industries. James Millerd President, 4D Technology Growing a NASA Sponsored Metrology Project to Serve Many Applications and Industries James Millerd President, 4D Technology Outline In the Beginning Early Technology The NASA Connection NASA Programs First

More information

A new Hetero-material Stepped Gate (HSG) SOI LDMOS for RF Power Amplifier Applications

A new Hetero-material Stepped Gate (HSG) SOI LDMOS for RF Power Amplifier Applications A new Hetero-material Stepped Gate (HSG) SOI LDMOS for RF Power Amplifier Applications Radhakrishnan Sithanandam and M. Jagadesh Kumar, Senior Member, IEEE Department of Electrical Engineering Indian Institute

More information

Feature-level Compensation & Control

Feature-level Compensation & Control Feature-level Compensation & Control 2 Lithography Andrew Neureuther and Costas Spanos, UCB Workshop & Review 04/15/2004 11/19/2003 - Lithography 3 Lithography: Andy Neureuther, UCB Research Themes: Linking

More information

Technology for the MEMS processing and testing environment. SUSS MicroTec AG Dr. Hans-Georg Kapitza

Technology for the MEMS processing and testing environment. SUSS MicroTec AG Dr. Hans-Georg Kapitza Technology for the MEMS processing and testing environment SUSS MicroTec AG Dr. Hans-Georg Kapitza 1 SUSS MicroTec Industrial Group Founded 1949 as Karl Süss KG GmbH&Co. in Garching/ Munich San Jose Waterbury

More information

Positive-Tone Photosensitive Polyimide Coatings for Lens Layer in image sensors. Introduction of the characteristic of CS-series

Positive-Tone Photosensitive Polyimide Coatings for Lens Layer in image sensors. Introduction of the characteristic of CS-series Positive-Tone Photosensitive Polyimide Coatings for Lens Layer in image sensors Photoneece CS-series Introduction of the characteristic of CS-series Toray Industries, Inc. 1 1 CS-7500 basic properties

More information

Lithography Session. EUV Lithography optics current status and outlook. F. Roozeboom Professor TU Eindhoven & TNO-Holst Centre, Eindhoven, Netherlands

Lithography Session. EUV Lithography optics current status and outlook. F. Roozeboom Professor TU Eindhoven & TNO-Holst Centre, Eindhoven, Netherlands Lithography Session F. Roozeboom Professor TU Eindhoven & TNO-Holst Centre, Eindhoven, Netherlands Fred Roozeboom is a Professor at Eindhoven University of Technology, The Netherlands and Senior Technical

More information