Pattern Transfer CD-AFM. Resist Features on Poly. Poly Features on Oxide. Quate Group, Stanford University

Transcription

1 Resist Features on Poly Pattern Transfer Poly Features on Oxide CD-AFM

2 The Critical Dimension AFM Boot -Shaped Tip Tip shape is optimized to sense topography on vertical surfaces Two-dimensional feedback enables imaging of vertical or reentrant profiles Tip calibration allows accurate measurements of lithographed features

3 Latent Images in Resist Exposed regions of resist are raised after scanning probe lithography Additional swelling occurs during post exposure bake (PEB) and development steps

4 pmosfet Process Flow (a) LOCOS Isolation Field Thickness=4500 Å Vt Implant As, 100 kev, 1x10 13 cm -2 Implant Anneal RTA, 1050 C, 10 s Gate Oxidation Poly Deposition Thickness=57 Å Thickness=1000 Å Poly Implant BF 2, 10 kev, 1x10 15 cm -2 Poly Activation RTA, 1050 C, 10 s Gate Litho Hybrid AFM / STM

5 pmosfet Process Flow (b) Spacer Formation Thickness=350 Å S/D Implant BF 2, 10 kev, 1x10 15 cm -2 LTO Passivation Anneal Thickness=4500 Å RTA, 1050 C, 10 s Furnace, 800 C, 30 min Contact Etch BOE 6:1 Metallization Al / 1% Si

6 pmosfet Gate Lithography (a) 1) LTO gate pad is defined using photolithography 2) SAL-601 resist is spun on the wafer; Hybrid AFM / STM lithography is performed

7 pmosfet Gate Lithography (b) 3) Resist is developed, leaving the exposed gate 4) Poly is etched by RIE; resist is stripped

8 Transistor After Gate Patterning gate poly gate source drain field oxide active area substrate Optical image of full transistor after gate litho CD-AFM image of poly at field/active transition

9 Completed pmosfet source gate drain Fabricated > 50 working pmosfets with L physical from 67 nm to 170 nm 10 µm substrate Device characteristics reported for a FET with: L physical =130 nm L effective =100 nm

10 Device Characteristics Gm=154 ms/mm Vt=-0.41 V Idmax=0.244 ma/µm 0 0 Drain Current (A) Drain Current (A) Drain Voltage (V) Gate Voltage (V)

11 Future Work High speed lithography with a single probe High speed lithography with multiple probes Large area patterning (1 mm x 1 mm)

12 Acknowledgments Dave Kyser, Bill Arnold, Bhanwar Singh, & Roger Alvis at Advanced Micro Devices (AMD) Rainer Schierle at Park Scientific Instruments The technicians at Stanford s Center for Integrated Systems (CIS) Keith Perkins at Naval Research Labs Mark McCord at Stanford University Financial support from DARPA, NSF, AMD

13 Throughput Requirements Lithography Capabilities 50 nm pixels 5 probes/mm 2 20 mm/s scan speed (patterns 1 mm 2 in 200 sec) probes pixel Throughput Goals 20 wafers/hour (200 mm wafers; 8x10 12 pixels/wafer) 10 5 tips required to reach this goal 50 nm 1 mm 1 mm 50 nm CHALLENGES * High Speed Scanning * Massively Parallel Arrays

14 pmosfet Fabrication Gate patterned by scanning probe lithography 100-nm pmosfet gate Etched 100-nm gate over field/active topography source 10 µm substrate drain

15 Device Characteristics Gm=154 ms/mm Vt=-0.41 V Idmax=0.244 ma/µm 0 0 Drain Current (A) Drain Current (A) Drain Voltage (V) Gate Voltage (V)

16 Patterning Resolution Linewidth (nm) Line Dose (nc/cm) Electron dose is the critical parameter for exposure Smallest feature is 41 nm wide, patterned at a dose of 26 nc/cm

17 Independent Current-Controlled Lithography With Two Tips Tip 1 Tip 2 10 µm Patterned linewidth is independently controlled by each tip through individual dose setpoints

18 Hybrid AFM / STM Lithography FORCE FEEDBACK optical lever deflection sensor detector laser maintain constant force z piezo tube signal [v] xyz scanner CURRENT FEEDBACK current amplifier resist sample stage tip cantilever bias [v] maintain constant current