College of Engineering Department of Electrical Engineering and Computer Sciences University of California, Berkeley

Size: px
Start display at page:

Download "College of Engineering Department of Electrical Engineering and Computer Sciences University of California, Berkeley"

Transcription

1 College of Engineering Department of Electrical Engineering and Below are your weekly quizzes. You should print out a copy of the quiz and complete it before your lab section. Bring in the completed quiz to lab the week it is due. Week 3--Active Area Definition Week 4--Gate Oxidation Week 5--Poly deposition--will be given in lab after Microlab tour Week 6--Gate Definition Week 7--Source/drain Week 8--Contact cut Week 9--Metallization Week 10--Metal Definition Week 11--Characterization (I) Week 12 MEMS Characterization Last update 11/9/2001 Usage of this site is subject to the U.C. Computer Usage Policy.

2 Spring Semester, 2000 Week #3 Quiz--Active Area Definition Name Section Date (1) How does spin speed and time affect photoresist application? (2) What is the purpose of the soft bake (before exposure)? (3) What color are the lights in the lithography room, and why? (4) What chemical do we use to define the features in the photoresist? (5) What chemical do we use to define the features in the oxide layer? (6) What chemical do we use to remove the photoresist after we're all done? (7) Will the dark areas on the mask produce islands of oxide or pits in the surrounding oxide? (8) What might happen if we do not leave the wafers in the oxide etchant long enough? (9) Where do we keep the ointment to treat HF burns? (10) What is the purpose of HMDS? A. Franke 8/31/99

3 Spring Semester, 1999 Week #4 Quiz--Gate Oxidation Name Section Date (1) What is the purpose of the furnace tube TCA step? (2) Why do we run an additional "control" wafer during the oxidation? (3) How fast is the wafer boat pushed into and pulled out of the furnace? (4) Why is this push/pull rate important? (5) Are we performing a wet or dry oxidation? Why? (6) Why do we do an anneal step after oxidation? (7) What do we use the NanoSpec for, and how does it work (briefly)? (7) What do we use the Four-Point Probe for, and how does it work (briefly)? M. Freed 1/20/99

4 Fall Semester, 1999 Week #6 Quiz--Gate Definition Name Section Date (1) Assuming perfect alignment, please draw a top view of what the overlapping alignment markers will look like for this week's mask and the ACTIVE mask? (2) Order the following steps for this weeks lab(1 for the first step, through 5 for last step): ( ) Etch the oxide ( ) Expose the photoresist ( ) Strip the photoresist ( ) Develop the photoresist ( ) Etch the polysilicon (3) Which of these is what a normal wet-etched film looks like (e.g. an oxide film after a BHF etch)? (top layer=photoresist middle layer=oxide bulk=silicon) ( ) ( ) ( ) (4) What can be done to help all the 2-micron gates survive the steps we will do in the lab this week? (5) Why do exposure times vary with substrate material?

5 (6) What do we etch the polysilicon with? What is the nominal polysilicon etch rate? Using the nominal etch rate above, assuming 3500Å of poly, and using a 10% overetch, how long should we etch the poly? (7) Why do we do an oxide etch after the polysilicon etch? (8) Show how one of your MOSFETs will look after this week's lab (draw cross section)?

6 Fall Semester, 1999 Week #7 Quiz--Source/Drain Name Section Date (1) What is the purpose of the spin-on glass (SOG)? (2) Why is the timing of the pre-diffusion step important? (3) What is the dopant atom we are depositing in the source/drain regions? (4) Why do we use a wet oxidation for the intermediate oxide? (5) What is the purpose of the N 2 anneal? (6) If the polysilicon was only 100nm thick instead of 350nm what problems might this create? (7) What are the advantages of using ion implantation instead of spin-on-glass to dope the source and drain? What are some of the disadvantages? (8) After the deposition, when we use the four-point probe, are we measuring sheet resistance or bulk resistivity? (9) Draw a cross-sectional view of what the diffused source and drain regions will look like after this week's lab for a simple transistor (MOSFET), including all other layers and the effects of isotropic etching. Is this a self-aligned process? Explain. (2 points)

7 Fall Semester, 1999 Week #8 Quiz--Contact Cut Name Section Date (1) What layer will we be cutting through today? (2) What etchant (and what concentration) will we be using? What is the nominal etch-rate? Assuming 1400 Å of the layer and using a 10% overetch, how long (in minutes and seconds) would you need to etch? (3) What are the potential problems if we overetch or underetch? (4) What is the purpose of the NH 4 F in the BHF (i.e. why is there NH 4 F in BHF instead of H 2 O)? (5) Is today's mask (CONT) a bright-field or dark-field mask? (6) What will you be aligning this week's mask to, the ACTV or POLY alignment markers? If we're off by several microns in alignment, how will this affect the performance of your MOSFETs? (7) If the wet etch is done for twice as long as needed, how will this affect the performance of your MOSFETs? (8) Draw the cross-sectional view, and top down view of a MOSFET before and after today's processing (3 points).

8 Fall Semester, 1999 Week #9 Quiz--Metallization Name Section Date (1) Draw a schematic diagram of the vacuum system, in the detail given in the lab manual. (label all components) (2) Why do we need the "roughing" or mechanical pump? Briefly describe how they work. (3) At what pressure do we switch to the diffusion pump (i.e. at what pressure has "roughing" been completed)? What could happen if we continue to pump using the mechanical pump at this pressure? (4) What does the oil in the diffusion pump do? What is the danger inherent in the diffusion pump oil? What is the purpose of the cooled baffle? (5) What is a cold trap and how does it "pump"? (6) What is the purpose of the HF dip just prior to metallization? (7) Why is low pressure so important for aluminum deposition?

9 (8) Why do we heat the charges at 40 Amps for ~20 seconds before we evaporate them? (9) Will the metal layer be conformal? Why or why not?

10 Fall Semester, 1999 Week #10 Quiz--Metal Definition Name Section Date (1) At what temperature is the aluminum etchant kept? Why can't the aluminum etchant be used at room temperature? (2) Why must the wafer be kept moving during the etch? (3) What is the nominal etch rate of the aluminum etchant? Assuming 8000Å of aluminum and using a 10% overetch, how long should we etch? (4) Why does the lithography step require a lower exposure time this week? (5) Why do we do the sintering step? (6) What will happen if the sintering temperature is too high or too low? (7) What is "spiking" and how can it be prevented? (8) What problems might have occurred if we used gold instead of aluminum for our contacts? (9) Why don't we have to use a slow push/pull for the sinter?

11 Fall Semester, 1999 Week #11 Quiz--Characterization Name Section Date (1) What is Metrics and what is it used for? (2) What is a HP-4145 and what can it measure? (3) How many terminals will be connected to the diodes, capacitors, MOSFETs? What are these terminals for the MOSFET (i.e. the common names)? (4) What will we use to measure C-V? Is this tool available at all probe stations? (5) How many circuits (not devices) are there on your test chip? What are they? (6) How can we sometimes measure a two terminal device with only one probe tip? (hint: these are often vertical devices) (7) Give a brief description of a wafer probe station with schematic diagram.

12 Fall Semester, 2001 Week #12 Quiz MEMS Processing & Characterization Name Section Date (1) Unlike MOSFET fabrication where we removed PR of METL layer to prepare for sintering, we leave the resist to stay on Al layer for MEMS fabrication. Why is this the case? (2) Etch rate of XeF 2 for <100> single-crystal silicon varies from 2400 to 2900 A/min. To release our cantilevers with 100 micron in their width, what is the shortest expected release time? We assume that XeF 2 etch is perfectly isotropic, and is also perfect in selectivity between silicon and silicon dioxide. (3) If your wafer is not dehydrated enough before you bring it into the XeF 2 chamber, what kind of undesired byproduct is possibly created? (Hint: Recall the etch chemistry of XeF 2, especially when it reacts with moisture, i.e., H 2 O.) (4) What would happen if native oxide film was left on the wafers as it went into the XeF 2 etching step? (5) Once the bimorph is released, is the cantilever bent towards upward or downward? (Thermal expansion coefficients of Al and oxide are 6.5 and /C, respectively.) (6) To measure voltage and current characteristics of the oxide-metal bimorph as it undergoes deflection, which equipment(s) do you need to have?

FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag

FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag FABRICATION OF CMOS INTEGRATED CIRCUITS Dr. Mohammed M. Farag Outline Overview of CMOS Fabrication Processes The CMOS Fabrication Process Flow Design Rules Reference: Uyemura, John P. "Introduction to

More information

EE C245 / ME C218 INTRODUCTION TO MEMS DESIGN FALL 2011 PROBLEM SET #2. Due (at 7 p.m.): Tuesday, Sept. 27, 2011, in the EE C245 HW box in 240 Cory.

EE C245 / ME C218 INTRODUCTION TO MEMS DESIGN FALL 2011 PROBLEM SET #2. Due (at 7 p.m.): Tuesday, Sept. 27, 2011, in the EE C245 HW box in 240 Cory. Issued: Tuesday, Sept. 13, 2011 PROBLEM SET #2 Due (at 7 p.m.): Tuesday, Sept. 27, 2011, in the EE C245 HW box in 240 Cory. 1. Below in Figure 1.1 is a description of a DRIE silicon etch using the Marvell

More information

CMOS Digital Integrated Circuits Lec 2 Fabrication of MOSFETs

CMOS Digital Integrated Circuits Lec 2 Fabrication of MOSFETs CMOS Digital Integrated Circuits Lec 2 Fabrication of MOSFETs 1 CMOS Digital Integrated Circuits 3 rd Edition Categories of Materials Materials can be categorized into three main groups regarding their

More information

Major Fabrication Steps in MOS Process Flow

Major Fabrication Steps in MOS Process Flow Major Fabrication Steps in MOS Process Flow UV light Mask oxygen Silicon dioxide photoresist exposed photoresist oxide Silicon substrate Oxidation (Field oxide) Photoresist Coating Mask-Wafer Alignment

More information

EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng

EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng EE4800 CMOS Digital IC Design & Analysis Lecture 1 Introduction Zhuo Feng 1.1 Prof. Zhuo Feng Office: EERC 730 Phone: 487-3116 Email: zhuofeng@mtu.edu Class Website http://www.ece.mtu.edu/~zhuofeng/ee4800fall2010.html

More information

VLSI Design. Introduction

VLSI Design. Introduction Tassadaq Hussain VLSI Design Introduction Outcome of this course Problem Aims Objectives Outcomes Data Collection Theoretical Model Mathematical Model Validate Development Analysis and Observation Pseudo

More information

VLSI Design. Introduction

VLSI Design. Introduction VLSI Design Introduction Outline Introduction Silicon, pn-junctions and transistors A Brief History Operation of MOS Transistors CMOS circuits Fabrication steps for CMOS circuits Introduction Integrated

More information

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices Christopher Batten School of Electrical and Computer Engineering Cornell University http://www.csl.cornell.edu/courses/ece5950 Simple Transistor

More information

420 Intro to VLSI Design

420 Intro to VLSI Design Dept of Electrical and Computer Engineering 420 Intro to VLSI Design Lecture 0: Course Introduction and Overview Valencia M. Joyner Spring 2005 Getting Started Syllabus About the Instructor Labs, Problem

More information

+1 (479)

+1 (479) Introduction to VLSI Design http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Invention of the Transistor Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable

More information

Lecture 0: Introduction

Lecture 0: Introduction Lecture 0: Introduction Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): bucketloads! Complementary Metal Oxide Semiconductor Fast, cheap, low power

More information

Topic 3. CMOS Fabrication Process

Topic 3. CMOS Fabrication Process Topic 3 CMOS Fabrication Process Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk Lecture 3-1 Layout of a Inverter

More information

Layout of a Inverter. Topic 3. CMOS Fabrication Process. The CMOS Process - photolithography (2) The CMOS Process - photolithography (1) v o.

Layout of a Inverter. Topic 3. CMOS Fabrication Process. The CMOS Process - photolithography (2) The CMOS Process - photolithography (1) v o. Layout of a Inverter Topic 3 CMOS Fabrication Process V DD Q p Peter Cheung Department of Electrical & Electronic Engineering Imperial College London v i v o Q n URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk

More information

Photolithography I ( Part 1 )

Photolithography I ( Part 1 ) 1 Photolithography I ( Part 1 ) Chapter 13 : Semiconductor Manufacturing Technology by M. Quirk & J. Serda Bjørn-Ove Fimland, Department of Electronics and Telecommunication, Norwegian University of Science

More information

EE 5611 Introduction to Microelectronic Technologies Fall Thursday, September 04, 2014 Lecture 02

EE 5611 Introduction to Microelectronic Technologies Fall Thursday, September 04, 2014 Lecture 02 EE 5611 Introduction to Microelectronic Technologies Fall 2014 Thursday, September 04, 2014 Lecture 02 1 Lecture Outline Review on semiconductor materials Review on microelectronic devices Example of microelectronic

More information

Photolithography Technology and Application

Photolithography Technology and Application Photolithography Technology and Application Jeff Tsai Director, Graduate Institute of Electro-Optical Engineering Tatung University Art or Science? Lind width = 100 to 5 micron meter!! Resolution = ~ 3

More information

Semiconductor Physics and Devices

Semiconductor Physics and Devices Metal-Semiconductor and Semiconductor Heterojunctions The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is one of two major types of transistors. The MOSFET is used in digital circuit, because

More information

6.777J/2.372J Design and Fabrication of Microelectromechanical Devices Spring Term Massachusetts Institute of Technology

6.777J/2.372J Design and Fabrication of Microelectromechanical Devices Spring Term Massachusetts Institute of Technology 6.777J/2.372J Design and Fabrication of Microelectromechanical Devices Spring Term 2007 Massachusetts Institute of Technology PROBLEM SET 2 (16 pts) Issued: Lecture 4 Due: Lecture 6 Problem 4.14 (4 pts):

More information

Part 5-1: Lithography

Part 5-1: Lithography Part 5-1: Lithography Yao-Joe Yang 1 Pattern Transfer (Patterning) Types of lithography systems: Optical X-ray electron beam writer (non-traditional, no masks) Two-dimensional pattern transfer: limited

More information

Notes. (Subject Code: 7EC5)

Notes. (Subject Code: 7EC5) COMPUCOM INSTITUTE OF TECHNOLOGY & MANAGEMENT, JAIPUR (DEPARTMENT OF ELECTRONICS & COMMUNICATION) Notes VLSI DESIGN NOTES (Subject Code: 7EC5) Prepared By: MANVENDRA SINGH Class: B. Tech. IV Year, VII

More information

EE 330 Lecture 7. Design Rules. IC Fabrication Technology Part 1

EE 330 Lecture 7. Design Rules. IC Fabrication Technology Part 1 EE 330 Lecture 7 Design Rules IC Fabrication Technology Part 1 Review from Last Time Technology Files Provide Information About Process Process Flow (Fabrication Technology) Model Parameters Design Rules

More information

ECSE-6300 IC Fabrication Laboratory Lecture 9 MOSFETs. Lecture Outline

ECSE-6300 IC Fabrication Laboratory Lecture 9 MOSFETs. Lecture Outline ECSE-6300 IC Fabrication Laboratory Lecture 9 MOSFETs Prof. Rensselaer Polytechnic Institute Troy, NY 12180 Office: CII-6229 Tel.: (518) 276-2909 e-mails: luj@rpi.edu http://www.ecse.rpi.edu/courses/s18/ecse

More information

EE 143 Microfabrication Technology Fall 2014

EE 143 Microfabrication Technology Fall 2014 EE 143 Microfabrication Technology Fall 2014 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 EE 143: Microfabrication

More information

Pattern Transfer CD-AFM. Resist Features on Poly. Poly Features on Oxide. Quate Group, Stanford University

Pattern Transfer CD-AFM. Resist Features on Poly. Poly Features on Oxide. Quate Group, Stanford University Resist Features on Poly Pattern Transfer Poly Features on Oxide CD-AFM The Critical Dimension AFM Boot -Shaped Tip Tip shape is optimized to sense topography on vertical surfaces Two-dimensional feedback

More information

Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced.

Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced. Unit 1 Basic MOS Technology Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced. Levels of Integration:- i) SSI:-

More information

isagers. Three aicron gate spacing was

isagers. Three aicron gate spacing was LIJEAR POLY GATE CHARGE COUPLED DEVICE IMAGING ARRAYS Lucien Randazzese Senior Microelectronic Engineering Student Rochester Institute of Technology ABSTRACT A five cask level process was used to fabricate

More information

Chapter 3 Basics Semiconductor Devices and Processing

Chapter 3 Basics Semiconductor Devices and Processing Chapter 3 Basics Semiconductor Devices and Processing 1 Objectives Identify at least two semiconductor materials from the periodic table of elements List n-type and p-type dopants Describe a diode and

More information

TECHNO INDIA BATANAGAR (DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING) QUESTION BANK- 2018

TECHNO INDIA BATANAGAR (DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING) QUESTION BANK- 2018 TECHNO INDIA BATANAGAR (DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING) QUESTION BANK- 2018 Paper Setter Detail Name Designation Mobile No. E-mail ID Raina Modak Assistant Professor 6290025725 raina.modak@tib.edu.in

More information

Chapter 3: Basics Semiconductor Devices and Processing 2006/9/27 1. Topics

Chapter 3: Basics Semiconductor Devices and Processing 2006/9/27 1. Topics Chapter 3: Basics Semiconductor Devices and Processing 2006/9/27 1 Topics What is semiconductor Basic semiconductor devices Basics of IC processing CMOS technologies 2006/9/27 2 1 What is Semiconductor

More information

ECSE-6300 IC Fabrication Laboratory Lecture 7 MOSFETs. Lecture Outline

ECSE-6300 IC Fabrication Laboratory Lecture 7 MOSFETs. Lecture Outline ECSE-6300 IC Fabrication Laboratory Lecture 7 MOSFETs Prof. Rensselaer Polytechnic Institute Troy, NY 12180 Office: CII-6229 Tel.: (518) 276-2909 e-mails: luj@rpi.edu http://www.ecse.rpi.edu/courses/s16/ecse

More information

INTRODUCTION TO MOS TECHNOLOGY

INTRODUCTION TO MOS TECHNOLOGY INTRODUCTION TO MOS TECHNOLOGY 1. The MOS transistor The most basic element in the design of a large scale integrated circuit is the transistor. For the processes we will discuss, the type of transistor

More information

The Design and Realization of Basic nmos Digital Devices

The Design and Realization of Basic nmos Digital Devices Proceedings of The National Conference On Undergraduate Research (NCUR) 2004 Indiana University Purdue University Indianapolis, Indiana April 15-17, 2004 The Design and Realization of Basic nmos Digital

More information

2.8 - CMOS TECHNOLOGY

2.8 - CMOS TECHNOLOGY CMOS Technology (6/7/00) Page 1 2.8 - CMOS TECHNOLOGY INTRODUCTION Objective The objective of this presentation is: 1.) Illustrate the fabrication sequence for a typical MOS transistor 2.) Show the physical

More information

Semiconductor Manufacturing Technology. Semiconductor Manufacturing Technology. Photolithography: Resist Development and Advanced Lithography

Semiconductor Manufacturing Technology. Semiconductor Manufacturing Technology. Photolithography: Resist Development and Advanced Lithography Semiconductor Manufacturing Technology Michael Quirk & Julian Serda October 2001 by Prentice Hall Chapter 15 Photolithography: Resist Development and Advanced Lithography Eight Basic Steps of Photolithography

More information

In this lecture we will begin a new topic namely the Metal-Oxide-Semiconductor Field Effect Transistor.

In this lecture we will begin a new topic namely the Metal-Oxide-Semiconductor Field Effect Transistor. Solid State Devices Dr. S. Karmalkar Department of Electronics and Communication Engineering Indian Institute of Technology, Madras Lecture - 38 MOS Field Effect Transistor In this lecture we will begin

More information

High-Speed Scalable Silicon-MoS 2 P-N Heterojunction Photodetectors

High-Speed Scalable Silicon-MoS 2 P-N Heterojunction Photodetectors High-Speed Scalable Silicon-MoS 2 P-N Heterojunction Photodetectors Veerendra Dhyani 1, and Samaresh Das 1* 1 Centre for Applied Research in Electronics, Indian Institute of Technology Delhi, New Delhi-110016,

More information

MEMS for RF, Micro Optics and Scanning Probe Nanotechnology Applications

MEMS for RF, Micro Optics and Scanning Probe Nanotechnology Applications MEMS for RF, Micro Optics and Scanning Probe Nanotechnology Applications Part I: RF Applications Introductions and Motivations What are RF MEMS? Example Devices RFIC RFIC consists of Active components

More information

Basic Fabrication Steps

Basic Fabrication Steps Basic Fabrication Steps and Layout Somayyeh Koohi Department of Computer Engineering Adapted with modifications from lecture notes prepared by author Outline Fabrication steps Transistor structures Transistor

More information

EECS 151/251A Spring 2019 Digital Design and Integrated Circuits. Instructors: Wawrzynek. Lecture 8 EE141

EECS 151/251A Spring 2019 Digital Design and Integrated Circuits. Instructors: Wawrzynek. Lecture 8 EE141 EECS 151/251A Spring 2019 Digital Design and Integrated Circuits Instructors: Wawrzynek Lecture 8 EE141 From the Bottom Up IC processing CMOS Circuits (next lecture) EE141 2 Overview of Physical Implementations

More information

Power MOSFET Zheng Yang (ERF 3017,

Power MOSFET Zheng Yang (ERF 3017, ECE442 Power Semiconductor Devices and Integrated Circuits Power MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) Evolution of low-voltage (

More information

Lecture 7. Lithography and Pattern Transfer. Reading: Chapter 7

Lecture 7. Lithography and Pattern Transfer. Reading: Chapter 7 Lecture 7 Lithography and Pattern Transfer Reading: Chapter 7 Used for Pattern transfer into oxides, metals, semiconductors. 3 types of Photoresists (PR): Lithography and Photoresists 1.) Positive: PR

More information

KMPR 1010 Process for Glass Wafers

KMPR 1010 Process for Glass Wafers KMPR 1010 Process for Glass Wafers KMPR 1010 Steps Protocol Step System Condition Note Plasma Cleaning PVA Tepla Ion 10 5 mins Run OmniCoat Receipt Dehydration Any Heat Plate 150 C, 5 mins HMDS Coating

More information

PHGN/CHEN/MLGN 435/535: Interdisciplinary Silicon Processing Laboratory. Simple Si solar Cell!

PHGN/CHEN/MLGN 435/535: Interdisciplinary Silicon Processing Laboratory. Simple Si solar Cell! Where were we? Simple Si solar Cell! Two Levels of Masks - photoresist, alignment Etch and oxidation to isolate thermal oxide, deposited oxide, wet etching, dry etching, isolation schemes Doping - diffusion/ion

More information

SAMPLE SLIDES & COURSE OUTLINE. Core Competency In Semiconductor Technology: 2. FABRICATION. Dr. Theodore (Ted) Dellin

SAMPLE SLIDES & COURSE OUTLINE. Core Competency In Semiconductor Technology: 2. FABRICATION. Dr. Theodore (Ted) Dellin & Digging Deeper Devices, Fabrication & Reliability For More Info:.com or email Dellin@ieee.org SAMPLE SLIDES & COURSE OUTLINE In : 2. A Easy, Effective, of How Devices Are.. Recommended for everyone who

More information

Nanofluidic Diodes based on Nanotube Heterojunctions

Nanofluidic Diodes based on Nanotube Heterojunctions Supporting Information Nanofluidic Diodes based on Nanotube Heterojunctions Ruoxue Yan, Wenjie Liang, Rong Fan, Peidong Yang 1 Department of Chemistry, University of California, Berkeley, CA 94720, USA

More information

EECS130 Integrated Circuit Devices

EECS130 Integrated Circuit Devices EECS130 Integrated Circuit Devices Professor Ali Javey 11/6/2007 MOSFETs Lecture 6 BJTs- Lecture 1 Reading Assignment: Chapter 10 More Scalable Device Structures Vertical Scaling is important. For example,

More information

EE 410: Integrated Circuit Fabrication Laboratory

EE 410: Integrated Circuit Fabrication Laboratory EE 410: Integrated Circuit Fabrication Laboratory 1 EE 410: Integrated Circuit Fabrication Laboratory Web Site: Instructor: http://www.stanford.edu/class/ee410 https://ccnet.stanford.edu/ee410/ (on CCNET)

More information

Micro-fabrication of Hemispherical Poly-Silicon Shells Standing on Hemispherical Cavities

Micro-fabrication of Hemispherical Poly-Silicon Shells Standing on Hemispherical Cavities Micro-fabrication of Hemispherical Poly-Silicon Shells Standing on Hemispherical Cavities Cheng-Hsuan Lin a, Yi-Chung Lo b, Wensyang Hsu *a a Department of Mechanical Engineering, National Chiao-Tung University,

More information

This writeup is adapted from Fall 2002, final project report for by Robert Winsor.

This writeup is adapted from Fall 2002, final project report for by Robert Winsor. Optical Waveguides in Andreas G. Andreou This writeup is adapted from Fall 2002, final project report for 520.773 by Robert Winsor. September, 2003 ABSTRACT This lab course is intended to give students

More information

CS/ECE 5710/6710. Composite Layout

CS/ECE 5710/6710. Composite Layout CS/ECE 5710/6710 Introduction to Layout Inverter Layout Example Layout Design Rules Composite Layout Drawing the mask layers that will be used by the fabrication folks to make the devices Very different

More information

ECE4902 B2015 HW Set 1

ECE4902 B2015 HW Set 1 ECE4902 B2015 HW Set 1 Due in class Tuesday November 3. To make life easier on the graders: Be sure your NAME and ECE MAILBOX NUMBER are prominently displayed on the upper right of what you hand in. When

More information

APPLICATION TRAINING GUIDE

APPLICATION TRAINING GUIDE APPLICATION TRAINING GUIDE Basic Semiconductor Theory Semiconductor is an appropriate name for the device because it perfectly describes the material from which it's made -- not quite a conductor, and

More information

CMOS Technology. 1. Why CMOS 2. Qualitative MOSFET model 3. Building a MOSFET 4. CMOS logic gates. Handouts: Lecture Slides. metal ndiff.

CMOS Technology. 1. Why CMOS 2. Qualitative MOSFET model 3. Building a MOSFET 4. CMOS logic gates. Handouts: Lecture Slides. metal ndiff. CMOS Technology 1. Why CMOS 2. Qualitative MOSFET model 3. Building a MOSFET 4. CMOS logic gates poly pdiff metal ndiff Handouts: Lecture Slides L03 - CMOS Technology 1 Building Bits from Atoms V in V

More information

William Reiniach 5th Year Microelectronic Engineering Student Rochester Institute of Technology

William Reiniach 5th Year Microelectronic Engineering Student Rochester Institute of Technology DEVELOPMENT OF A PHOTOSENSITIVE POLYIMIDE PROCESS William Reiniach 5th Year Microelectronic Engineering Student Rochester Institute of Technology 1~BS TRACT A six step lithographic process has been developed

More information

Integrated diodes. The forward voltage drop only slightly depends on the forward current. ELEKTRONIKOS ĮTAISAI

Integrated diodes. The forward voltage drop only slightly depends on the forward current. ELEKTRONIKOS ĮTAISAI 1 Integrated diodes pn junctions of transistor structures can be used as integrated diodes. The choice of the junction is limited by the considerations of switching speed and breakdown voltage. The forward

More information

MEMS in ECE at CMU. Gary K. Fedder

MEMS in ECE at CMU. Gary K. Fedder MEMS in ECE at CMU Gary K. Fedder Department of Electrical and Computer Engineering and The Robotics Institute Carnegie Mellon University Pittsburgh, PA 15213-3890 fedder@ece.cmu.edu http://www.ece.cmu.edu/~mems

More information

Lecture 020 ECE4430 Review II (1/5/04) Page 020-1

Lecture 020 ECE4430 Review II (1/5/04) Page 020-1 Lecture 020 ECE4430 Review II (1/5/04) Page 020-1 LECTURE 020 ECE 4430 REVIEW II (READING: GHLM - Chap. 2) Objective The objective of this presentation is: 1.) Identify the prerequisite material as taught

More information

Lecture 020 ECE4430 Review II (1/5/04) Page 020-1

Lecture 020 ECE4430 Review II (1/5/04) Page 020-1 Lecture 020 ECE4430 Review II (1/5/04) Page 020-1 LECTURE 020 ECE 4430 REVIEW II (READING: GHLM - Chap. 2) Objective The objective of this presentation is: 1.) Identify the prerequisite material as taught

More information

Dr. Dirk Meyners Prof. Wagner. Wagner / Meyners Micro / Nanosystems Technology

Dr. Dirk Meyners Prof. Wagner. Wagner / Meyners Micro / Nanosystems Technology Micro/Nanosystems Technology Dr. Dirk Meyners Prof. Wagner 1 Outline - Lithography Overview - UV-Lithography - Resolution Enhancement Techniques - Electron Beam Lithography - Patterning with Focused Ion

More information

INTRODUCTION: Basic operating principle of a MOSFET:

INTRODUCTION: Basic operating principle of a MOSFET: INTRODUCTION: Along with the Junction Field Effect Transistor (JFET), there is another type of Field Effect Transistor available whose Gate input is electrically insulated from the main current carrying

More information

(ksaligner & quintel resolution)

(ksaligner & quintel resolution) Process [4.10] (ksaligner & quintel resolution) 1.0 Process Summary 1.1 Since Karl Suss ksaligner is heavily used and Quintel aligner is not, nanolab decided to compare the 2 micron line resolution from

More information

University of California at Berkeley College of Engineering Dept. of Electrical Engineering and Computer Sciences. EECS 40 Midterm II

University of California at Berkeley College of Engineering Dept. of Electrical Engineering and Computer Sciences. EECS 40 Midterm II University of California at Berkeley College of Engineering Dept. of Electrical Engineering and Computer Sciences EECS 40 Midterm II Fall 1998 Prof. Roger T. Howe November 19, 1998 Name: Student ID: Guidelines

More information

EXPERIMENT # 3: Oxidation and Etching Tuesday 2/3/98 and 2/5/98 Thursday 2/10/98 and 2/12/98

EXPERIMENT # 3: Oxidation and Etching Tuesday 2/3/98 and 2/5/98 Thursday 2/10/98 and 2/12/98 EXPERIMENT # 3: Oxidation and Etching Tuesday 2/3/98 and 2/5/98 Thursday 2/10/98 and 2/12/98 Experiment # 3: Oxidation of silicon - Oxide etching and Resist stripping Measurement of oxide thickness using

More information

DESIGN AND FABRICATION OF A LATERAL BIPOLAR PNP TRANSISTOR COMPATIBLE WITH RIT S DOUBLE DIFFUSED PROCESS

DESIGN AND FABRICATION OF A LATERAL BIPOLAR PNP TRANSISTOR COMPATIBLE WITH RIT S DOUBLE DIFFUSED PROCESS DESIGN AND FABRICATION OF A LATERAL BIPOLAR PNP TRANSISTOR COMPATIBLE WITH RIT S DOUBLE DIFFUSED PROCESS James A. Will II Senior Microelectronic Engineering Student Rochester Institute of Technology ABSTRACT

More information

High-Ohmic Resistors using Nanometer-Thin Pure-Boron Chemical-Vapour-Deposited Layers

High-Ohmic Resistors using Nanometer-Thin Pure-Boron Chemical-Vapour-Deposited Layers High-Ohmic Resistors using Nanometer-Thin Pure-Boron Chemical-Vapour-Deposited Layers Negin Golshani, Vahid Mohammadi, Siva Ramesh, Lis K. Nanver Delft University of Technology The Netherlands ESSDERC

More information

Fabrication and Characterization of Pseudo-MOSFETs

Fabrication and Characterization of Pseudo-MOSFETs Fabrication and Characterization of Pseudo-MOSFETs Joachim Knoch February 8, 2010 Contents 1 Introduction 2 2 The pseudo-mosfet 3 3 Device Fabrication 5 4 Electrical Measurement and Characterization 8

More information

AC : EXPERIMENTAL MODULES INTRODUCING MICRO- FABRICATION UTILIZING A MULTIDISCIPLINARY APPROACH

AC : EXPERIMENTAL MODULES INTRODUCING MICRO- FABRICATION UTILIZING A MULTIDISCIPLINARY APPROACH AC 2011-1595: EXPERIMENTAL MODULES INTRODUCING MICRO- FABRICATION UTILIZING A MULTIDISCIPLINARY APPROACH Shawn Wagoner, Binghamton University Director, Nanofabrication Labatory at Binghamton University,

More information

MICROPROCESSOR TECHNOLOGY

MICROPROCESSOR TECHNOLOGY MICROPROCESSOR TECHNOLOGY Assis. Prof. Hossam El-Din Moustafa Lecture 3 Ch.1 The Evolution of The Microprocessor 17-Feb-15 1 Chapter Objectives Introduce the microprocessor evolution from transistors to

More information

Color Plates SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 7

Color Plates SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 7 Color Plates SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 7 FIGURE CP.1 Layout and cross section of an N-Well CMOS process using 2D models in SIMPL-2 [rzz.lee.phd]. FIGURE CP.2 Magnified

More information

problem grade total

problem grade total Fall 2005 6.012 Microelectronic Devices and Circuits Prof. J. A. del Alamo Name: Recitation: November 16, 2005 Quiz #2 problem grade 1 2 3 4 total General guidelines (please read carefully before starting):

More information

Synthesis of Silicon. applications. Nanowires Team. Régis Rogel (Ass.Pr), Anne-Claire Salaün (Ass. Pr)

Synthesis of Silicon. applications. Nanowires Team. Régis Rogel (Ass.Pr), Anne-Claire Salaün (Ass. Pr) Synthesis of Silicon nanowires for sensor applications Anne-Claire Salaün Nanowires Team Laurent Pichon (Pr), Régis Rogel (Ass.Pr), Anne-Claire Salaün (Ass. Pr) Ph-D positions: Fouad Demami, Liang Ni,

More information

i- Line Photoresist Development: Replacement Evaluation of OiR

i- Line Photoresist Development: Replacement Evaluation of OiR i- Line Photoresist Development: Replacement Evaluation of OiR 906-12 Nishtha Bhatia High School Intern 31 July 2014 The Marvell Nanofabrication Laboratory s current i-line photoresist, OiR 897-10i, has

More information

Fabrication and Characterization of Pseudo-MOSFETs

Fabrication and Characterization of Pseudo-MOSFETs Fabrication and Characterization of Pseudo-MOSFETs March 19, 2014 Contents 1 Introduction 2 2 The pseudo-mosfet 3 3 Device Fabrication 5 4 Electrical Measurement and Characterization 7 5 Writing your Report

More information

A FIVE MICRON, SELF-ALIGNED, POLYSILICON GATE CMOS PROCESS DESIGN

A FIVE MICRON, SELF-ALIGNED, POLYSILICON GATE CMOS PROCESS DESIGN A FIVE MICRON, SELF-ALIGNED, POLYSILICON GATE CMOS PROCESS DESIGN BY JOHN P. SCOOPO Fifth Year Microelectronic Engineering Student Rochester Institute of Tehnology ABSTRACT The design of a five micron,

More information

Outline. 1 Introduction. 2 Basic IC fabrication processes. 3 Fabrication techniques for MEMS. 4 Applications. 5 Mechanics issues on MEMS MDL NTHU

Outline. 1 Introduction. 2 Basic IC fabrication processes. 3 Fabrication techniques for MEMS. 4 Applications. 5 Mechanics issues on MEMS MDL NTHU Outline 1 Introduction 2 Basic IC fabrication processes 3 Fabrication techniques for MEMS 4 Applications 5 Mechanics issues on MEMS 2.2 Lithography Reading: Runyan Chap. 5, or 莊達人 Chap. 7, or Wolf and

More information

Contribution of Gate Induced Drain Leakage to Overall Leakage and Yield Loss in Digital submicron VLSI Circuits

Contribution of Gate Induced Drain Leakage to Overall Leakage and Yield Loss in Digital submicron VLSI Circuits Contribution of Gate Induced Drain Leakage to Overall Leakage and Yield Loss in Digital submicron VLSI Circuits Oleg Semenov, Andrzej Pradzynski * and Manoj Sachdev Dept. of Electrical and Computer Engineering,

More information

Supplementary Information

Supplementary Information Supplementary Information Wireless thin film transistor based on micro magnetic induction coupling antenna Byoung Ok Jun 1, Gwang Jun Lee 1, Jong Gu Kang 1,2, Seung Uk Kim 1, Ji Woong Choi 1, Seung Nam

More information

Cost Effective Mask Design in CMOS Transistor Fabrication for Undergraduates Program

Cost Effective Mask Design in CMOS Transistor Fabrication for Undergraduates Program Proceedings of Encon2008 2& Engineering Conference on Sustainable Engineering nfrastructures Development & Management December 18-19,2008, Kuching, Sarawak, Malaysia Cost Effective Mask Design in CMOS

More information

This Week s Subject. DRAM & Flexible RRAM. p-channel MOSFET (PMOS) CMOS: Complementary Metal Oxide Semiconductor

This Week s Subject. DRAM & Flexible RRAM. p-channel MOSFET (PMOS) CMOS: Complementary Metal Oxide Semiconductor DRAM & Flexible RRAM This Week s Subject p-channel MOSFET (PMOS) CMOS: Complementary Metal Oxide Semiconductor CMOS Logic Inverter NAND gate NOR gate CMOS Integration & Layout GaAs MESFET (JFET) 1 Flexible

More information

32nm High-K/Metal Gate Version Including 2nd Generation Intel Core processor family

32nm High-K/Metal Gate Version Including 2nd Generation Intel Core processor family From Sand to Silicon Making of a Chip Illustrations 32nm High-K/Metal Gate Version Including 2nd Generation Intel Core processor family April 2011 1 The illustrations on the following foils are low resolution

More information

Dr. Lynn Fuller, Ivan Puchades

Dr. Lynn Fuller, Ivan Puchades ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Bulk Micromachined Laboratory Project Dr. Lynn Fuller, Ivan Puchades Motorola Professor 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel

More information

Nanostencil Lithography and Nanoelectronic Applications

Nanostencil Lithography and Nanoelectronic Applications Microsystems Laboratory Nanostencil Lithography and Nanoelectronic Applications Oscar Vazquez, Marc van den Boogaart, Dr. Lianne Doeswijk, Prof. Juergen Brugger, LMIS1 Dr. Chan Woo Park, Visiting Professor

More information

CMOS as a Research Platform Progress Report -June 2001 to August 2002-

CMOS as a Research Platform Progress Report -June 2001 to August 2002- CMOS as a Research Platform Progress Report -June 2001 to August 2002- Zhiping (James) Zhou Microelectronics Research Center Georgia Institute of Technology http://cmos.mirc.gatech.edu September 5, 2002

More information

Process Control Limits in a CMOS ASIC Fabrication Process K. Jayavel, K.S.R.C.Murthy

Process Control Limits in a CMOS ASIC Fabrication Process K. Jayavel, K.S.R.C.Murthy Process Control Limits in a CMOS ASIC Fabrication Process K. Jayavel, K.S.R.C.Murthy Society for Integrated circuit Technology and Applied Research Centre (SITAR), 1640, Doorvaninagar, Bangalore, Karnataka,

More information

Device Fabrication: Photolithography

Device Fabrication: Photolithography Device Fabrication: Photolithography 1 Objectives List the four components of the photoresist Describe the difference between +PR and PR Describe a photolithography process sequence List four alignment

More information

INTRODUCTION TO MICROMACHINING AND MEMS: A LECTURE AND HANDS-ON LABORATORY COURSE FOR UNDERGRADUATE AND GRADUATE STUDENTS FROM ALL BACKGROUNDS

INTRODUCTION TO MICROMACHINING AND MEMS: A LECTURE AND HANDS-ON LABORATORY COURSE FOR UNDERGRADUATE AND GRADUATE STUDENTS FROM ALL BACKGROUNDS INTRODUCTION TO MICROMACHINING AND MEMS: A LECTURE AND HANDS-ON LABORATORY COURSE FOR UNDERGRADUATE AND GRADUATE STUDENTS FROM ALL BACKGROUNDS Jack W. Judy and Paulo S. Motta Electrical Engineering Department,

More information

Chapter 3 CMOS processing technology (II)

Chapter 3 CMOS processing technology (II) Chapter 3 CMOS processing technology (II) Twin-tub CMOS process 1. Provide separate optimization of the n-type and p-type transistors 2. Make it possible to optimize "Vt", "Body effect", and the "Gain"

More information

EE141-Fall 2009 Digital Integrated Circuits

EE141-Fall 2009 Digital Integrated Circuits EE141-Fall 2009 Digital Integrated Circuits Lecture 2 Integrated Circuit Basics: Manufacturing and Cost 1 1 Administrative Stuff Discussions start this Friday We have a third GSI Richie Przybyla, rjp@eecs

More information

Wafer-level Vacuum Packaged X and Y axis Gyroscope Using the Extended SBM Process for Ubiquitous Robot applications

Wafer-level Vacuum Packaged X and Y axis Gyroscope Using the Extended SBM Process for Ubiquitous Robot applications Proceedings of the 17th World Congress The International Federation of Automatic Control Wafer-level Vacuum Packaged X and Y axis Gyroscope Using the Extended SBM Process for Ubiquitous Robot applications

More information

SUPPLEMENTARY INFORMATION

SUPPLEMENTARY INFORMATION SUPPLEMENTARY INFORMATION doi:10.1038/nature11293 1. Formation of (111)B polar surface on Si(111) for selective-area growth of InGaAs nanowires on Si. Conventional III-V nanowires (NWs) tend to grow in

More information

3084 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 60, NO. 4, AUGUST 2013

3084 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 60, NO. 4, AUGUST 2013 3084 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 60, NO. 4, AUGUST 2013 Dummy Gate-Assisted n-mosfet Layout for a Radiation-Tolerant Integrated Circuit Min Su Lee and Hee Chul Lee Abstract A dummy gate-assisted

More information

Characterization of SOI MOSFETs by means of charge-pumping

Characterization of SOI MOSFETs by means of charge-pumping Paper Characterization of SOI MOSFETs by means of charge-pumping Grzegorz Głuszko, Sławomir Szostak, Heinrich Gottlob, Max Lemme, and Lidia Łukasiak Abstract This paper presents the results of charge-pumping

More information

Outcomes. Spiral 1 / Unit 8. DeMorgan s Theorem DEMORGAN'S THEOREM. Transistor Implementations CMOS Logic Gates

Outcomes. Spiral 1 / Unit 8. DeMorgan s Theorem DEMORGAN'S THEOREM. Transistor Implementations CMOS Logic Gates 18.1 18.2 Spiral 1 / Unit 8 Transistor Implementations MOS Logic Gates Mark Redekopp Outcomes I know the difference between combinational and sequential logic and can name examples of each. I understand

More information

Contrast Enhancement Materials CEM 365HR

Contrast Enhancement Materials CEM 365HR INTRODUCTION In 1989 Shin-Etsu Chemical acquired MicroSi, Inc. including their Contrast Enhancement Material (CEM) technology business*. A concentrated effort in the technology advancement of a CEM led

More information

An X band RF MEMS switch based on silicon-on-glass architecture

An X band RF MEMS switch based on silicon-on-glass architecture Sādhanā Vol. 34, Part 4, August 2009, pp. 625 631. Printed in India An X band RF MEMS switch based on silicon-on-glass architecture M S GIRIDHAR, ASHWINI JAMBHALIKAR, J JOHN, R ISLAM, C L NAGENDRA and

More information

EE 330 Lecture 11. Capacitances in Interconnects Back-end Processing

EE 330 Lecture 11. Capacitances in Interconnects Back-end Processing EE 330 Lecture 11 Capacitances in Interconnects Back-end Processing Exam 1 Friday Sept 21 Students may bring 1 page of notes HW assignment for week of Sept 16 due on Wed Sept 19 at beginning of class No

More information

Design Simulation and Analysis of NMOS Characteristics for Varying Oxide Thickness

Design Simulation and Analysis of NMOS Characteristics for Varying Oxide Thickness MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 2, August 2014, pp. 81 85 81 Design Simulation and Analysis of NMOS Characteristics for Varying Oxide Thickness Alpana

More information

EXPERIMENT # 1: REVERSE ENGINEERING OF INTEGRATED CIRCUITS Week of 1/17/05

EXPERIMENT # 1: REVERSE ENGINEERING OF INTEGRATED CIRCUITS Week of 1/17/05 EXPERIMENT # 1: REVERSE ENGINEERING OF INTEGRATED CIRCUITS Week of 1/17/5 Experiment #1: Reading: Reverse engineering of integrated circuits Jaeger 9.2: MOS transistor layout and design rules HP4145 basics:

More information

AN ELECTRET-BASED PRESSURE SENSITIVE MOS TRANSISTOR

AN ELECTRET-BASED PRESSURE SENSITIVE MOS TRANSISTOR 587 AN ELECTRET-BASED PRESSURE SENSITIVE MOS TRANSISTOR J.A. Voorthuyzen and P. Bergveld Twente University, P.O. Box 217, 7500 AE Enschede The Netherlands ABSTRACT The operation of the Metal Oxide Semiconductor

More information

Digital Integrated Circuit Design I ECE 425/525 Chapter 3

Digital Integrated Circuit Design I ECE 425/525 Chapter 3 Digital Integrated Circuit Design I ECE 425/525 Chapter 3 Professor R. Daasch Depar tment of Electrical and Computer Engineering Portland State University Portland, OR 97207-0751 (daasch@ece.pdx.edu) http://ece.pdx.edu/~ecex25

More information