CMOS as a Research Platform Progress Report -June 2001 to August 2002-

Transcription

1 CMOS as a Research Platform Progress Report -June 2001 to August Zhiping (James) Zhou Microelectronics Research Center Georgia Institute of Technology September 5, 2002

2 Outline Introduction Platform Baselines Services Training Research People Conclusions Acknowledgments

3 Introduction Why Platform The baseline alone is not enough to support research and new initiatives such as sea of leads (SOL), MEMS sensors, or communications technologies. What the Platform does The platform facilitates a synergetic collaboration between CMOS research and other research projects, which may also involve training, service, and facility support.

4 Platform CMOS AS A RESEACH PLATFORM PEOPLE BASELINES SERVICES TRAINING RESEARCH

5 Baselines CMOS runs Finished Batch 5, 6, 7; Started Batch 8 Development Electrical test In-line test matrix Recipe refinement Maintenance Checking equipment status Working with maintenance staff

6 Baselines Electrical test status summary Installed LabView 6i on PC and now have GPIB control of HP 4156 parametric analyzer, Keithley 590 CV meter, Alessi REL-6100 probe station movement Identified 541 parametric tests of which 459 (85%) are completed in LabView code and fully automated Reduced man hours from ~80 to 1 and test time from 2 weeks to 3 days Can sample any number of die across wafer as desired Results are stored in an ASCII text file for easy use with various analysis software Testing has provided several insights for process improvement such as transistor leakage with wafer flat GFA

7 Baselines In-line test matrix Independent (Test Grade) Split I-1 I-2 I-3 I-4 I-5 I-6 I-7 I-8 I-9 I-10 I-11 # Wafers Process Sequences Initial Oxidation Pad Oxidation Sacrificial Oxide Gate Oxidation Capacitor Oxide LOCOS PSG Deposition Metal-1 Deposition SOG Deposition 2nd PSG Deposition VIA Photo N-Well Litho Nitride Hard Mask 1st PolySilicon 2nd PolySilicon Nitride Wet Etch PSG Densification Metal-2 RIE Etch Back Test Via Etch to ME-1 Nitride RIE Poly Doping Poly Doping PSG Etch Sintering Poly Anneal Poly Anneal Poly Etch Poly Etch I-12 2 Metal 2- Deposition Metal-2 RIE Sintering Monitor (Prime Grade) Split M-1 M-2 M-3 M-4 M-5 M-6 M-7 M-8 # Wafers Process Sequences Intiial Oxidation Pad Oxidation Sacrificial Oxide Gate Oxidation Capacitor Oxide Gate/Cap Sequence N+ S/D Implant P+ S/D Implant N-Well Implantation Field Implantation Threshold Implant 1st PolySilicon 2nd PolySilicon Drive In Drive In Poly Doping Poly Doping Poly Anneal Poly Anneal CMOS Batch 8 9/4/02

8 Baselines Publications 1. M. S. Bakir, H. D. Thacker, Z. Zhou, P. A. Kohl, K. P. Martin, and J. D. Meindl, "Sea of lead microwave characterization and process integration with FEOL & BEOL," IEEE International Interconnect Technology Conference, pp , San Francisco, CA, June Jiandong Jin and Zhiping Zhou, Simulation and Modeling of Micro Pressure Sensor Array Int. Conf. MSM 2002, pp , San Juan, Puerto Rico, April 22-25, Zhou, Z. CMOS as a Research Platform, Proceedings of the 14 th University/Government/Industry Microelectronics Symposium, pp , Virginia Commonwealth University, Richmond, VA, June 17-20, Akil Sutton and Zhiping Zhou, Simulation of Georgia Tech s CMOS Baseline Using T- SUPREM4 and MEDICI, Proceedings of the 14 th University/Government/Industry Microelectronics Symposium, pp , Virginia Commonwealth University, Richmond, VA, June 17-20, Aric Madayag and Zhiping Zhou, Optimization of Spin-On-Glass Process for Multilevel Metal Interconnects, Proceedings of the 14 th University/Government/Industry Microelectronics Symposium, pp , Virginia Commonwealth University, Richmond, VA, June 17-20, 2001.

9 Services The Platform provides the following processing services to Tech research community and other research group around the world. Process Modules Run (as needed) CMOS Runs (Quarterly) Wet/Dry oxidation Process design LPCVD HTO and nitride growth IC design LPCVD low-stress nitride growth Mask design LPCVD polysilicon growth Processing RIE nitride and poly etch Characterization ICP deep trench processing Mask Making Lithography Mask design consultation Multilevel interconnection Mask fabrication Processing consultation Any combination of above

10 Services Service requests completed CMOS run: Batch 7 Process modules run: 29 Mask fabrication: 195 Revenue: over $49,000 Masks Generated Jun-01 Aug-01 Oct-01 Dec-01 Feb-02 Apr-02 Jun-02 Aug-02 Month Num. of Process Requests Jun-01 Jul-01 Aug-01 Sep-01 Oct-01 Nov-01 Dec-01 Jan-02 Feb-02 Mar-02 Apr-02 May-02 Jun-02 Jul-02 Aug-02 Month

11 Services service completed without revenue CMOS run: Batch 5, 6 Process modules run: 41 Mask fabrication: 38

12 Training Training content Onsite equipment training, one-on-one check off, processing training, and chemical safety refresher Trainers Over 20 people includes MiRC Staff, Graduate students, Student assistants Attendees Over 450 on-site classes have been offered and more than 2500 attendees have gone through the program since September 1999

13 Equipment Training Group training One-on-one check-off

14 Equipment Training 09/13/99 10/28/99 11/08/99 12/09/99 01/24/00 02/21/00 04/03/00 05/15/00 06/26/00 07/24/00 09/11/00 10/30/00 11/27/00 01/22/01 02/19/01 03/26/01 04/23/01 05/29/01 06/25/01 07/23/01 08/27/01 09/24/01 10/29/01 11/26/01 01/28/02 02/26/02 03/25/02 05/28/02 06/24/02 07/29/02 08/26/02 Training Session Start Date Signup per Session Total Signups

15 Processing Training CMOS baseline processing training 6 research groups participated in complete processing training and 3 research groups are using the CMOS baseline processing to integrate/fabricate their devices Individual processing module training Mask design, lithography, deposition, oxidation, surface preparation, plasma etching, SEM inspection, etc. Processing consultation Over 80 graduate or postdoctoral students from 32 PIs benefited from the free consultation

16 Chemical Safety Refresher

17 Research The Platform supports a variety of research, which includes, but is not limited to, the following programs: Novel CMOS structures and processing Semiconductor Sensor arrays Integration of CMOS and MEMS Integrated optoelectronics New interconnection schemes Sea of leads chip input/output interconnects

18 1. Thin Film Deposition Material/dielectric development and characterization Polysilicon Stress, growth rate, grain size, and surface roughness Sio 2,Si x N y,sio x N y Deposition methods: LPCVD, PECVD, APCVD Full control of stress, composition, thickness, refractive index Partial control of conformality

19 2. CMP Objectives Investigate the influence of pad roughness (conditioning) and abrasive size on dishing and erosion Investigate the effect of process conditions on dishing and erosion Investigate the influence of suction pressure on the location of dishing and erosion Develop physics-based models of dishing and erosion

20 SEM Images of Patterned Wafers (a) Top view (b) Cross-section showing SiO 2 trenches (c) Cross-section showing Ta/Cu seed layer

21 SEM Images of Patterned Wafers (d) Cross-section showing electro-plated Cu (e) Cross-section showing DC sputtered Cu

22 3. Chemical Sensor Array

23 8-channel chemical sensor array GT-01

24 4. CMOS/MEMS Integration CMOS based integration

25 4.1 MEMS Pressure Sensor Array Design Concept The distribution of stress on elastic diaphragm depends on diaphragm structure and material parameters. Each designed chip includes one temperature sensor, three absolute pressure sensors, one differential pressure sensor, and one signal collecting and processing circuit. CMOSCIRCUIT AP3 AP1 DP AP2 Fig.1. The sensor array layout Fig.2. The cross-section of a differential pressure sensor Fig.3. The cross-section of an absolute pressure sensor

26 Circuits designs unbuffered, two-stage CMOS Op-amp Analog MUX

27 ANSYS Model The rectangular diaphragm consists of polysilicon and silicon nitride. The resistors are made of polysilicon and aluminum. All volumes should be defined with respective material parameters. Using the conversion factors from standard MKS to µmksv. (Units related with meter change to micrometer related.). Selecting proper element type and mesh size. Fig.4 The absolute pressure sensor cross sketch Al Si3N4 Doped poly Si3N4 Polysilicon Cavity Si Substrate

28 Results ANSYS Simulation Polysilicon growth Poly membrane on air gap

29 4.2 Silicon Photodiode Detector Array Current [A] Photodiode Characterization Lamp On Lamp Off 1.50E E E E E E E E E E E E E Voltage [V] Batch 7 fabrication and test result

30 4.3 Conformal Coating SEM Results oxide oxide 600nm High Temperature LPCVD Oxide

31 5. CMOS/SOL Integration

32 People It is a vital link between research and development sectors and fabrication technologies at Georgia Tech. It consists of MiRC staff, GRAs, co-op students, and student assistants to provide support to other four components of the Platform. The Platform provides a unique opportunity for these people to master their processing skill and enhance their collaboration experience while serving research and development communities.

33 People

34 People Student hours Published schedule on web Meet at 8:00am daily to discuss job to be done Often come to work on weekends and after hours

35 Processing Team

36 Processing Team

37 Conclusions A unique, extended CMOS Platform for research has been progressing to its perfection. The Platform is attracting research and development groups from the campus and around the world. The Platform provides An extensive processing service via its CMOS baselines operation A free training program to facilitate cleanroom usage A vital link between research sectors and fabrication technologies The creation of the Platform has significantly elevated the research and process capability at MiRC of Georgia Tech.

38 Acknowledgments The Platform has been encouraged and supported by the MiRC Director, Dr. James D. Meindl. The participation and support of the MiRC staff, CMOS group members, equipment trainers, and the MiRC affiliated PIs makes this program possible. The efforts of Mr. Todd McKenzie, Mr. Eric Woods, Mr. Matthew Leidy, and Mr. Akil Sutton add tremendous values to the program.