High Voltage and MEMS Process Integration
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1 ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING High Voltage and MEMS Process Integration Dr. Lynn Fuller and Dr. Ivan Puchades webpage: Electrical and Microelectronic Engineering Rochester Institute of Technology 82 Lomb Memorial Drive Rochester, NY microe program webpage: HV_Integration.pptx Page 1
2 OUTLINE Introduction Specifications Design and Simulation Photo Mask approach Process Flow Optimization Test Results Summary Page 2
3 DESIGN AND FABRICATE LARGE INK JET PRINT HEAD 2-inch wide ink jet print head chip design such that 1inch 700 jet cell can be copied and pasted to make larger print heads up to 6 inch width. Each ink jet (cell) is 240um high and 600um wide. The 1 inch wide array is 15 rows and 42 columns. Shown above is 2 inch wide array of 2800 individual ink jets. Page 3
4 240 um High Voltage Process Integration INK JET CELL DETAIL 600 um Column select 30V (Metal 2) Row select Gate (Metal 1) Ground thru substrate 500 ohm Resisor Ink Reservoir Page 4
5 ADDRESSING SINGLE INK JET CELL Column CONSIDERATIONS Row Resistor NMOS Gate Delay (propagation along two inch metal line connected to 47 gate capacitances) Resistance to ground (should be as low as possible) NMOSFET Voltages and Currents RESISTOR Thermal properties Page 5
6 SPICE SIMULATION OF 1us PULSE PROPAGATION Simulation: Uniform Distributed RC Lines (Lossy) is used. Model needs resistance and capacitance per unit length as input. 1) 1um thick, 2 Al line, 1usec signal: 3) 1um thick, 4 Al line, 1usec signal: 2) 0.75um thick, 2 Al line, 1usec signal: 4) 0.75um thick, 4 Al line, 1usec signal: Page 6
7 CALCULATION OF RESISTANCE TO GROUND Equivalent model for wafer, to be used in calculation: P- epi R = R epi + R substrate R epi R substrate 10um 675um P++ substrate T T W1, L1 W3, L3 6 cm W2, L cm Where: R T = Thickness of the region p = Resistivity of the material T WL W, L= Width, length of the top rectangle a = Ratio of the width of the bottom rectangle to the width of top rectangle b = Ratio of the length of the bottom rectangle to the length of the top rectangle ln a a b b (Gray and Meyer) Page 7
8 CALCULATION OF RESISTANCE TO GROUND In the circuit, the source resistor should not have a voltage across it more than 2V, this means: R source x 40mA < 2V, R source < 50ohms So, the dimensions are: W1 = 70um L1 = 230um W2 = 90um L2 = 250um W3 = 1440um L3 = 1600um R R 6 cm x 10 um epi 70 um x 230 um substrate cm 90 um x ln( 90 / 70 ) 250 / ln( x 675 um um and the answer is / 90 / ) and the answer is 0.43 R = R epi + R substrate = ohms, and the potential drop across this R = 1.28V Page 8
9 NMOSFET V, I AND SIZE REQUIREMENTS High Voltage on Drain and Gate Vgate either 5, 10, 15 or 20V (determined by address electronics) Vdrain=30V Idrain= ~ 40mA (determines size of transistor) Transistor Size Requirements - Matrix set up: Cells are 240um high and 600um wide Approximately 240x350um for transistor Location of NMOSFET Page 9
10 Column VDD =30V NMOSFET VOLTAGES C o lu m n V D D = 30V R=500 Ohm ID=40mA R=500 Ohm ID=0A Row VGATE =15V VDS=10V Resistance to ground? R o w V G A T E = 0 V VDS=30V ON VGATE=15V and VDD=30V ID=40mA, VDS=10V OFF VGATE=0V and VDD=30V VGATE=15V and VDD = 0V Page 10
11 HIGH VOLTAGE TRANSISTORS Xox Metal Gate N- N+ P- epi P++ Thick gate oxides to prevent gate oxide breakdown (30 Volts) Low doping on both sides of drain-to-well pn junction to give large depletion width, low electric field and give high breakdown voltage. Deep drain junctions to increase radius of curvature, reduce electric field and give high breakdown voltage. Long channel length to prevent punch through Page 11
12 NMOSFET PROCESS SIMULATION Metal Gate Lower Doped Drain Well - HVNW N+ Source P+ Contact to Substrate and Ground P-well N+ Drain Channel Stop Silvaco Athena Channel length is ~3µm. Good alignment between N+ source and HVNW is required. Page 12
13 NMOS TRANSISTOR CONSIDERATIONS N/P Junction Reverse Bias Breakdown. I 30V Reverse Bias Forward Bias N+ P 0V Breakdown V Max E field in Si is 3E5V/cm Breakdown voltage is related to the concentration of lower doped side BV Si 2 max 2 qna Page 13
14 NMOS TRANSISTOR CONSIDERATIONS BV dependence of junction depth and curvature * Page 14
15 NMOS TRANSISTOR CALCULATIONS With Vdrain=30V -Make Gate oxide 1000Å, Ey=3.0MV/cm -C ox=3.45e-8f/cm 2 Threshold voltage with NA=3.5E15/cm 3 is VT adjust implant needed for VT=1 is Boron, dose=8e11/cm 2 V Q ' ox V FB ms C ' ox TN V FB +/- Vt = q Dose /Cox N+/PW build in voltage = 0.85V s s 2 q With VR=30V, Wd=3.35um, =1.84E5V/cm <3E5V/cm Wd W 1 W 2 = [ (2 si q F +V R ) (1/N A 1/N D )] 1/2 C ' = - [(2q/ si F+V R ) (N A N D /(N A N D ))] 1/2 si ox N A s F 2 4 q Volts/cm F kt ln N n i A t Page 15
16 NMOSFET SIMULATIONS Silvaco Emax=1.6e5V/cm<E crit(3e5v/cm) P-EPI NA Equipotential lines in the HVNW with VD>35V. Emax=1.2e5V/cm<E crit(3e5v/cm) Page 16
17 NMOSFET ELECTRICAL SIMULATIONS Silvaco Atlas For VG=5V IDS/W=60µA/µm W for 60mA=1000µm For VG=10V IDS/W=100µA/µm W for 60mA=600µm For VG=20V IDS/W=350µA/µm W for 60mA=171µm Channel W set to 210µm Page 17
18 MASK MAKING RIT Mask Making Capabilities (MEBES Electron Beam Writer) 1X masks for RIT Karl Suss Aligner (6 x 6 x ) Qty 3 5X masks for RIT ASML I-Line Stepper (6 x 6 x ) Qty 3 1X masks for Company s Karl Suss Aligner (6 x 6 x ) Qty 5 5X masks for Company s Canon Stepper (6 x 6 x ) Qty 5 RIT Price is $500 each = ~$8,000 Commercial Price is $2000 each = ~$32,000 Page 18
19 FOURTEEN DIFFERENT MASKS USED RIT layers:: layer 99 -> Alignment keys 5X layer 1 -> Active 1X layer 4 -> Nplus 5X layer 6 -> HVNW 5X layer 3 -> Pplus 1X layer 7 -> Contact cut 1X layer 24 -> 60 Metal1 1X (Lab s 1 st ) Company s Research Lab layers:: layer 15 -> 30 Metal2 layer 29 -> 70 Via layer 30 -> 80 Heater layer 34 -> 90 Feed Channel layer 37 -> 96 Backside holes layer 19 -> Polyimide chamber layer 25 -> 04 Nozzles Page 19
20 1. Initial 100 Silicon, boron=3.5e15 2. Alignment layer photo 5X Stepper- dark field reticle 3. Alignment etch Silicon etch 4. Grow 500Å oxide (43min at 1000C) 5. Deposit 1500Å Si3N4 PROCESS FLOW 6. Active photo 1X clear field 7. Nitride etch (LAM490) 8. Channel stop boron implant Dose=5e12, 80KeV 9. Strip resist, RCA Clean Photoresist Si3N4 SiO2 P+ P+ P-EPI Page 20
21 PROCESS FLOW - HVNW 10. LOCOS oxidation (210min at 1100, weto2) 11. Strip nitride (Hot phosphoric) 12. HF dip to remove oxide 13. Kooi oxide (45min at 900C, wet O2) 14. HVNW photo - 5X stepper, dark field 15. HVNW implant Phos Dose=9e12 at 80KeV 16. Strip resist, RCA Clean FOX PR HVNW PR FOX P-EPI Page 21
22 N++ S/D 17. HVNW Drive, 90min at 1100C, N2 18. VT adjust implant boron 1.1e12, 60KeV 1.1e12, 100KeV 19. N+ Photo 5X stepper, dark field 20. N+ Implant Phos 4e15, 100KeV 21. Strip resist, RCA Clean FOX PR N+ N+ N+ HVNW FOX P-EPI 22 Page 22
23 22. P+ Photo 1X dark field 23. P+ Implant Boron 2e15, 60KeV 24. Strip resist, RCA Clean 25. Remove Kooi oxide 1 min HF P++ SUBSTRATE CONTACT P++ N+ N+ N+ HVNW P++ P-EPI Page 23
24 METAL GATE AND S-S-D CONTACT 26. Grow 1000Å gate oxide 160min at 1000C dryo2 27. Contact cut photo 1X dark field 28. Contact cut etch (5.2:1 BOE 1min) 29. Strip resist, RCA Clean final HF dip 30. Metal dep (1.2µm) AlSi 31. Metal photo 1x clear field 32. Metal etch 33. Sinter P++ N+ N+ N+ HVNW P++ P-EPI Page 24
25 LAYOUT OF TRANSISTOR WITHIN CELL Gate Source Drain W=210µm Source Page 25
26 LAYOUT AND PHOTO P+ P+ N+ N+ N+ I P-channel and HVNW P-channel and HVNW I Page 26
27 1 st LOT L st lot L Channel Stop 8e13, 100KeV HVNW 9e12, 120KeV HVNW drive 210min + O2 IDS(VG=20V)=85mA ILK(VD=20V)=20mA BVDSS=20V HVNW to N+ seemed shorted. Reduce HVNW drive. Page 27
28 2 nd LOT L nd lot L Channel stop 8e13, 100KeV HVNW 9e12, 80KeV HVNW drive 140min++O2 IDS=55mA ILK(VD=20V)=10µA BVDSS=20V Remove O2 from HVNW drive. Increase BVDSS. 1X alignment issues. 6-inch mask holder. Page 28
29 4th lot L Channel stop 8e13, 80/100KeV HVNW 9e12/1e13, 80KeV HVNW drive 90/120min nit IDS=53mA ILK=1µA BVDSS=22V 4 th LOT L HVNW drive needs to be shorten even further. Low leakage for wafer with 90min and 9e12 dose after sinter. Channel stop implant dose reduction 120min Drive 90min Drive Page 29
30 HVNW Drive-in High Voltage Process Integration 5th lot L Channel stop 5e12, 80KeV HVNW 9e12/1e13, 80KeV HVNW drive 80/90min nit 90min 5 th LOT L min 9e12 1e13 HVNW Implant IDS ~ 65mA ILK <0.5µA BVDSS > 45V Targets met for IDS, ILK and BVDSS. R Page 30
31 HVNW WINDOWING Oneway Analysis of IDS(VG20,VD10) By HVNW Oneway Analysis of ILK(VG0,VD30 By HVNW ID S ( V G 2 0,V D 1 0 ) IL K ( V G 0,V D e13/80min 1e13/90min 9e12/80min 9e12/90min HVNW Each Pair Student's t e13/80min 1e13/90min 9e12/80min 9e12/90min HVNW Each Pair Student's t 0.05 Means and Std Deviations Means and Std Deviations Level Number Mean Std Dev Level Number Mean Std Dev 1e13/80min 1e13/90min 9e12/80min e13/80min 1e13/90min 9e12/80min e12/90min e12/90min IDS very little variation between the groups. ILK Best is 9e12/80min group. Higher leakage for 1e13/90min. Page 31
32 BEST NMOSFET RESULTS Page 32
33 CONCLUSION Successful development and fabrication of a 30V high-side NMOS transistor. IDS, ILK and BVDSS requirements have been met. Robust process flow has been designed and demonstrated. Fabrication of ~20 wafers has been completed. Continuous process improvement to reduce ILK even further and improve drain series resistance. Page 33
34 TEXTBOOK/REFERENCES 1. Modern Semiconductor Devices for Integrated Circuits, Chenming Hu, Prentice Hall, Solid State Electronic Devices, 5 th Edition, Ben Streetman, Sanjay Banerjee, Prentice Hall, Silicon VLSI Technology, James Plummer, Michael Deal, Peter Griffin, Prentice Hall, Analysis and Design of Analog Integrated Circuits, Gray and Meyer, John Wiley. Page 34
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