SQUID Test Structures Presented by Makoto Ishikawa

Transcription

1 SQUID Test Structures Presented by Makoto Ishikawa We need to optimize the microfabrication process for making an SIS tunnel junction because it is such an important structure in a SQUID. Figure 1 is a CAD layout of a mask set for a tunnel junction test chip designed by Mark Bowen. Each color represents a separate thin film layer. We will install this chip in a chip carrier and wirebond connections to the rectangular contact pads along the outer edges of the chip. The chip carrier will be mounted in the sample stage of a refirgerator. We will measure electrical characteristics such as I-V curves of tunnel junctions, resistance and superconducting transitions of superconducting films, and leakage currents of insulating layers. The actual chip dimensions are 1 cm X 1 cm. Even on this enlarged view you cannot distinguish details of the small test devices, so I will present qualitative descriptions and sketches of the various structures. Figure 1: Layout of Tunnel Junction Test Chip Figure 2 is a simplified cross-sectional view of an SIS tunnel junction. The figure shows the qualities that we want to test and optimize. In a preliminary set of room temperature measurements we will determine the stress in niobium and SiO 2 films. We will measure the resistance of the niobium films as we cool them down in order to evaluate the quality of the films. We will measure I-V curves to determine the critical current of single junctions and the range of critical currents among junctions in a series Figure 2: Quantities to be Tested and Optimised

2 array. We will measure the interface resistance between the counterelectrode and the wiring layer. We will measure the leakage resistance due to pinholes in the SiO 2 film, and we will measure the breakdown voltage of the SiO 2 film. Figure 3 is a graph of the resistance of a metal film as a function of temperature. Electrical resistance is due to scattering of electrons. Scattering of electrons by lattice vibrations, or phonons, varies linearly with the temperature, so at higher temperatures it is the dominant scattering process Electrons also are scattered by lattice imperfections such as defects, impurities, grain boundaries, and thin film surfaces. Figure 3: Variation of Resistance with Temperature in a This scattering process, which depends Superconductor upon the defect concentration but not the temperature, is the dominant scattering mechanism at a sufficiently low temperature. The Residual Resistance Ratio RRR is the ratio of the resistance at 300 K to the resistance at 10 K. In a perfect film in which only phonons scatter electrons the RRR would equal 30. Lower values of the RRR indicate a greater concentration of imperfections. (See Figure 4.) The resistance drops abruptly to zero if the film enters the superconducting state at a critical temperature T C. We are very interested in the value of T C and the width of the transition (on the scale shown on the graph the transition width is not observable, so the transition appears vertical). If you zoom in on the transition it will appear to be sloped. Figure 5 is a schematic of the test structure used to meaure the RRR, and also T C and T C for the trilayer SIS junctions and the wiring layer. Superconducting Thin Film Resistance R 0.9 R 0.1 R 0 0 Temperature Figure 4: Superconducting Transition, Viewed on an Expanded Temperature Scale T C T C T Figure 6 is the DC I-V curve of a single SIS tunnel junction. As the current through the junction is increased, the operating point initially follows the zero-voltage branch. When the current exceeds

3 the critical current, then the operating point jumps over to the non-zero voltage branch. If many junctions are connected in series, the same current flows through each junction in the array. As the current through the array is increased, initially all of the junctions will be operating on their zero voltage branches. When the current passes through the critical current of an individual junction, the operating point of that junction will jump to its non-zero voltage branch, and a step will appear in the array I-V curve as shown in the drawing. (See Figure 7.) The range of values of critical currents for the junctions can be determined by measuring the difference in current between the lowest and highest breakpoints in the I-V curve for the array. A large range of critical currents indicates that the tunnel barriers are not uniform and/or that the dimensions of the junctions are not identical. Figure 5: Test Structure for RRR, T C, and T C of Superconducting Films Figures 8a and 8b (next page) are, respectively, photographs of a junction pair and a series array (the wiring layer has been omitted for clarity). Figure 6: I-V Curve for a Single SIS Junction (T = 0) Figure 9 (next page) is a cross-sectional view of the structure used to measure the interface resistance between the counterelectrode and the wiring layer. Ideally this resistance should be negligible because the counterelectrode will be bombarded with argon ions to remove surface contaminants before the wiring layer is deposited. Figure 7: I-V Curve for Series Array of SIS Junctions (only 3 junctions shown; T = 0) We expect the interface resistance to be small, so we measure the resistance of many interfaces in series. The test structure consists of a series array of contacts between segments of the counterelectrode (the top layer of a tunnel junction) and segments of the wiring layer.

4 Figure 8a: Photo of Junction Pair (Wiring Layer Omitted for Clairty) Figure 8b: Photo of Array of Junction Pairs (Wiring Layer Omitted for Clarity) Figure 10 is a cross-sectional view of the structure used to measure the leakage current and breakdown voltage of the SiO 2 layer that we use as an electrical insulator between the base electrode and the wiring layer. Figure 9: Counterelectrode Interface Resistance Test Structure The left side of the test structure consists of a uniform region of base electrode which is insulated from a wiring layer contact by a layer of sputtered SiO 2. If the SiO 2 film has no pinholes through it, then there is infinite resistance between the wiring layer and the base layer. If the SiO 2 film does have pinholes through it, then there are connections between the wiring layer and the base layer. The higher the density of pinholes, the lower the resistance between the films. Pinhole density in SiO 2 films can be reduced by sputtering in a mixture of argon and oxygen. The right side of the test structure consists of a spiral-shaped base electrode which is insulated from a wiring layer contact by a layer of sputtered SiO 2. The cross-section of the spiral contact appears as a set of equally spaced squares as shown in the figure. The thickness of the SiO 2 over the steps in the lower film is not as great as the thickness of SiO 2 over a uniform film. As a result, the breakdown voltage of the SiO 2 insulating layer of the right structure is lower than the breakdown voltage of the left structure. We Figure 10: SiO 2 pinhole and Breakdown Volatge Test Structure

5 want to confirm our ability to predict the breakdown voltage of a sputtered SiO 2 film as a function of the sidewall slope of steps that the SiO 2 has to cover.