High -speed serial shift registers

Transcription

1 High-speed serial shift registers High -speed serial shift registers John X. Przybysz and R. D. Blaugher Westinghouse Research and Development Center 131 Beulah Road, Pittsburgh, Pennsylvania John X. Przybysz and R. D. Blaugher Westinghouse Research and Development Center 131 Beulah Road, Pittsburgh, Pennsylvania ABSTRACT ABSTRACT An integrated circuit chip was designed for a Josephson based shift register, and chip processing was initiated. The circuit design simulates operation at 25 GHz in the SPICE program. The transmission lines used to distribute the three-phase clock were modeled with the SUPERCOMPACT program to provide balanced, in-phase circuit drive, up to 1 GHz. Integrated circuit processing procedures have been developed to permit reactive ion etching of all seven deposited layers. The 6.25 mm square chip featured a twelve-gate, four-stage shift register fabricated with Nb/AlO /Nb Josephson junctions of 2 A/cm critical current density. An integrated circuit chip was designed for a Josephson based shift register, and chip processing was initiated. The circuit design simulates operation at 25 GHz in the SPICE program. The transmission lines used to distribute the three -phase clock were modeled with the SUPERCOMPACT program to provide balanced, in -phase circuit drive, up to 1 GHz. Integrated circuit processing procedures have been developed to permit reactive ion etching of all seven deposited layers. The 6.25 mm square chip featured a twelve -gate, four -stage shift register fabricated with Nb /AlOx /Nb Josephson junctions of 2 A /cm critical current density. 1. INTRODUCTION 1. INTRODUCTION Josephson shift registers are desired for use as high-speed memories, for instance, to store the output data stream of a Josephson analog to digital convertor. A high-speed shift register with serial read-in and parallel read-out capability could provide an essential link between GHz superconductor circuitry and MHz semiconductor circuitry, as shown in Figure 1. Josephson shift registers are desired for use as high -speed memories, for instance, to store the output data stream of a Josephson analog to digital convertor. A high -speed shift register with serial read -in and parallel read -out capability could provide an essential link between GHz superconductor circuitry and MHz semiconductor circuitry, as shown in Figure 1. Mlcroweve Slgnel JOSEPHSON A/P WITH MEMORY JOSEPHSON A/P WITH MEMORY Josephson Digital A/D Josephson Digital i 1 A/D Outputs.. Outputs. Josephson Shift Register* Josephson Shutt Regletara,1,1,1 1,1,1,1 III MM Parallel Readouts 1 Parallel Readouts THREE PHASE SHIFT REGISTER THREE PHASE SHIFT REGISTER >1 9^2 9^ mA Display I Digital Signal Processor Digits( Signal Processor * Display * H r1 & JJ Model: JJ Model: Vgap = 2.7 mv o V9 =.3 mv IO= f[al Cj = 1.5 pf 177> Je = 2 A/cm2 ap = 2.7 mv = 1.5pF/ fg =.3 mv = 2 A/cm2 Figure 1. System concept for advanced radar. Figure 2. Circuit schematic for a single radar. Superconductor circuits stage of the three-phase provide gigahertz analog to Josephson shift register, digital conversion, memory, and demultiplex functions. Megahertz semiconductor circuits provide signal processing and display. Figure 1. System concept for advanced radar. Figure 2. Circuit schematic for a single radar. Superconductor circuits stage of the three -phase provide gigahertz analog to Josephson shift register. digital conversion, memory, and demultiplex functions. Megahertz semiconductor circuits provide signal processing and display. Westinghouse is engaged in a program to develop a superconductive shift register from 1 to 1 stages in length which will operate between 2 and 1 GHz. The shift register will be fabricated with refractory materials, either niobium or niobium nitride. Westinghouse is engaged in a program to develop a superconductive shift register from 1 to 1 stages in length which will operate between 2 and 1 GHz. The shift register will be fabricated with refractory materials, either niobium or niobium nitride. Previously, a Josephson shift register, suitable for a memory element in high-speed digital signal processing, was designed and simulated operation using the SPICE program. The three-phase shift register employs Direct Coupled Logic OR-gates connected in series, as shown in Figure 2. An unregulated clock supplies an offset sine-wave driving signal that can be tuned for optimum amplitude and de-bias. The Josephson junctions are Nb/AlO /Nb with 2 A/cm2 critical current density. The shift register circuit simulates properxoperation up to 25 GHz, as shown in Figure 3. These results show that 25 GHz shift register performance lies within the capabilities of a practical LSI Josephson junction technology. 5 Previously, a Josephson shift register, suitable for a memory element in high -speed digital signal processing, was designed and simulated operation using the SPICE program.1-3 The three -phase shift register employs Direct Coupled Logic OR- gates' connected in series, as shown in Figure 2. An unregulated clock supplies an offset sine -wave driving signal that can be tuned for optimum amplitude and dc-bias. The Josephson junctions are Nb /AlOx /Nb with 2 A /cm2 critical current density. The shift register circuit simulates proper operation up to 25 GHz, as shown in Figure 3. These results show that 25 GHz shift register performance lies within the capabilities of a practical LSI Josephson junction technology.s This paper describes our current efforts to lay out and fabricate a shift register chip to take advantage of the high-speed capability of Josephson electronics. Some modifications of the circuit were required because the SPICE simulation assumed lumped elements, This paper describes our current efforts to lay out and fabricate a shift register chip to take advantage of the high -speed capability of Josephson electronics. Some modifications of the circuit were required because the SPICE simulation assumed lumped elements, 1-3 SPIE Vol. 879 Sensing, Discrimination, & Signal Processing & Superconducting Materials & Instrumentation (1988) / 81 SPIE Vol. 879 Sensing, Discrimination, & Signal Processing & Superconducting Materials & Instrumentation (1988) / 81

2 I2=2I1 R1=2R2 Input Input Input 4 Ilk ka Input Stage t Stage 1 Stage2 Stage2 ym.«25 GHz SiIFT R GISTER2 25 GHz SHIFT REGISTER a Slope 1, Stage 1 * A A A LA/V-^/ :..AA* A, I I II I I l I Picoseconds 1 2 Picoseconds I- 1pm 1 pm Figure 3. SPICE simulation of the shift register operation at 25 GHz. Figure 3. SPICE simulation of the shift register operation at 25 GHz. Figure 4. Layout of a single DCL OR -gate in the shift register. Critical current ratios and resistor ratios of 2:1 were obtained by making three copies of each component and connecting two of each in parallel. while the actual circuit used distributed thin -film resistors. First attempts to fabricate the chip revealed the importance of controlling several aspects of the all reactive ion etching process. 2. CHIP DESIGN The chief constraints in the design of the chip were: 1. A process compatible with both Nb and NbN. 2. Freedom from tight dimensional tolerances. 3. Only one resistor metallization. 4. No planarization. 5. Minimum parasitic capacitance and inductance. Figure 4. Layout of a single DCL OR-gate in the shift register. Critical current ratios and resistor ratios of 2:1 were obtained by making three copies of each component and connecting two of each in parallel. while the actual circuit used distributed thin-film resistors. First attempts to fabricate the chip revealed the importance of controlling several aspects of the all reactive ion etching process. 2. CHIP DESIGN The chief constraints in the design of the chip were: 1. A process compatible with both Nb and NbN. 2. Freedom from tight dimensional tolerances. 3. Only one resistor metallization. 4. No planarization. 5. Minimum parasitic capacitance and inductance. The desire to establish a fabrication procedure that was compatible with NbN eliminated the option of wet anodization to define the junction area, i.e., the SNAP process was ruled out. Instead, reactive ion etching of the counter electrode was employed. The desire to establish a fabrication procedure that was compatible with NbN eliminated the option of wet anodization to define the junction area, i.e., the SNAP process was ruled out. Instead, reactive ion etching of the counter electrode was employed. SPICE simulations show that a shift register capable of operating at 25 GHz requires a Josephson critical current density of about 2 A /cm2. However, NbN technology is not advanced enough to make reproducible Josephson junctions at this current density.' Hence, Nb /A1 /Nb Josephson junctions were planned for the first circuits, with an eventual switch to NbN,, when that technology matures. SPICE simulations show that a shift register capable of operating at 25 GHz requires a Josephson critical current density of about 2 A/cm2. However, NbN technology is not advanced enough to make reproducible Josephson junctions at this current density. 6 Hence, Nb/AlO /Nb Josephson junctions were planned for the first circuits, with an eventual switch to NbN, when that technology matures. The unit cell shown in Figure 4 made use of several techniques to minimize sensitivity to lithography errors. The proper operation of the DCL OR -gate requires junction J2 to have twice the critical current of junction J1. The mask contained three 5 /m size Josephson junctions and connected two of them together into a single junction. Thus, if the fabricated junctions contained an error in the junction diameter, the requirement of 2:1 critical current ratio would still be satisfied. Similarly, the DCL design calls for a resistance ratio of 2:1 between resistors R :R2. The mask design thus contained three identical resistors with two of them conneced in parallel. This approach guarded against errors in the length to width ratio of fabricated resistors and against contact resistance problems. The unit cell shown in Figure 4 made use of several techniques to minimize sensitivity to lithography errors. The proper operation of the DCL OR-gate requires junction J2 to have twice the critical current of junction J x. The mask contained three 5 pm size Josephson junctions and connected two of them together into a single junction. Thus, if the fabricated junctions contained an error in the junction diameter, the requirement of 2:1 critical current ratio would still be satisfied. Similarly, the DCL design calls for a resistance ratio of 2:1 between resistors R :Ra. The mask design thus contained three identical resistors with two of them connected in parallel. This approach guarded against errors in the length to width ratio of fabricated resistors and against contact resistance problems. 82 / SPIE Vol. 879 Sensing, Discrimination, & Signal Processing & Superconducting Materials & Instrumentation (1988) 82 / SPIE Vol. 879 Sensing, Discrimination, & Signal Processing & Superconducting Materials & Instrumentation (1988)

3 The fabrication of reproducible refractory metal resistors is a significant challenge for superconductor integrated circuits. It was desired to begin to meet this challenge with a single resistor level, if possible. The unit cell of the DCL OR -gate required a.3 ohm resistor and a 1.2 ohm resistor. These were provided in the design by a metallization with a sheet resistance of.6 ohm per square and length to width ratios of.5 square and 2 squares. The resistivity of bulk molybdenum is 18 µohm -cm at 4.2 Kelvin, so a film thickness of 3 A would provide the required sheet resistance. The fabrication of reproducible refractory metal resistors is a significant challenge for superconductor integrated circuits. It was desired to begin to meet this challenge with a single resistor level, if possible. The unit cell of the DCL OR-gate required a.3 ohm resistor and a 1.2 ohm resistor. These were provided in the design by a metallization with a sheet resistance of.6 ohm per square and length to width ratios of.5 square and 2 squares. The resistivity of bulk molybdenum is 18 /Johm-cm at 4.2 Kelvin, so a film thickness of 3 A would provide the required sheet resistance. Difficulties arose in the attempts to implement the 2 ohm gate resistors in this single resistor level. With a 5 µm linewidth, the resistors would have to be more than 1.6 mm long. Furthermore, if a ground plane were incorporated to prevent crosstalk between adjacent phases, then the resistors would look like resistive transmission lines at microwave frequencies. It was not possible to treat the 2 ohm resistors as lumped elements. Instead, the computer program SUPERCOMPACT was employed to model the gate resistors as distributed elements. Difficulties arose in the attempts to implement the 2 ohm gate resistors in this single resistor level. With a 5 /im linewidth, the resistors would have to be more than 1.6 mm long. Furthermore, if a ground plane were incorporated to prevent crosstalk between adjacent phases, then the resistors would look like resistive transmission lines at microwave frequencies. It was not possible to treat the 2 ohm resistors as lumped elements. Instead, the computer program SUPERCOMPACT was employed7 to model the gate resistors as distributed elements. Treating the gate resistors as long, thin film resistors, the modeling program showed that it was possible to reduce the gate resistor values to only 3 ohms for a four -stage shift register design. This ensured that the bias current to the first gate would vary by no more than 4% when the shift register state went from the "1 " (lowest current) state to the " 1 1 1" (highest current) state. Treating the gate resistors as long, thin film resistors, the modeling program showed that it was possible to reduce the gate resistor values to only 3 ohms for a four-stage shift register design. This ensured that the bias current to the first gate would vary by no more than 4% when the shift register state went from the "1 " (lowest current) state to the " 1 1 1" (highest current) state. The SUPERCOMPACT modeling also showed that the center -fed buss bar arrangement of Figure 5 could maintain phase coherence between the center gates and the end gates of the shift register. At 1 GHz, all gates in the same phase were coherent to within 2 degrees. The SUPERCOMPACT modeling also showed that the center-fed buss bar arrangement of Figure 5 could maintain phase coherence between the center gates and the end gates of the shift register. At 1 GHz, all gates in the same phase were coherent to within 2 degrees. 4 SHIFT REGISTER CIRCUIT STRUCTURE. SHIFT REGISTER CIRCUIT STRUCTURE \ \\l *-1Ii Á Ï,... : %:C:`rd-+:\\Q, '.,:A ll wwv\ X w^ Hi Y:'11::!:eii!ir?tfQoO:v.4S-6.6:::eWdiPrwt"w:Jiiì! Br la Nb Mo OSIOZ SI 3 Mo DSIO, Si Figure 5. Layout of the twelve-gate four- Figure 6. stage shift register, showing the three clock inputs. Each clock phase was connected to the center of a superconducting transmission line that supplied power to four gate resistors. Orthogonal lines were on different levels to prevent shorts. Figure 5. Layout of the twelve -gate four - stage shift register, showing the three clock inputs. Each clock phase was connected to the center of a superconducting transmission line that supplied power to four gate resistors. Orthogonal lines were on different levels to prevent shorts. Figure 6. Cross section of the shift register circuit schematic. Cross section of the shift register circuit schematic. Complex circuits with a high level of integration usually require planarization processes to maintain yields. However, the present four -stage, twelve -gate shift register circuit can probably be fabricated without planarization. It was desirable to short cut the time to develop the planarization steps and to simplify the circuit processing by avoiding planarization in the first chips. The circuit implementation used thin layers of metals and insulators as much as possible, as shown in Table 1. Thin layers facilitated step coverage, eliminating the need for planarization. In addition, they reduced the total stress in the sputtered films, since stress is proportional to film thickness.8 Complex circuits with a high level of integration usually require planarization processes to maintain yields. However, the present four-stage, twelve-gate shift register circuit can probably be fabricated without planarization. It was desirable to short cut ~~ _. layers step coverage, eliminating the need for planarization. In addition, they reduced the total stress in the sputtered films, since stress is proportional to film thickness. 8 The SPICE modeling of circuit performance took no account of parasitic capacitance or inductance, so it was essential to minimize these effects in the circuit layout. The unit cell of the DCL OR -gate was made as small as possible to treat the circuit components as lumped elements, as shown in Figure 4. Furthermore, the layout included a ground plane to minimize parasitic inductance in the interconnections. The SPICE modeling of circuit performance took no account of parasitic capacitance or inductance, so it was essential to minimize these effects in the circuit layout. The unit cell of the DCL OR-gate was made as small as possible to treat the circuit components as lumped elements, as shown in Figure 4. Furthermore, the layout included a ground plane to minimize parasitic inductance in the interconnections. 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4 Table Circuit levels levels used to fabricate the shift register chip CIRCUIT LEVELS Mask Level Ground Plane Insulator Base Electrode Counter Electrode Insulator Interconnects Resistors Contact Contact. Pads Material SiO SiO SiOa Molybdenum Gold Thickness 2 AA 2 AI 2 A 1 AI I 2 A 2 A1 3 A 1 A I A cross section of of the the circuit circuit structure structure is is shown shown in in Figure Figure Circuits were fabricated fabricated substrates, with aa 2 on silicon silicon substrates, 2 A buffer layer layer of of silicon silicon dioxide. dioxide. Each of the the first first seven seven layers layers was deposited by sputtering sputtering and and patterned patterned by by reactive reactive ion ion etching. etching. The eighth eighth mask level level provided a gold coating for for the the contact contact pads edge of chip. Only the pads at at the the edge of the chip. patterned by by liftoff. liftoff. gold was patterned The the mm mm chip chip is is shown shown in in Figure Figure At the the bottom of of the the chip, chip, there there The layout of the -gate with with two two contacts contacts to to each of the four was a single DCL DCL OR OR-gate four circuit circuit nodes. nodes. This permitted a four four-point -point probe probe measurement measurement of of every every individual individual resistor resistor and and Josephson Josephson junction in in a gate, gate, to verify that they junction they had had been been fabricated fabricated correctly. correctly. Shift Register Chip Layout Figure Layout of the the mm mm square square chip. chip. Significant features from top to bottom (1) (1) three-gate three -gate single-stage single -stageshift shiftregister, register, (2) (2) 5 5 ohm ohm coplanar coplanar waveguide waveguide were: feedthrough, (3) (3) mask mask alignment alignment marks, marks, (4) (4) twelve twelve-gate -gate four four-stage -stage shift shift register, (5) single s ing1e gate. gate. register, and (5) top of o f the th e chip, ch i p,, there th e r e was was a athree threegat e, single s i ng 1 e --stage s t age shift s h i f t register. r e g i s t e r, There Th e :r e was At the top -gate, connection, plus plus output output connections connections from from each each gate, gate, to to verify verify the the proper proper an input input connection, the circuit. circuit, functioning of the Ju s t above abov e the alignment ali gnme nt patterns, p atte rn s, there the r e was was aa 5 5-ohm cop1anar waveguide wav egu i de feedthrough, fee dthrough, Just -ohm coplanar -speed testing of of the the side of the other. other. This could be be used used for for high high-speed from one one side of the chip to the cryogenic chip cryogenic chip probe, probe, or or to to provide provide aa synchronization synchronization signal signal for for sampling scope scope measurements. / SPIEVol Vol Sensing, Sensing,Discrimination, Discrimination,&&Signal SignalProcessing Processing&& Superconducting Superconducting Materials Materials & & Instrumentation Instrumentation(1988) (1988) 84 / SPIE

5 In the center of the chip, there was a twelve-gate, four-stage shift register. The high-speed data input and data output were on the left side. The high-speed connections for the three clock phases were on the right side. In the center of the chip, there was a twelve -gate, four -stage shift register. The high -speed data input and data output were on the left side. The high -speed connections for the three clock phases were on the right side. 3. FABRICATION 3. FABRICATION The first attempts to fabricate the shift register revealed several challenges to be overcome. Some difficulties related directly to the reactive ion etching: (1) lack of adequate etch selectivity, (2) failure to remove etch stop material, and (3) formation of polymer deposits during etching. Another problem was merely coincident with the etching: peeling of films after etching. The first attempts to fabricate the shift register revealed several challenges to be overcome. Some difficulties related directly to the reactive ion etching: (1) lack of adequate etch selectivity, (2) failure to remove etch stop material, and (3) formation of polymer deposits during etching. Another problem was merely coincident with the etching: peeling of films after etching. Since all the layers were first deposited on the entire wafer and then patterned by etching away unwanted material, it was necessary to have high etch rates for the layer being etched and low etch rates for the underlayers that were eventually exposed during the etch. When the reactive ion etch of the molybdenum film in CF4 + 2 exposed the niobium film underneath, there was too much etching of the niobium. In some cases, the niobium interconnections were destroyed. Since all the layers were first deposited on the entire wafer and then patterned by etching away unwanted material, it was necessary to have high etch rates for the layer being etched and low etch rates for the underlayers that were eventually exposed during the etch. When the reactive ion etch of the molybdenum film in CF4 + 2 exposed the niobium film underneath, there was too much etching of the niobium. In some cases, the niobium interconnections were destroyed. The CC1 2 F 2 gas that was used to etch the niobium would also etch the underlayers of Si 2, so an etch stop layer of thin aluminum was deposited between them. This was very effective in protecting the Si 2. Unfortunately, it was difficult to removed this etch stop layer. A thin metallic layer could be left on the wafer, which shorted out parts of the circuit. The CC12F2 gas that was used to etch the niobium would also etch the underlayers of SiO2, so an etch stop layer of thin aluminum was deposited between them. This was very effective in protecting the Si2. Unfortunately, it was difficult to removed this etch stop layer. A thin metallic layer could be left on the wafer, which shorted out parts of the circuit. When CC1 2F 2 reacted with the aluminum/niobium interface and the photoresist, there was a tendency to form a layer of organic polymer as a reaction product. This polymer degraded the adhesion of subsequent depositions, so that they would sometimes peel off. When CC12F2 reacted with the aluminum /niobium interface and the photoresist, there was a tendency to form a layer of organic polymer as a reaction product. This polymer degraded the adhesion of subsequent depositions, so that they would sometimes peel off. The Nb/AlO /Nb trilayers that were used to form the Josephson junctions were sputter deposited at Tow argon pressure, which has been shown to produce compressive stress in the films. 8 ' 9 The subsequent reactive ion etching of the trilayer produced a gradual peeling of the trilayer. This peeling continued over several days and generated particles that interfered with photolithographic patterning of subsequent layers. The Nb /A1 /Nb trilayers that were used to form the Josephson junctions were sputter deposited at fow argon pressure, which has been shown to produce compressive stress in the films.8'9 The subsequent reactive ion etching of the trilayer produced a gradual peeling of the trilayer. This peeling continued over several days and generated particles that interfered with photolithographic patterning of subsequent layers. These processing problems have prevented any attempt to verify the operation of the shift register circuit. These processing problems have prevented any attempt to verify the operation of the shift register circuit. 4. DISCUSSION 4. DISCUSSION The SPICE simulations treated the circuit components as discrete, lumped elements. In the actual layout, they became distributed elements. The SPICE design called for 2 ohm gate resistors. But the desire to start with only one resistor metallization level made it impractical to fabricate such large resistors. Instead, the SUPERCOMPACT modeling showed that 3 ohm gate resistors should suffice for a four-stage shift register. Large gate resistors provide equal sharing of the clock current between gates in different logic states. In the present design, current uniformity is expected to be within ±2%, which is well within the usual gate bias margin of ±44% for the DCL OR-gate. The SPICE simulations treated the circuit components as discrete, lumped elements. In the actual layout, they became distributed elements. The SPICE design called for 2 ohm gate resistors. But the desire to start with only one resistor metallization level made it impractical to fabricate such large resistors. Instead, the SUPERCOMPACT modeling showed that 3 ohm gate resistors should suffice for a four -stage shift register. Large gate resistors provide equal sharing of the clock current between gates in different logic states. In the present design, current uniformity is expected to be within *2 %, which is well within the usual gate bias margin of *44% for the DCL OR -gate. On the chip, the gate resistors did not meet at a common point. This caused phase shifts along the transmission lines that distributed the bias currents to the various gates. The 25 GHz simulations suggested that significant problems would not occur until neighboring gates went out of synchronization by one picosecond. At 1 GHz, one picosecond corresponds to 3.6 degrees. The SUPERCOMPACT modeling showed that the gates should be in phase to within 2 degrees at 1 GHz. On the chip, the gate resistors did not meet at a common point. This caused phase shifts along the transmission lines that distributed the bias currents to the various gates. The 25 GHz simulations suggested that significant problems would not occur until neighboring gates went out of synchronization by one picosecond. At 1 GHz, one picosecond corresponds to 3.6 degrees. The SUPERCOMPACT modeling showed that the gates should be in phase to within 2 degrees at 1 GHz. Some parasitics were present in the chip layout that were not modeled by the SPICE simulations. The largest capacitive parasitic was the electrode to ground capacitance of the node where the gate resistor met J ± and R. The size of this capacitance is approximately one half of the junction capacitance of J.. The time needed to charge this node may increase the switching time of Josephson junction J^ by 5%. One may estimate a consequent reduction in speed of the gate to 16 GHz. Some parasitics were present in the chip layout that were not modeled by the SPICE simulations. The largest capacitive parasitic was the electrode to ground capacitance of the node where the gate resistor met J1 and R,. The size of this capacitance is approximately one half of the junction capacitance of J. The time needed to charge this node may increase the switching time of Josephson junction J1 by 5%. One may estimate a consequent reduction in speed of the gate to 16 GHz. Parasitic inductance may be more of a problem for the chip reported here. The long arm of the electrode at this same node may contribute about 1.5 ph of parasitic inductance. At 1 GHz, that corresponds to about.1 ohm of inductive impedance. Since the bias current is divided by resistors with values of.3 and.15 ohm, there is a possibility that it will not be distributed to the junctions in the proper 2:1 ratio. Parasitic inductance may be more of a problem for the chip reported here. The long arm of the electrode at this same node may contribute about 1.5 ph of parasitic inductance. At 1 GHz, that corresponds to about.1 ohm of inductive impedance. Since the bias current is divided by resistors with values of.3 and.15 ohm, there is a possibility that it will not be distributed to the junctions in the proper 2:1 ratio. This parasitic inductance problem may be overcome in future chips by the use of finer line lithography. Resistor values scale inversely with critical current to keep a constant This parasitic inductance problem may be overcome in future chips by the use of finer line lithography. Resistor values scale inversely with critical current to keep a constant SP/E Vol 879 Sensing, Discrimination, & Signal Processing & Superconducting Materials & Instrumentation (1988) / 85 SPIE Vol. 879 Sensing, Discrimination, & Signal Processing & Superconducting Materials & Instrumentation (1988) / 85

6 IR product. So smaller junctions would require larger resistors. Thus the ratio of parasitic inductive impedance to designed resistive impedance would diminish. Smaller Josephson junctions would have the added advantage of reducing the total rf power required to operate the circuit. The difficulties encountered in processing the chips represented inconveniences, rather than fundamental obstacles. Work is already in progress to develop a more reliable process. Etch stop layers are being incorporated to prevent unwanted etching of underlayers. Processes have been developed to remove or to oxidize any metallic etch stop residues. Chemical removal by wet or dry etching is preferable to oxidation, because of the possibility of microwave losses in metal oxide films. Polymer formation in reactive ion etching has been controlled by the addition of oxygen to the plasma. This has the added advantage of producing a sloped edge on the etched layer, which facilitates step coverage and ameliorates any problems from the lack of planarization. Peeling of sputtered films is being controlled by adjustments of the sputtering gas pressure to produce stress-free films. In summary, SPICE simulations show that 25 GHz shift register performance lies within the capabilities of modern Josephson LSI technologies. The chip layout presented here was a first step toward the realization of that promise. In particular, the microwave inputs to provide power to the chip modeled proper performance up to 1 GHz. Processing techniques have been established to fabricate the first chips containing a a four-stage shift register. 4. ACKNOWLEDGEMENT This work was sponsored by by AF AF Contract F C-158 -C -158 with RADC funded by SDIO/IST. 5. REFERENCES 1. John X. Przybysz and R. D. Blaugher, "Josephson Shift Register for High-Speed Serial Memory," Extended Abstracts of the 1987 International Superconductivity Electronics Conference, pp , Tokyo, Japan. 2. R. E. Jewett, "Josephson Junctions in SPICE 2G5," published at Electronics Research Lab, U. Cal. Berkeley, December 2, A. Vladimirescu, Kaihe Zhang, A. R. Newton, D. O.. Pederson, A. Sangiovanni-Vincentelli, "SPICE Version 2G User's Guide," published at Department of Electrical Engineering and Computer Sciences, U. Cal. Berkeley, August 1, T. R. Gheewala and A. Mukherjee, "Josephson Direct Coupled Logic(DCL)," IEDM Tech. Dig., pp (Washington, DC, December 33-4, 1979). 5. S. Kotani, N. Fujimaki, S. Morohashi, S. Ohara, T. Imamura, and S. Hasuo, "High-Speed Unit-Cell for Josephson LSI Circuits using Nb/AlO /AlOx/Nb /Nb Junctions," IEEE Trans. on Magnetics, Vol. Mag-23, No. 2, pp , March x 6. A. Shoji, M. Aoyagi, S. Kosaka, and F. Shinoka, "Temperature-Dependent Properties of Nitride Josephson Tunnel Junctions," IEEE Trans. on Magnetics, Vol. Mag-23, No. 2, pp , March, SUPERCOMPACT is available from Compact Software, 483 McLean Boulevard and 18th Avenue, Paterson, NJ 754, (21) D. W. Hoffman, and John A. Thornton, "The Compressive Stress Transition in Al, V, Zr, Nb, and W Metal Films Sputtered at Low Working Pressures," Thin Solid Films, Vol. 45, pp , C. T. Wu, "Intrinsic Stress of Magnetron-Sputtered Films," Thin Solid Films, Vol. 64, pp , / / SPIE Vol. 879 Sensing, Discrimination, & Signal Processing & Superconducting Materials & Instrumentation (1988)