From Bulk Gallium Nitride Material to Vertical GaN Devices

Transcription

1 From Bulk Gallium Nitride Material to Vertical GaN Devices Thomas Mikolajick 1,2, Stefan Schmult 2, Rico Hentschel 1, Patrick Hofmann 1, and Andre Wachowiak 1 1 NaMLab ggmbh 2 Chair of Nanoelectronic Materials, TU Dresden

2 Outline o Introduction GaN o GaN HVPE material Doping o GaN Vertical Device Trench gate MOSFET

3 Introduction GaN

4 c-axis GaN material properties III-V compound semiconductor Hexagonal crystal lattice Direct semiconductor Wide bandgap ~3.4 ev high breakdown E-field strength High mobility 2DEG at GaN/AlGaN Ga-face Ga N heterostructure interface EVBM ECBM p-gan MQW n-gan

5 Application of GaN Semiconductors OPTO - ELECTRONICS ELECTRONICS Laser Diodes LED Power Devices RF electronic systems industry projection car lighting power supply power management power amplifier RF communications PV converter electric vehicle hybrid electric vehicle

6 GaN for power devices Properties Si / SiC / GaN Melting point [x 1000 C] Area specific R on vs. Breakdown Voltage Stephen Sque (NXP) ESSDERC tutorial (2013) Band gap [ev] Electron sat. velocity [x 10 7 cm/s] Breakdown field E crit [MV/cm] GaN Levers: Electron mobility [x 1000 cm 2 /Vs] Superior bulk properties for power applications: E crit, µ, E gap Higher temperature operation possible HEMT device concept Advantages of GaN Low on-state resistance at given voltage rating - compact high voltage devices - fast efficient switching Benefits on system level: - more efficient energy conversion - smaller inductors - smaller and low weighted converter systems energy saving / innovative systems

7 GaN Material MOCVD hetero-epitaxy on host substrate Example HEMT structure on Si (111) Homo-epitaxy of functional device layers on GaN substrate MOCVD (MBE) Layer stack dependent on device n+ GaN wafer Advantage: Low cost for large diameter: up to 200mm available Device processing in standard silicon fabs Challenge: large lattice and thermal expansion mismatch to Si Core IP in complex strain management buffer Semi-Insulating properties by compensation of residual n-type doping (N-vac.,O) with C, Fe,.. Dislocation density in top layers: 1E8 5E8 cm -2 Alternative Substrates: Sapphire, SiC ~ 150 mm Advantage: No lattice and thermal expansion mismatch Low dislocation density of substrate < 3E6 cm -2 Challenge / Requirements: high-quality regrowth without defect generation Freestanding GaN substrate wafer by HVPE growth wafer size 2-4 Chemical-mechanical polished substrate surface Doping of GaN substrate wafer

8 GaN HVPE material

9 GaN HVPE HVPE: Hydride Vapour Phase Epitaxy: Growth on GaN/Sapphire Template Growth thickness: several 100 µm 1 cm Growth rate: ~ µm/h Growth Temp.: C Dislocation density: 2E6 cm -2 Low residual dopant conc. (uid): 1E16 cm -3 NaMLab s vertical HVPE Reactor

10 Doping GaN Doping during growth Introduction of dopant to the growth atmosphere Post growth doping Ion implant lattice damage High temp. anneal necessary for pgan: Mg (>1300 C) material decomposition w/o cap Diffusion Small diffusion constants for Si and Mg reported n-type GaN Optoelectronic, sensory, power application Main dopants: Si Ga, Ge Ga, (O N ) Semi-insulating GaN device, sensory applications Main dopants: Fe Ga, Mn Ga, C p-type GaN (MOCVD) Optoelectronic, power application Dopant: Mg Ga GaN:Si GaN:Ge GaN:Fe GaN:Mn

11 Si-Doping n-type 2 GaN Boule Si Si Ga, E D = mev HVPE: dichlorosilane, thermal stability Reduction of threading dislocation prior Si doping to avoid tensile stress generation HVPE GaN:Si samples n e ~2* *10 19 cm -3 Linear dependency of charge carriers on eff. DCS flow x-section Local strain analyses by Raman spectroscopy using E 2 high mode GaN:Si ~2E18 cm -3 un-intentionally doped-gan Dichloro- Silane (DCS) T. Mikolajick Patrick Hofmann et al J. Phys. D: Appl. Phys (2016)

12 Ge doping n-type n-type doping without tensile stress generation Vapour phase dopant smaller incorporation efficiency Solid State Doping line Doping flux SIMS 2.6 rpmsample 3 1E21 1E21 1E20 Sample 2 1E19 1E18 1E19 Sample 1 1E rpm 1E17 Sample 3 Sample 2 Sample 1 Hall SIMS 1E17 1E16 1E HCl flow [sccm] Sputter depth [mm] T. Mikolajick Patrick Hofmann et al. J. Cryst. Growth (2016) Concentration [cm-3] Concentration [cm-3] 1E20

13 Pyroelectricity of semi-insulating GaN Change of spontaneous polarization due to change in temperature PS = p T I(t) T(t) Measure current with electrodes on c plane surfaces GaN:Fe / GaN:Mn / GaN:C Dependence of pyroeletric effect on c-lattice constant: Spontaneous polarization function of lattice constant and different dopants change c-lattice constant differently T. Mikolajick Sven Jachalke et al. Appl. Phys. Lett. 109, (2016)

14 GaN vertical device

15 GaN for power switches V BD 2 R ON A = μe C 3 ε/4 = C mat highest for GaN ON I SD I max min R ON Source Gate Drain Area specific R on vs. Breakdown Voltage Stephen Sque (NXP) ESSDERC tutorial (2013) fast switching by gate V I 0 Power Loss Efficiency < 1 OFF V SD min. I Leak V BD Performance Targets Min. On-Resistance (R ON ) Max. Break-Down Voltage V BD Fast Switching w/o Transients Small Device Area / Large Wafer low cost Advantages of GaN Low on-state resistance at given voltage rating - compact high voltage devices - fast efficient switching Benefits on system level: - more efficient energy conversion - smaller inductors - smaller and low weighted converter systems energy saving / innovative systems

16 Lateral GaN HEMT HEMT = High electron mobility transistor Vertical GaN Transistor Example: Trench MOSFET Gate-Drain distance defines VBD Source Gate Source Gate Passivation Drain HV n(+) n(+) p 2DEG AlGaN GaN e - Strain management (AlGaN/GaN) buffer Compensated (C,Fe..) Substrate Si(111) n(-) GaN drift n(+) GaN Substrate Drain: HV Pros - High mobility 2DEG - large GaN-Si epi wafer up to 200 mm Advantages - area efficient scaling of breakdown voltage with drift layer thickness (> 1 kv) - separation HV / isolation, less surface effects - GaN substrates dislocations density < 3E6 cm -2 Cons - Less area efficient for high voltages - Vertical buffer breakdown / trapping - Higher dislocation density > 1E8 cm -2 Con - Costly GaN substrates / Wafer size 2-4

17 Vertical transistor device concepts in GaN Examples Trench MOSFET Slanted HEMT p-gan Gate MOS Fin Tower + high V th > 3V - Lower channel mobility Ch. Gupta et al. IEEE EDL (2016) 37 p1601 Ray Li et al. IEEE EDL (2016) 37 p1466 Tohru Oka et al. APEX (2015) 8 p V th = 2.5 V + high channel mobility - Complex integration Daisuke Shibata et al. IEDM (2016) + no p-gan used + low Ron - V th ~ 1V for fins < 500nm Min Sun et al. IEEE EDL (2017) 48, p509 Pics from Jie Hu et al. Mat. Sci. Semi. Processing (2017)

18 Pseudo-vertical MOSFET device (Low volt.) (High volt.) True vertical MOSFET S e - G D S n + GaN p GaN n - GaN n + GaN separated high and low voltage terminals area efficient scaling of breakdown voltage with drift layer thickness normally-off operation n + /p/n - layer stack on freestanding GaN needed Pseudo-vertical MOSFET better GaN material availability Limitations in RON and VBD n - GaN thickness, TDD, top-sided Drain process and characterization well transferable to true vertical devices G S B D n + GaN p GaN n - GaN n + GaN Sapphire suitable test vehicle for technology setup

19 Pseudo vertical layer stack 5 4 5,0 n + GaN : Si p GaN : Mg 200 nm 500 nm Dislocation examples 3 2 4,0 n - GaN : Si n + GaN : Si 1000 nm 3500 nm R RMS = 0.4 nm 3,0 Sapphire substrate 300 µm 4 2,0 prior to MBE overgrowth: H out-diffusion anneal Benefits of MBE for n+ GaN regrowth Hydrogen free environment for PA-MBE Lower growth temperature ( C) High quality regrowth: dislocation density n+ surface ~ Dislocation examples R RMS = 0.3 nm (nm) 1, cm -2 as on p GaN surface (µm) Atomic force microscope images

20 Device integration Growth & p-gan: Mg activation Insulation / pseudo vert. etch Ohmic contacts to n GaN (Ti/Al) Upper n + GaN etch Ohmic contacts to p GaN (Ni/Au) Gate trench etch (dry & wet) Gate dielectric deposition (ALD-Al 2 O 3 ) Gate TiN Source Body Drain Ti/Al Al 2 O 3 n + GaN p GaN n - GaN Ni/Au Ti/Al n + GaN Sapphire Gate metal deposition & structuring (ALD-TiN) Passivation (ALD-Al 2 O 3 ) processed 2 wafer contact lithography TiN Al 2 O 3 GaN 200 nm R. Hentschel et al. at ASDAM 2016

21 Device characteristics Transfer characteristic = 5 V R. Hentschel et al. at ASDAM 2016 G S B D V GS 0V 0V V DS n + GaN p GaN n - GaN n + GaN expected output control with increasing gate overdrive withv th ~5 V I D (V DS ) scaling but weak output saturation Drain Curr. Density I D (ma/mm) Sapphire Output characteristics V GS = 7 V to 12 V, 1 V step Drain-Source Voltage V DS (V) Well controllable normally-off operation

22 Body bias method: measure p-gan:mg activation Transfer V BS G S B D V GS 0V V BS 0.1V n + -GaN p -GaN n - -GaN n + -GaN Sapphire Many Mg-sites hydrogen passivated p-gan:mg deep acceptor level ~ 0.18 ev reduced hole conc. in equilibrium at RT Substrate control allows estimation of apparent hydrogen-free Mg acceptor sites V th = Φ MS Q eff C ox + 2ϕ F + 2qϵ GaNN A x ( 2ϕF U BS ) C ox estimated concentration N A- = cm -3 (SIMS: N Mg = cm -3 ) R. Hentschel et al. at ASDAM 2016

23 vertical GaN transistor benchmark Vertical GaN transistors beyond area specific R ON vs. Breakdown Voltage lateral GaN HEMT Different device concepts with different strength (V TH, R ON, V BD ) L lateral HEMT [3] Fin tower MOSFET V TH =1V [1] Trench MOSFET vertical [2] slanted HEMT p-gan Gate [1] T. Oka et al. APEX 8, p (2015) [2] Daisuke Shibata et al. IEDM (2016) [3] Min Sun et al. IEEE EDL 48, p509 (2017) Graph by part from Daisuke Shibata et al. IEDM (2016) T. Mikolajick

24 Summary and outlook o o o HVPE growth currently most productive technology for GaN wafer n-type doping opens door for vertical power devices Promising performance indicators of vertical GaN devices (main competitor SiC MOSFET) o Further understanding of interaction between material and device important to foster vertical GaN power technology o Reliability to be demonstrated on large device count o o Influence of defect density and different types on yield Availability and cost development of larger GaN wafer (100mm and above) important for decision on manufacturing

25 Thank you for your kind attention!!! Thanks to: Martin Krupinski Nadine Szábo Felix Schubert Cooperation: Acknowledgement: This work was financially supported by the European Fund for regional Development EFRD, the Free State of Saxony, Europe supports Saxony and the German Federal Ministry of Education und Research BMBF