IN THE UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD

Transcription

1 IN THE UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD SAMSUNG DISPLAY CO., LTD., TOSHIBA CORPORATION, AND FUNAI ELECTRIC CO., LTD, Petitioners, v. GOLD CHARM LIMITED Patent Owner. Case No. To Be Assigned Patent No. 5,966,589 PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 5,966,589 UNDER 35 U.S.C AND 37 C.F.R et seq.

2 TABLE OF CONTENTS I. Mandatory Notices (37 C.F.R. 42.8(a)(1))... 1 A. Real Party-In-Interest (37 C.F.R. 42.8(b)(1))... 1 B. Related Matters (37 C.F.R. 42.8(b)(2))... 1 C. Lead and Backup Counsel (37 C.F.R. 42.8(b)(3))... 2 D. Service Information (37 C.F.R. 42.8(b)(4))... 2 II. Fees (37 C.F.R )... 3 III. Requirements for Inter Partes Review Under 37 C.F.R A. Grounds for Standing (37 C.F.R (a))... 3 B. Citation of Prior Art... 3 C. Claims and Statutory Grounds (37 C.F.R (b)(1) & (b)(2))... 4 IV. The 589 Patent... 5 A. Overview of the 589 Patent... 5 B. Prosecution History Summary Of The 589 Patent... 8 C. Person of Ordinary Skill in the Art... 9 D. Claim Construction (37 C.F.R (b)(3)) operative semiconductor in facing relation where above said drain and source electrodes E. Unpatentability of the Construed Claims (37 C.F.R (b)(4)) F. Supporting Evidence (37 C.F.R (b)(5)) i -

3 V. There is a Reasonable Likelihood that Petitioner Will Prevail With Respect to at Least One Claim of the 589 Patent A. Prior Art Takizawa (Ex. 1003) Hoshino (Exs and 1005) Shin (Ex. 1006) B. Ground I: Claims 1 and 3-6 Are Invalid Under 35 U.S.C. 102(b) As Anticipated By Takizawa C. Ground II: Claim 2 Is Invalid Under 35 U.S.C. 103 As Obvious Over Takizawa In View Of Hoshino D. Ground III: Claims 1 And 4-6 Are Invalid Under 35 U.S.C. 102(e) As Anticipated By Shin E. Ground IV: Claim 2 Is Invalid Under 35 U.S.C. 103 As Obvious Over Shin In View Of Hoshino F. Ground V: Claim 3 Is Invalid Under 35 U.S.C. 103 As Obvious Over Shin In View Of Takizawa G. Ground VI: Claims 1-4 And 6 Are Invalid Under 35 U.S.C. 102(b) As Anticipated By Hoshino VI. CONCLUSION ii -

4 Exhibit Ex Description LIST OF EXHIBITS U.S. Patent No. 5,966,589 (the 589 Patent ) Ex File History for U.S. Patent No. 5,966,589 Ex U.S. Patent No. 5,483,082 ( Takizawa ) Ex Japanese Patent Application Publication H Ex Ex Ex Ex Ex Ex Ex Ex Ex Certified English Translation of Japanese Patent Application Publication H ( Hoshino ) U.S. Patent No. 5,825,449 ( Shin ) N. Ibaraki et al., A new a-si TFT with SiO 2 /SiN x gate insulator for 10.4-inch LCDs, Conference Record of the International Display Research Conference, pp , Oct , 1991 ( Ibaraki ) K. Hiranaka, T. Yamaguchi, Amorphous Silicon Thin-Film Transistors with SiO x N y /SiN x Gate Insulators, 29(2) Japanese J. Appl. Phys (Feb. 1990) ( Hiranaka ) H. Morimoto, (Invited) Current Progress in Manufacturing Process Technologies and Equipment for AMLCDs, Proceedings of the 12th International Display Research Conference, pp , Oct , 1992 ( Morimoto ) U.S. Patent No. 5,478,766 ( Park ) Disclaimer in Patent Under 37 C.F.R 1.321(a) Declaration of Dr. Anne Chiang Curriculum vitae of Dr. Anne Chiang - iii -

5 U.S. Patent No. 5,966,589 ( the 589 Patent ) purports to innovate over the prior art by combining two photolithography steps that form through-holes in a thinfilm transistor ( TFT ) array into one, thus achieving a five-step TFT fabrication process. But prior art not described in the specification and not previously considered by the PTO teaches TFT fabrication using five or even fewer steps, including the use of a single step for forming through-holes. Claims of the 589 Patent should be cancelled because they recite nothing more than prior art methods. I. MANDATORY NOTICES (37 C.F.R. 42.8(A)(1)) A. Real Party-In-Interest (37 C.F.R. 42.8(b)(1)) The petitioners are Samsung Display Co., Ltd.; Toshiba Corporation; and Funai Electric Co., Ltd. ( Petitioners ). The real parties in interest in addition to the Petitioners are: Toshiba America, Inc.; Toshiba America Information Systems, Inc.; Funai Corporation Inc.; and P&F USA Inc. B. Related Matters (37 C.F.R. 42.8(b)(2)) The 589 Patent is currently the subject of litigation against multiple defendants in the District of Delaware, captioned MiiCs & Partners, America, Inc. and Gold Charm Limited v. Toshiba Corporation, Toshiba America, Inc. and Toshiba America Information Systems, Inc. (Civil Action No. 1:14-cv RGA); 1 Petitioner does not seek cancellation of Claim 1, even though it is also invalid, because Patent Owner Gold Charm disclaimed Claim 1 under 37 C.F.R (a)

6 MiiCs & Partners, America, Inc. and Gold Charm Limited v. Funai Electric Co., Ltd., P&F USA, Inc. and Funai Corporation, Inc. (Civil Action No. 1:14-cv RGA); and MiiCs & Partners, America, Inc. and Gold Charm Limited v. Mitsubishi Electric Corporation, Mitsubishi Electric U.S. Holdings, Inc., Mitsubishi Electric U.S., Inc. and Mitsubishi Electric Visual Solutions America, Inc. (Civil Action No. 1:14-cv RGA). C. Lead and Backup Counsel (37 C.F.R. 42.8(b)(3)) Lead counsel is Jay I. Alexander (Reg. No. 32,678); T: (202) ; F: (202) ; E: Back-up counsel are Andrea G. Reister (Reg. No. 36,253) T: (202) ; F: (202) ; E: and Gregory S. Discher (Reg. No. 42,488) T: (202) ; F: (202) ; E: The postal address for the foregoing counsel is: Covington & Burling LLP, One CityCenter, 850 Tenth St., N.W., Washington, D.C Additional back-up counsel are Paul Meiklejohn (Reg. No. 26,569); Adam Floyd (Reg. No. 39,192); and Clinton L. Conner (Reg. No. 52,764), each of whom can be contacted at T: (206) ; F: (206) ; E: The postal address for the foregoing counsel is: Dorsey & Whitney LLP, 701 Fifth Ave., Suite 6100, Seattle, WA Additional back-up counsel are Marc R. Labgold (Reg. No. 34,651); T: (703) ; F: (877) ; E: and Steven B. Kelber (Reg. No. 30,073); T: (240)

7 6702; F: (877) ; E: The postal address for the foregoing counsel is: Sunrise Valley Drive, Suite 110, Reston, VA D. Service Information (37 C.F.R. 42.8(b)(4)) Service information for lead and back-up counsel is provided in the designation of lead and back-up counsel above. II. FEES (37 C.F.R ) The undersigned authorizes the Office to charge $23,000 ($9,000 request fee and $14,000 post-institution fee) to Deposit Account No for the fees set forth in 37 C.F.R (a) for this Petition for Inter Partes Review. The undersigned further authorizes charging any additional fees that might be due in connection with this Petition to the above referenced Deposit Account. III. REQUIREMENTS FOR INTER PARTES REVIEW UNDER 37 C.F.R A. Grounds for Standing (37 C.F.R (a)) Pursuant to 37 C.F.R (a), Petitioner certifies that the 589 Patent is available for inter partes review and that Petitioner is not barred or estopped from requesting an inter partes review challenging the 589 Patent on the grounds identified in the present Petition. B. Citation of Prior Art Exhibit Reference Publication or Filing Date Availability as Prior Art - 3 -

8 Ex U.S. Patent No. 5,483,082 ( Takizawa ) Jan. 9, (b) Ex. 1004, Ex Japanese Patent Appl. Publication H and Certified English Translation Of Same ( Hoshino ) April 15, (b) Ex U.S. Patent No. 5,825,449 ( Shin ) Mar. 15, (e) C. Claims and Statutory Grounds (37 C.F.R (b)(1) & (b)(2)) Petitioner requests as relief that Claims 2-6 of the 589 Patent be found unpatentable and cancelled from the 589 Patent on the grounds below. Although Patent Owner Gold Charm Ltd. has disclaimed Claim 1, the invalidity of Claim 1 is still explained because Claims 2-6 depend from it. See Ex. 1011; 35 U.S.C. 253; 37 C.F.R (a); Guinn v. Kopf, 96 F.3d 1419, 1422 (Fed. Cir. 1996). Ground Claims Basis I 1, 3-6 Anticipated (35 U.S.C. 102) in view of Takizawa II 2 Obvious (35 U.S.C. 103) in view of Takizawa and Hoshino III 1, 4-6 Anticipated (35 U.S.C. 102) in view of Shin IV 2 Obvious (35 U.S.C. 103) in view of Shin and Hoshino V 3 Obvious (35 U.S.C. 103) in view of Shin and Takizawa VI 1-4, 6 Anticipated (35 U.S.C. 102) in view of Hoshino - 4 -

9 IV. THE 589 PATENT A. Overview of the 589 Patent The 589 Patent is entitled Method of Fabricating Thin Film Transistor Array. The claims at issue in this Petition, Claims 2-6, are directed to a method for fabricating a TFT array, and the pertinent embodiment in the specification is a method that uses five photolithography steps instead of six. Thin film transistor ( TFT ) arrays are used to turn pixels on and off in liquid crystal displays ( LCDs ) such as televisions and computer monitors. Ex. 1012, 18. TFT arrays are built by depositing various metal, insulating, and semiconductor layers onto a transparent substrate. See Ex. 1001, 1:10-19; Ex. 1012, 19. During fabrication, certain layers are covered with a mask layer that is patterned using photolithography. See Ex. 1001, 1:44-2:54; Ex. 1012, 19. When the substrate is subsequently exposed to an etching process, the mask layer prevents etching in the areas covered by the mask pattern and allows it in in the exposed areas, thus causing the mask pattern to be transferred onto the top layer(s) on the substrate. Ex. 1012, 19. Sequential addition of material layers, followed by etching those layers, fabricates the structure of the TFT array. Ex. 1012, 19. It was known in the prior art that each photolithography step added cost to the fabrication process and reduced the yield of the process by providing an opportunity for defects to occur. See Ex. 1001, 2:50-54, 4:5-14; Ex. 1012, 20. Accordingly, there - 5 -

10 were continued efforts in the industry to reduce the number of masks required to fabricate a TFT array for an LCD display. See, e.g., Ex. 1001, 1:44-48 (citing three example patent application publications); Ex. 1012, 20. The 589 Patent claims that the prior art required at least six photolithography steps in order to create a TFT array (Ex. 1001, Abstract), and describes as the purported invention two embodiments that use either five or four photolithography steps. Ex. 1012, 21. The method of the first embodiment fabricates a twisted nematic ( TN ) TFT array and corresponds to Claims 1-6. Ex. 1012, 22. Figures 7A-7N describe the various steps comprising the method. Figure 7N (below) shows the product of the method and can be used to illustrate the method itself. The method begins with depositing a metal layer (the lowest red layer) onto a transparent substrate (yellow). Ex. 1001, Fig. 7A, 5:30-33; Ex. 1012, 23. This lower metal layer is etched during the first photolithography step to form a gate electrode 1-6 -

11 (red), gate bus line, gate line terminal 3 (also red), auxiliary bus line, and an auxiliary capacitive terminal. Id. at 5:34-49; Ex. 1012, 23. Next, insulating films 14 and 15 (orange) and amorphous silicon film 21 (green) are deposited onto the substrate. Ex. 1001, 5:50-55, Fig. 7D; Ex. 1012, 23. In a second photolithography step, the amorphous silicon is etched to form an island (21) above the gate electrode. Ex. 1001, 5:56-67; Ex. 1012, 24. Then a metal layer (upper red) is deposited onto the substrate and a third photolithography step etches this layer to form source and drain electrodes (7), drain bus lines (8), and drain line terminals (9). Ex. 1001, 6:1-12; Ex. 1012, The next step is to deposit a protection film (13) (purple), followed by a fourth photolithography step, which forms through-holes through the protection film and gate insulation films to expose the source electrode, drain bus line terminal, and gate bus line terminal. Ex. 1001, 6:19-61; Ex. 1012, 28. Lastly, a layer of indium tin oxide ( ITO ) is deposited (blue). Ex. 1001, 6: This ITO layer contacts lower metal layers via the through-holes formed in the prior step, and is etched in a fifth photolithography step to form the pixel electrode (11) and the other blue-colored contacts shown in Figure 7N. Ex. 1001, 6:62-7:7; Ex. 1012, 29. By comparing this process to the patent s description of the prior art (see Ex. 1001, 1:10-43, Figs. 1-3), it appears that the combination of two hole-cutting steps into one is the purported innovation of the 589 Patent. Compare Ex. 1001, 1:28-30, - 7 -

12 1:39-43 with Ex. 1001, 6:22-28; Ex. 1012, 30. But this combination was not new. There were other five-step processes, and even some four-step processes, already in use including ones that used only one photolithography step for cutting throughholes. See, e.g., V.B-V.G; see also, e.g., Ex. 1010, Abstract (teaching that threemask and four-mask processes were known by 1994); Ex. 1012, 20. As a result, the supposed improvement offered by the 589 Patent simply does not exist. Even if, hypothetically, five-step methods for TFT fabrication were not already known, the patent would still not claim anything inventive because the claims are not limited to five photolithography steps. There is no express limitation on the number of photolithography steps allowed in the claims. The claims cannot be distinguished from the prior art based upon the structures or techniques used, either. Steps (a)-(g) in Claim 1 do not expressly recite specific techniques rather, they require forming and removing various structures. These verbs are sufficiently broad that they provide no basis by which to distinguish the prior art under the broadest reasonable construction of the claims: any number of photolithography steps can satisfy the limitations, and each step of the method is satisfied by any technique that forms the required structures or removes the required material. B. Prosecution History Summary Of The 589 Patent The prosecution history of the 589 Patent does not contain rejections and - 8 -

13 responsive arguments by the Applicant and reflects only relatively minor amendments to the claims, such as making words plural or not plural, and adding or deleting said or and. See, e.g., Ex. 1002, 77-78, None of these amendments are material to the issues raised in this Petition. On June 24, 2014, however, the patent owner filed a Disclaimer in Patent Under 37 C.F.R (a), in which the patent owner disclaimed Claim 1 of the 589 Patent, rendering it unenforceable. See Ex. 1011; 35 U.S.C. 253; 37 C.F.R (a); Guinn, 96 F.3d at 1422 ( A statutory disclaimer under 35 U.S.C. 253 has the effect of canceling the claims from the patent and the patent is viewed as though the disclaimed claims had never existed in the patent. ). C. Person of Ordinary Skill in the Art A person of ordinary skill in the art of the 589 Patent at the time of the alleged invention ( POSA ) would typically have had at least a Bachelor s of Science degree involving study of electrical engineering, semiconductor manufacturing, or other relevant fields and approximately five years of professional experience with thin film transistor ( TFT ) liquid crystal display ( LCD ) design and fabrication, or the equivalent. Ex. 1012, 17. D. Claim Construction (37 C.F.R (b)(3)) A claim subject to IPR is given its broadest reasonable construction in light of the specification of the patent in which it appears. 37 C.F.R (b); In re - 9 -

14 Cuozzo Speed Techs., LLC, 778 F.3d 1271, 1281 (Fed. Cir. 2015). Petitioner discusses below the broadest reasonable construction consistent with the specification ( BRC ) for a number of claim terms of the 589 Patent. 1. operative semiconductor Step (c) of Claim 1 requires forming an operative semiconductor on the gate insulating film. Corresponding to the operative semiconductor, the 589 Patent discloses forming a film made of two materials: amorphous silicon (a-si + n + a-si) film 21. Ex. 1001, 5:50-55; Fig. 7D-7F; Ex. 1012, The POSA would understand film 21 to include one layer of intrinsic (i-type) amorphous silicon ( a- Si ) and one layer of n + doped amorphous silicon, with the latter acting as a contact layer between the i-type a-si and a metal layer, such as a source or drain electrode. Ex. 1012, Nonetheless, the 589 Patent uses the singular amorphous silicon... film 21 rather than a plural ( films ), and Figure 7F illustrates only a film 21, not two separate films. Id. at 5:53 (emphasis added), Fig. 7F; Ex. 1012, 37. Thus the BRC for operative semiconductor must include within its scope both the i-type a-si layer and the n + a-si contact layer. Ex. 1012, in facing relation Claim 2 requires an auxiliary capacitive bus line ( ACBL ) in facing relation to the pixel electrode. The specification states that the auxiliary capacitive bus line 4 [is] in facing relation with the pixel electrode 11 with the gate insulating

15 film 14 therebetween. Ex. 1001, 5: Figure 4 shows the ACBL 4 (red) overlapping the pixel electrode 11 (blue). The red capacitive bus line 4 is made of the lower metal layer, which is formed directly on the transparent substrate, just like the gate electrode 1. Ex. 1001, 5:47-49; Ex. 1012, 38. Above the lower metal layer are the gate insulating films (Ex. 1001, 5:50-55, Fig. 7D), and the pixel electrode 11 is formed above those layers (Ex. 1001, 6:62-7:5, Fig. 7N). See also Ex. 1012, 38. The specification describes no other relationship between the ACBL and the pixel electrode. Accordingly, the BRC for in facing relation is such that it overlaps. Ex. 1012, 39. Claim 2 thus requires an auxiliary capacitive bus line formed on said substrate such that it overlaps said pixel electrode with said gate insulating film therebetween. 3. where Claim 4 requires the operative semiconductor to be formed where the gate bus line overlaps said drain bus line. Figure 4 illustrates the first embodiment, and the drain bus line 8 (blue) and gate bus line 2 (red) overlap in a small area a square whose edges are only as long as the bus lines are wide. See Ex. 1001, Fig. 4; Ex

16 1012, 40. The operative semiconductor 6 (green) is relatively close by. Ex. 1001, Fig. 4; Ex. 1012, 40. The same relationship is illustrated in Figure 8, which describes the second embodiment. Ex. 1001, Fig. 8. Again, the operative semiconductor is shown near the overlap; the figures do not show the operative semiconductor 6 (green) directly at or underneath the small area outlined by the overlap of the gate line 2 (red) with the drain bus line 8 (blue). Id.; see also Ex. 1012, The specification shows no location, other than nearby, for the operative semiconductor relative to the drain bus line and the gate bus line. Accordingly, the BRC for where in Claim 4 is nearby the place at which, such that Claim 4 recites, wherein said operative semiconductor is formed nearby the place at which said gate bus line overlaps said

17 drain bus line. Ex. 1012, above said drain and source electrodes Claim 5 requires that a portion of protection film located above said drain and source electrodes is removed in step (f) of Claim 1. But the 589 Patent only describes removing material from above the source electrode, not both the source and drain. The specification describes removing (i) protection film 13 (purple) and gate insulating films 14 and 15 (orange) above gate bus line terminal 3 (lower red) to create through-hole 10a; (ii) protection film 13 only from above source electrode 7 (upper red) to create hole 10b; and (iii) protection film 13 only above drain bus line terminal 9 (upper red) to create through-hole 10c. Ex. 1001, Figs. 7K-7L; 6:22-32, 6:54-58; Ex. 1012, The holes are shown in Figure 7L, reproduced here, 2 As noted in the attached expert declaration, this construction does not require operative semiconductor at the crossover location even though the claim may still allow a semiconductor layer to be formed at the crossover location. Ex. 1012,

18 which includes source electrode 7, drain bus line 8, and the unlabeled drain electrode (shown with a red arrow). Ex. 1012, 46. Holes 10a and 10c correspond to Claim element 1(f), which recites the removal of gate insulation and protection film from above a terminal of the gate bus line, and of protection film from above a terminal of the drain bus line. The remaining hole, 10b, corresponds to Claim 5, which further narrows Claim 1 by reciting the removal of protection film located above said drain and source electrodes. However, through-hole 10b is located above only source electrode 7. Ex. 1012, 48. Accordingly, without prejudice to its ability to assert defenses under 35 U.S.C. 112 under a different standard for claim construction, Petitioner submits that the BRC for above said drain and source electrodes should encompass removing protection film from above any one or all of the drain and source electrodes. Id. E. Unpatentability of the Construed Claims (37 C.F.R (b)(4)) Section V below explains how Claims 2-6 of the 589 Patent are unpatentable under the statutory ground(s) identified above. F. Supporting Evidence (37 C.F.R (b)(5)) The Exhibit List above sets forth the exhibit numbers and a brief description of each exhibit. The explanatory text and claim charts below identify specific portions of the evidence that support the challenge, explain the relevance of the evidence to

19 the challenge raised, and provide the exhibit numbers of the supporting evidence relied upon. V. THERE IS A REASONABLE LIKELIHOOD THAT PETITIONER WILL PREVAIL WITH RESPECT TO AT LEAST ONE CLAIM OF THE 589 PATENT The subject matter of Claims 2-6 of the 589 Patent is disclosed and taught in the prior art as explained below. As set forth in V.A.-V.G., the references and combinations utilized in Grounds I-VI anticipate or render obvious each of Claims 2-6 pursuant to 35 U.S.C and provide a reasonable likelihood that the Petitioner will prevail on at least one claim. 35 U.S.C. 314(a). A. Prior Art The 589 Patent (Ex. 1001) issued on October 12, 1999 from U.S. Patent Application No. 08/989,573, filed December 12, Thus, publications before December 12, 1996 are prior art under 35 U.S.C. 102(b). The 589 Patent claims priority to Japanese Patent Application Publication , filed December 18, Therefore U.S. patents that issued from an application made in the United States before December 18, 1996 are prior art under 35 U.S.C. 102(e). 1. Takizawa (Ex. 1003) Takizawa (U.S. Pat. No. 5,483,082, Ex. 1003) issued on January 9, 1996 and is prior art to the 589 Patent under 35 U.S.C. 102(b). Takizawa was neither cited nor considered during prosecution of the 589 Patent. See generally Ex Takizawa discloses two embodiments of a method for fabricating a thin film

20 transistor matrix device that invalidate the 589 Patent. In fact, Takizawa had the same goals (to simplify the fabrication process to reduce costs and improve production yields, Ex. 1003, 4:1-6, 16:38-55), used the same number of steps (five, see, e.g., Ex. 1003, 13:30-16:21), and reduced the number of steps in the same way (etching all contact holes in one photolithography step, see Ex. 1003, 15:47-53, 16:4-9, 18:45-53). Claims 1 and 3-6 are anticipated by Takizawa, and Claim 2 is rendered obvious by Takizawa in view of Hoshino. 2. Hoshino (Exs and 1005) Hoshino (Japanese Patent Application Publication No. H (Ex. 1004; Certified English Translation Ex. 1005)) 3 was published on April 15, 1994, and is prior art to the 589 Patent under 35 U.S.C. 102(b). The 589 Patent briefly discusses Hoshino, but the file history does not contain a translation and there is no evidence in the file history that the Examiner analyzed Hoshino in any way. Hoshino discloses methods for fabricating a thin film transistor matrix device. Like the 589 Patent, one goal of Hoshino s method was to reduce the number of photolithography steps used during fabrication. Ex. 1005, 0003, Accordingly, Hoshino combined two through-hole etching steps into one, see id. at , just like the combination of steps disclosed in the 589 Patent. As explained in V.G. below, Claims 1-4 and 6 are anticipated by Hoshino. 3 All citations below are to Ex. 1005, the Certified English Translation

21 3. Shin (Ex. 1006) Shin (U.S. Patent No. 5,825,449) was filed in the U.S. on January 10, 1997, issued on October 20, 1998, and claims priority to an earlier application filed March 15, It therefore is prior art to the 589 Patent under 35 U.S.C. 102(e). Shin was neither cited nor considered during prosecution of the 589 Patent. Shin observed that the prior art required at least six photolithography masks, which Shin described as an excessive number. Ex. 1006, 2: Accordingly, to reduce the number of steps, decrease costs, and increase production yield, Shin teaches a method that requires only five photolithography steps to create a TFT array. Shin also discloses the purported point of novelty of the 589 Patent: a step that forms through-holes through multiple layers using only one mask. See, e.g., Ex. 1006, Figs. 2d-2e, 3. As explained in more detail below, two embodiments in Shin invalidate the 589 Patent. Claims 2-6 of the 589 Patent are anticipated or rendered obvious by Shin alone or in combination with Hoshino and Takizawa. B. Ground I: Claims 1 and 3-6 Are Invalid Under 35 U.S.C. 102(b) As Anticipated By Takizawa Takizawa discloses methods that use only five photolithography steps to fabricate a TFT array. Two very similar embodiments anticipate Claims 1 and 3-6 of the 589 Patent, and the two are described together below. See Ex. 1012, 50. The first and second embodiments in Takizawa are methods for fabricating a TFT array that include all of the components required by the preamble of Claim 1. Id

22 at Takizawa discloses TFTs arranged in a matrix, (see, e.g., Ex. 1003, Title, 1:4-7), where the TFTs are formed on a transparent insulating substrate 10 that is made of glass (Ex. 1003, 13:40-42, 17:57-60; Ex. 1012, 51). Takizawa discloses a gate bus line 12c connected to gate electrodes 12a (Ex. 1003, 14:56-63, 18:15-25; Ex. 1012, 51), a drain bus line 36 connected to drain electrodes 22b (Ex. 1003, 14:9-14, 17:51-56; Ex. 1012, 51), and a pixel electrode (picture element electrode 34a) driven by the TFT (Ex. 1003, Figs. 1, 12, 13:54-57, 17:51-56; Ex. 1012, 51). The methods described in Takizawa can be understood with reference to Figures 11A-11D and 13A-13D, with figures 11B and 13B (shown below) focusing on the TFT. Ex. 1012, 53. The method begins with depositing a metal layer (lower red) onto a transparent substrate 10 (yellow). Ex. 1003, 14:56-57; Ex. 1012, 53. The first photolithography step etches the lower metal layer, which corresponds to 589 Patent Claim step 1(a), to form gate electrodes 12a (lower red), gate bus lines 12c (lower red), and the Cs electrodes 12b (lower red). Ex. 1003, Figs. 1, 11-13, 14:56-63, 18:15-21; Ex. 1012, 53. Takizawa then teaches forming a gate insulating film (insulating film 14) over the substrate 10, which corresponds to Claim step 1(b). Ex. 1012, 54. The gate insulating film can be a single silicon nitride (SiN) film, or can be two layers, SiN and silicon oxide (SiO 2 ). Ex. 1003, 15:1-5, 18:15-21; Ex. 1012,

23 The methods continue by forming a semiconductor film of intrinsic amorphous silicon ( i-type a-si, which is often referred to in the art simply as a-si, see Ex. 1012, 24, n.1) and another SiN layer, followed by a photolithography step. Ex. 1003, 15:1-10, 18:15-25; Ex. 1012, 55. Next, doped amorphous silicon (n + a-si) and metal layers are formed and then etched (using a photolithography process), along with the a-si layer, to form an operative semiconductor (a-si active layer 16a and n + a-si contact layers 20a, 20b), which corresponds to Claim step 1(c). Ex. 1003, 15:17-32, 18:15-32; Ex. 1012, 55. This etching step also forms source electrodes (22a), drain electrodes (22b), and drain bus lines (36; see Figs. 1, 12), which corresponds to

24 Claim step 1(d). Ex. 1012, 55. As can be seen in Figures 11B and 13B (above), the source and drain electrodes 22a, 22b (upper red) are formed on top of the operative semiconductor, items 16a, 20a, 20b (dark and bright green). Ex. 1003, Figs. 11B, 13B; Ex. 1012, 55. The drain bus line 36, formed at the same layer as the source and drain electrodes, is formed above the gate insulating film 14 (orange). Ex. 1012, 55. Steps (c) and (d) of Claim 1 of the 589 Patent recite forming an operative semiconductor and source and drain electrodes, with no express limitation requiring the use of any particular technique. Ex. 1001, Claim 1(c)-(d); Ex. 1012, 56. Takizawa discloses one method of forming an operative semiconductor, source electrode, and drain electrode, known as the etch stop technique. See Ex. 1003, 15:6-16, 18:15-25; Ex. 1012, 56. Because it is a method for forming the recited structure, the disclosure in Takizawa of the etch stop technique satisfies Claim 1 elements 1(c) and (d). Ex. 1012, 56. Takizawa also teaches forming a protection film (passivation film 30, pink in Figs. 11B and 13B, above) after the previous steps. In particular, Takizawa describes forming a layer of SiO 2 film, SiN film, or a composite of both, by sputtering to a thickness of approximately 400 nm. Ex. 1003, 15:42-45, 18: Forming this film corresponds to Claim step 1(e). Ex. 1012, 57. Takizawa next describes etching through-holes 32a-32d through the gate insulating film and protection film, which corresponds to Claim step 1(f). Ex. 1003,

25 Figs. 9A-9D; Ex. 1012, 58. Through-hole 32c is formed above the drain bus line terminal by the removal of passivation film 30, and through-hole 32d is formed above the gate bus line terminal by the removal of passivation film 30 and gate insulation film 14. Ex. 1003, 15:46-64, 18:44-52; Ex. 1012, 58. Lastly, corresponding to Claim element 1(g), Takizawa teaches depositing a layer of ITO metal and etching it (using another photolithography mask) to form a pixel electrode (picture element electrode 34a, shown in Figures 11B and 13B in blue). Ex. 1003, 15:65-16:9, 18:54-60, Figs. 11B, 11C, 13B, 13C; Ex. 1012, 59. Relating to Claim 3, Takizawa discloses a multi-layered gate insulating film, having layers of both SiN and SiO 2. Ex. 1003, 15:1-5, 18:15-25; Ex. 1012, 60. Corresponding to Claim 4, Takizawa teaches formation of the operative semiconductor (i-type a-si layer 16a and n + a-si layers 20a and 20b) nearby the place at which the gate and drain bus lines overlap. See, e.g., Ex. 1003, Figs. 1, 12. Takizawa has two TFTs per pixel, and thus there are two operative semiconductors 16a, 20a, and 20b (green) nearby the overlap of the gate bus line (red) and drain bus line (blue), as shown in Figure 1 (reproduced here). Ex. 1012, 61. Takizawa also teaches formation of semiconductor layers at the

26 crossover location. Ex. 1012, 61. Claim 5 requires removal of protection film above the source and drain electrodes, which, under the BRC, includes removal of protection film from above only one of the electrodes. Takizawa, like the 589 Patent itself, discloses removing passivation film 30 from above source electrode 22a to create through-hole 32a. See Ex. 1003, 15:46-53, 18:44-52, Figs. 9B-C (showing through-hole 32a for the first and second embodiments), Fig. 13B (showing pixel electrode 34a contacting source electrode 22a through unlabeled hole 32a); Ex. 1012, 62. As to Claim 6, Takizawa also discloses that the picture element electrode 34a is made of indium tin oxide (ITO). Ex. 1003, 15:65-16:9, 18:44-60; Ex. 1012, 63. Claim 1 Takizawa (Ex. 1003) 4 A method of In the TFT unit of the TFT matrix device, a gate electrode 12a fabricating a thin of a metal layer of, e.g., Al, Cr or others is formed on a film transistor transparent insulating substrate 10 of glass or others. Ex. array comprising 1003, 13: a transparent Next, the method for fabricating the inverse staggered TFT insulating matrix device of FIGS. 1, 2A, 2B, 2C, and 2D will be explained substrate, a with reference of FIGS. 3A to 11D which are sectional views of plurality of thin the inverse staggered TFT matrix device in the respective step film transistors of the method. FIGS. 3A, 4A,..., 11A represent the drain formed on said terminal unit, FIGS. 3B, 4B,..., 11B represent the TFT unit, substrate in a FIGS. 3C, 4C,..., 11C represent the picture element unit and matrix, a gate bus the storage capacitance unit, and FIGS. 3D, 4D,..., 11D line connected to represent the gate terminal unit respectively along the line A-- gate electrodes of A' section, the B--B' section, C--C' section and the D--D' said thin film section in FIG In this and all following claim charts, all emphasis has been added

27 Claim 1 Takizawa (Ex. 1003) 4 transistors, a drain bus line connected to drain electrodes of said thin film transistors, and a pixel electrode driven by said thin film transistors, said method comprising the steps of: (a) forming said gate electrodes and said gate bus line on said transparent insulating substrate; (b) forming a gate insulating film over said substrate; (c) forming an operative semiconductor on said gate insulating film; A required resist pattern is formed on the metal layer, and then with the resist pattern as a mask, the metal layer is etched to form the gate electrode 12a, the Cs electrode 12b, the gate bus line 12c connected to the gate electrode 12a.... Ex. 1003, 14:45-63; see also 17: In the drain terminal unit, a drain terminal lower electrode 28 comprises the n + -type a-si layer 20 common with the n + -type a- Si contact layer 20b and a metal layer 22 common with the drain electrode 22b. The drain terminal lower electrode 28 is connected to a plurality of drain electrodes 22b of the TFT matrix device through drain bus lines 36. Ex. 1003, 14:9-14. Ex. 1003, Figs. 1, 2A-11D; see also Claim 1(a)-(f). A metal layer of, e.g., Al, Cr or others, is formed.... A required resist pattern is formed on the metal layer, and then with the resist pattern as a mask, the metal layer is etched to form the gate electrode 12a, the Cs electrode 12b, the gate bus line 12c connected to the gate electrode 12a.... Ex. 1003, 14:56-63; see also 18:15-21, Figs. 11B, 13B. Then, the insulating film 14 is formed of a SiN film or two layers of an SiN film and a SiO 2 film in an about 400 nmthickness on the entire surface by plasma CVD. Here, the part of the insulating film 14 on the gate electrode 12a is especially called the gate insulating film 14a. Ex. 1003, 15:1-5; see also 18: Then, on the insulating film 14, the non-doped i-type a-si layer 16, and the protecting film 18 of SiO 2 film or SiN film are formed in the stated order respectively in a 20 nm-thickness and a 150 nm-thickness by plasma CVD (FIGS. 4A to 4D).... Subsequently, the n + -type a-si layer 20 is formed in a 60 nmthickness on the entire surface by plasma CVD, and the metal film 22 of, e.g., Al, Cr or others is formed in a 200 nmthickness by sputtering (FIGS. 6A to 6D). Then, a required resist pattern is formed... and... the metal layer 22, the n + -type a-si layer 20 and the i-type a-si layer 16 are sequentially etched. Ex. 1003, 15:6-32; see also 18:15-32, Figs. 4A-6D. (d) forming [T]he metal film 22 of, e.g., Al, Cr or others is formed in a 200

28 Claim 1 Takizawa (Ex. 1003) 4 source electrodes, nm-thickness by sputtering (FIGS. 6A to 6D). said drain Then, a required resist pattern is formed on the metal layer 22, electrodes, and and then with the resist pattern as a mask, the metal layer 22, said drain bus the n + -type a-si layer 20 and the i-type a-si layer 16 are line of said thin sequentially etched. Thus, the a-si active layer 16a of the i-type film transistors on a-si layer 16 is formed on the gate insulating film 14a of the said gate TFT unit, while the source electrode 22a and the drain insulating film electrode 22b of the metal layer 22 connected to the a-si active and said operative layer 16a respectively through the n + -type a-si contact layer semiconductor; 20a, 20b of the n + -type a-si layer 20 on both sides of the channel protecting film 18a are formed.... In the drain terminal unit, the drain terminal lower electrode 28 comprising the n + -type a-si layer 20 and the metal layer 22 connected to the drain electrode 22b through the drain bus line (not shown), is formed (FIGS. 7A to 7D). Ex. 1003, 15:18-41; (e) forming a protection film over said substrate; (f) removing a portion of both said gate insulating film and said protection film, located above a terminal of said gate bus line, and removing a portion of said protection film located above a terminal of said drain bus line; and see also 18: Then, the passivation film 30 of SiO 2 film, SiN film or their composite film is formed in a 400 nm-thickness on the entire surface by CVD or sputtering to cover the TFT (FIGS. 8A to 8D). Ex. 1003, 15: Then, following the steps shown in FIGS. 8A to 11D, the passivation film 30 is formed on the entire surface to cover the completed TFT.... Ex. 1003, 18: Then, a resist is applied, and a resist pattern having openings on the source electrode 22a, the counter electrode 26, the drain terminal lower electrode 28, and the gate terminal lower electrode 12d is formed by photolithography. With the resist pattern as a mask, the passivation film 30, or the passivation film 30 and the insulating film 14 are etched to open the contact holes 32a, 32b, 32c, 32d.... [T]he source electrode 22a, the counter electrode 26, the drain terminal lower electrode 28 and the gate terminal lower electrode 12d [are] exposed in the contact holes 32a, 32b, 32c, 32d, and the transparent conducting film of ITO or others, which is to be formed in the next step, must be electrically connected.... Ex. 1003, 15: Then, following the steps shown in FIGS. 8A to 11D,... the passivation film 30, or the passivation film 30 and the insulating film 14 are selectively etched to form contact holes

29 Claim 1 Takizawa (Ex. 1003) 4 on the source electrode 22a, the 50 drain terminal lower electrode 18 and the gate terminal lower electrode 12d. Ex. 1003, 18: (g) forming said pixel electrode on said substrate. Then, the transparent conducting film 34 of ITO or others is formed on the entire surface in a 100 nm-thickness by sputtering (FIGS. 10A to 10D). Then, the transparent conducting film 34 is patterned as required to form the picture element electrode 34a connected to the source electrode 22a and the counter electrode 26 through the contact holes 32a, 32b. Ex. 1003, 15:65-16:9. Subsequently, a transparent conducting film 34 is formed, and then the transparent conducting film 34 is patterned as required to form the picture element electrode 34a.... Ex. 1003, 18: Claim 3 Takizawa (Ex. 1003) The method as set See Claim 1, above. forth in claim 1, Then, the insulating film 14 is formed of a SiN film or two wherein said gate layers of an SiN film and a SiO 2 film in an about 400 nmthickness on the entire surface by plasma CVD. Here, the part insulating film is formed to have a of the insulating film 14 on the gate electrode 12a is especially multi-layered called the gate insulating film 14a. Ex. 1003, 15:1-5. structure in said Following the steps shown in FIGS. 3A to 6D, a gate step (b). electrode 12a, a Cs electrode 12b, a gate bus line 12c connected to the gate electrode 12a, and a gate terminal lower electrode 12d connected to the gate bus line 12c are formed on a transparent insulating substrate 10, and then an insulating film 14 and a non-doped i-type a-si layer 16 are formed on the entire surface in the stated order. Ex. 1003, 18: Claim 4 Takizawa (Ex. 1003) The method as set See Claim 1, above. forth in claim 1, Ex 1003, Figs. 1, 12; see also Ex. 1003, Figs. 2B-C, 13B-C. wherein said FIG. 1 is a plan view of the inverse staggered TFT matrix operative device according to a first embodiment of this invention. Ex. semiconductor is 1003, 13: formed where FIG. 12 is a plan view of the inverse staggered TFT matrix said gate bus line device according to a second embodiment of this invention. Id. overlaps said at 10:41-42.

30 drain bus line. Then, on the insulating film 14, the non-doped i-type a-si layer 16...[is] formed.... Subsequently, the n + -type a-si layer 20 is formed.... Then, a required resist pattern is formed... and... the n + -type a-si layer 20 and the i-type a-si layer 16 are sequentially etched. Ex. 1003, 15:6-32; see also 18:15-32, Figs. 4A-6D. Claim 5 Takizawa (Ex. 1003) The method as set See Claim 1, above. forth in claim 1, See Ex. 1003, Figs. 9B-C, 13B. wherein a portion Then, a resist is applied, and a resist pattern having openings of said protection on the source electrode 22a, the counter electrode 26, the drain film located above terminal lower electrode 28, and the gate terminal lower said drain and electrode 12d is formed by photolithography. With the resist source electrodes pattern as a mask, the passivation film 30, or the passivation is also removed in film 30 and the insulating film 14 are etched to open the contact said step (f). holes 32a, 32b, 32c, 32d. Ex. 1003, 15: Then, following the steps shown in FIGS. 8A to 11D,... the passivation film 30, or the passivation film 30 and the insulating film 14 are selectively etched to form contact holes on the source electrode 22a, the 50 drain terminal lower electrode 18 and the gate terminal lower electrode 12d. Ex. 1003, 18: Claim 6 Takizawa (Ex. 1003) The method as set See Claim 1, above. forth in claim 1, Then, the transparent conducting film 34 of ITO or others is wherein said pixel formed on the entire surface in a 100 nm-thickness by electrode is sputtering (FIGS. 10A to 10D). formed of indium Then, the transparent conducting film 34 is patterned as tin oxide (ITO). required to form the picture element electrode 34a.... Ex. 1003, 15:65-16:9. Then, following the steps shown in FIGS. 8A to 11D,... Subsequently, a transparent conducting film 34 is formed, and then the transparent conducting film 34 is patterned as required to form the picture element electrode 34a.... Ex. 1003, 18:

31 C. Ground II: Claim 2 Is Invalid Under 35 U.S.C. 103 As Obvious Over Takizawa In View Of Hoshino Claim 2 requires (1) an auxiliary capacitive bus line ( ACBL ) in facing relation to the pixel electrode, with gate insulating film between the bus line and electrode, and (2) the removal in step (f) of Claim 1 of some gate insulating film and protection film above the auxiliary capacitive bus line terminal. Takizawa discloses an ACBL because it describes storage capacitors, referred to as Cs electrodes 12b. See, e.g., Ex. 1003, Figs. 11C, 13C; Ex. 1012, 66. These Cs electrodes are positioned in facing relation with pixel electrodes 34a (the picture element electrodes ) because the capacitors and the pixel electrodes overlap. See Section IV.D.2., supra (discussing the claim construction of in facing relation ); Ex. 1003, Figs. 1, 11C, 13C; Ex. 1012, 66. The POSA would understand that in this context, the storage capacitor electrodes are the same thing as the auxiliary capacitive bus line in the 589 Patent. Ex. 1012, 66. In between the ACBL and pixel electrodes lies the gate insulation film 14. See Ex. 1003, Figs. 11C, 13C; Ex. 1012, 66. The POSA would understand that implementation of the method taught by Takizawa would utilize a terminal at the end of the Cs electrode line (the ACBL), even though Takizawa may not expressly describe one. Ex. 1012, 67. The purpose of the capacitors in the TFT matrix is to maintain a voltage potential at the pixel electrode so that the pixel stays on in between refresh cycles of the display. Ex. 1012,

32 67. TFT and display performance were known to improve when the capacitors were provided a controlled reference voltage, so the capacitors were connected together to form an ACBL that often terminated in a single pad (or terminal) to which the reference voltage could be applied. Ex. 1012, The capacitors could not effectively serve their purpose if they were not provided a reference voltage via a terminal. Id. Accordingly a POSA would understand that Takizawa contemplated the use of a capacitive line terminal because otherwise the disclosed Cs electrodes 12b would not have a beneficial effect. See Ex. 1012, Indeed, using an ACBL with a terminal, as described in the 589 Patent, was known for at least a decade prior to the filing date of the 589 Patent. Ex. 1012, 68. Even if it were found that a POSA would not understand that an ACBL terminal would be used in the device fabricated by the method disclosed in Takizawa, Hoshino (Ex. 1005) 5 expressly discloses both a terminal for the ACBL and removal of films from above the ACBL terminal and gate line terminals in the same process step, as recited in Claim 2. Ex. 1012, 69. In both Takizawa and Hoshino, the ACBL lies in 5 Hoshino was filed in 1992 and is described more fully below in V.E., below

33 the lower metal layer, which also includes the gate electrode and gate bus line. Hoshino teaches that etching of a contact hole through to the terminal of the ACBL occurs in the same photolithography step as the etching of the contact hole to the gate bus line terminal. See Ex. 1005, Fig. 4(m), (q); Ex. 1012, The POSA implementing the method of Takizawa would use a terminal for the ACBL as expressly taught by Hoshino for the reason discussed above i.e., to provide a reference voltage and thereby achieve better performance. Ex. 1012, 70. The POSA would have reason to etch the ACBL contact hole at the same time as the gate bus line hole, as Hoshino describes, because the stated objective of both Takizawa and Hoshino is to reduce the number of photolithography steps required. See, e.g., Ex. 1003, 4:1-6; Ex. 1005, Abstract, 0003; Ex. 1012, 70. To etch the contact hole in a separate photolithography step would be counter to, and frustrate, this stated objective, and the POSA would know how to etch the hole in the same photolithography step because Hoshino teaches how to do so. Ex. 1012, 70. Further, as described above, the TFT array operates best when the ACBL receives a consistent voltage, which is provided by driving circuitry through the ACBL terminal. Thus, to create a properly operating device, the POSA would seek out methods of providing a reference voltage to the capacitive electrodes and would incorporate the ACBL terminal of Hoshino into the Takizawa device in order to do so. Ex. 1012, 70. Because Hoshino has the same objective of reducing the number of photolithography

34 steps, and addresses the same subject of TFT array fabrication, the POSA would look to Hoshino for ways to implement the method of Takizawa, and would have reason to implement the advantageous features of Hoshino into the method of Takizawa. Ex. 1012, 70. Accordingly, Takizawa combined with Hoshino renders obvious Claim 2. Claim 2 Takizawa (Ex. 1003) In View Of Hoshino (Ex. 1005) The method as In the storage capacitance unit, there is formed a Cs (storage set forth in capacitance) electrode 12b of a metal layer of the same material claim 1, wherein as the gate electrode 12a on the transparent substrate 10. A said thin film dielectric film 24 comprising an insulating film 14 common with transistor array the gate insulating film 14a, and a non-doped i-type a-si layer 16 further of the same material as the a-si active layer 16a is formed on the comprising an Cs electrode 12b. On the dielectric film 24, there is formed a auxiliary counter electrode 26 comprising an n + -type a-si layer 20 of the capacitive bus same material as the n + -type a-si contact layers 20a, 20b, and a line formed on metal layer 22 of the same material as the source and the drain said substrate in electrodes 22a, 22b. facing relation The counter electrode 26 is connected to the picture element to said pixel electrode 34a through a contact hole 32b opened in the electrode with passivation film 30. Thus, the storage capacitance unit comprising said gate the counter electrode 26 and the Cs electrode 12b with the insulating film dielectric film 24 held therebetween is formed in connection with therebetween, the picture element electrode 34a. Ex. 1003, 13:58-14:8. and wherein a Ex. 1003, Fig. 13C. portion of both At this time, the picture element electrode 34a is formed on a said gate dielectric film 38 comprising the insulating film 14 and the insulating film passivation film 30 above the Cs electrode 12b, and accordingly and said the storage capacitance unit comprising the picture element protection film, electrode 34a functioning as the counter electrode, the Cs located above a electrode 12b, and the dielectric film 38 held between both terminal of said electrodes is completed (FIGS. 16A to 16D). Ex. 1003, 19:3-10. auxiliary (0040) Refer to Fig 3(a) (c) [ ] A DC magnetron sputtering capacitive bus device is used to continuously form Al films (3, 4) 100 nm thick line, is also and Ti films (3a, 4a) 50 nm thick on the glass substrate (1) which removed in said has been washed and otherwise surface treated. Using a resist film step (f). (not illustrated) as a mask, wet etching is carried out with a liquid mixture of phosphoric acid and hydrofluoric acid as the etchant,

35 Claim 2 Takizawa (Ex. 1003) In View Of Hoshino (Ex. 1005) and gate bus lines (3, 3a) and auxiliary capacity bus lines (4, 4a) are formed. Ex. 1005, (0047)... Next, an ITO film that is, for example, 300 nm thick is formed on the entire surface with the sputtering method, a mask is used to etch the ITO film, and a pixel electrode (21) connected to the source electrode (18) and a contact (19a) connected to the end of the drain bus line (19) are formed. Ex. 1005, (0048)... [A] resist mask (22) is formed thereon [on the protective film 12] having a hole (23a) on the pixel electrode (21), a hole (23b) in the end of the gate bus line (3), a hole (23c) in the end of the auxiliary capacity bus line (4) and a hole (23d) in the end of the drain bus line (19). (0049) Refer to Fig. 4 (o) (r) [ ] The SiN film (12) is etched with BHF (buffered hydrofluoric acid) using the resist mask (22) as a mask. ITO acts as the etch stop layer at the pixel electrode (21) and the end of the drain bus line (19), and the polyimide film (20) acts as the etch stop layer at the end of the gate bus line (3) and the end of the auxiliary capacity bus line (4). Ex. 1005, Ex. 1005, Figs. 4(o), 4(m), 4(q). D. Ground III: Claims 1 And 4-6 Are Invalid Under 35 U.S.C. 102(e) As Anticipated By Shin Shin discloses the limitations of Claims 1 and 4-6. Ground III based on Shin is not redundant to Grounds I or II because Shin discloses the back channel etch method for fabricating a TFT, which is the same technique as the 589 Patent, whereas Takizawa teaches the etch stop method. Ex. 1012, 71. Shin teaches the claims of the 589 Patent, like Takizawa, but does it in a different way. Two Shin embodiments (the second a variant of the first) teach the limitations of the 589 Patent alone and combined with Takizawa or Hoshino. The discussion below refers to both embodiments unless otherwise noted

36 Regarding Claim 1, Shin discloses a method for fabricating an active matrix thin film transistor array for driving LCD pixels in a display. Ex. 1006, 1:8-21; Ex. 1012, 72. The POSA would understand that a TFT array for an LCD display would comprise a plurality likely thousands or millions of TFTs formed on a substrate. Ex. 1012, 72. Shin Figure 6 is a schematic representation of a prior art TFT array, and the POSA would understand that, as an improvement upon that prior art, the method described by Shin also contemplates fabrication of such an array. Ex. 1006, Fig. 6; Ex. 1012, 72. Shin describes a transparent glass substrate 1, gate electrodes 2 connected to gate bus lines 600, gate pads 630, source wiring connected to the source electrodes 7, and a pixel electrode drive by the TFTs. See generally Ex. 1006, 3:44-4:27; Figs. 2a-2e, 3, 6; Ex. 1012, 72. Shin also teaches a five-mask method for fabricating a TFT array that discloses the limitations of Claim elements (a)-(g). Shin describes multiple

37 embodiments, and two of them disclose the claimed method of the 589 Patent. See Ex. 1006, 3:44-4:46 (first embodiment), 4:47-5:22 (second embodiment); Ex. 1012, 73. The result of the method of the first embodiment is shown in Figure 2e (above), and the second embodiment is shown in Figure 3 (below). Corresponding to Claim step 1(a) of the 589 Patent, Shin expressly describes forming gate electrodes 2 (lower red) on the glass substrate along with storage capacitors 2D (see Ex. 1006, 3:44-49, 4:65-5:1), and the POSA would understand that the gate electrodes 2 are connected to a gate bus line formed of the same metal layer because proper TFT operation requires the gate electrodes to be connected to a gate bus line. See Ex. 1006, Fig. 6 (showing gate lines 600), 1:22-30; Ex. 1012, 74. Next, corresponding to Claim step 1(b), Shin teaches forming a gate insulating film 3 (orange), such as an oxide or nitride film, over the substrate. Ex. 1006, 3:

38 52, 5:1-2; Ex. 1012, 75. The insulation film is followed by formation of a semiconductor active layer 4 (dark green), made of amorphous silicon ( a-si ). Ex. 1006, 3:53-60, 5:2-5; Ex. 1012, 75. After subsequent deposition of a doped a-si layer 5 (bright green), layers 4 and 5 are etched to form semiconductor islands on the substrate, which corresponds to Claim step 1(c). Ex. 1006, 3:60-62, 5:4-5; Figs. 2b, 3; Ex. 1012, 75. Many of these features are shown in Shin Figures 2a-2e and 3; accurate labels, as a POSA would understand them, have been added to Figures 2e and 3 (above) in red text. Ex. 1012, 75. Thereafter, corresponding to Claim step 1(d), Shin discloses forming source and drain electrodes (upper red), and a drain bus line, on the gate insulating film and operative semiconductor. Ex. 1006, 3:63-4:5, 5:6-8; Ex. 1012, 76. The POSA would understand that what the 589 Patent refers to as forming drain electrodes and a drain bus line, Shin describes as forming source electrodes 7 and source wiring. Ex. 1006, 3:63-4:5, 5:6-8; Fig. 6; Ex. 1012, Shin also discloses a drain electrode 8 which a POSA would understand to be equivalent to the source electrode in the 589 Patent. Ex. 1006, 3:63-4:5, 5:6-8; Fig. 2c; Ex. 1012, The POSA would understand that the labeling of an electrode as source or drain in this context has no particular meaning other than to signify one side of the TFT as different than the other. Ex. 1012, 77. In the 589 Patent, the drain side is connected to the drain bus line that receives a signal voltage, and the source side connects the TFT to the pixel

39 electrode. Ex. 1012, 77. In Shin, these labels are simply reversed: the source connects to source wiring that receives a signal, and the drain connects the TFT to the pixel electrode. Ex. 1012, 77. Shin forms the same structures as those claimed by the 589 Patent, even if the labeling is not identical. See Ex. 1012, 77. Shin subsequently forms a passivation layer 9, such as a nitride film, over the entire substrate. Ex. 1006, 4:6-8, 5:8-15. This corresponds to Claim step 1(e). Ex. 1012, 78. Next, contact holes 20, 30, and 40 (first embodiment) and holes 45, 50, 55, 60, and an unnumbered hole in Figure 3 (second embodiment) are etched through the passivation layer 9 and gate insulating film 3, which corresponds to Claim step 1(f). Ex. 1006, 4:8-15, 4:47-61, 5:8-15; Figs. 2d, 2e, 3; Ex. 1012, 78. In the first embodiment, contact hole 40 is formed above gate pad 2C by etching portions of both gate insulating film 3 and passivation layer 9. Ex. 1006, Figs. 2d, 2e; 4:6-15; 4:47-64; Ex. 1012, 79. Contact hole 20 is formed above the source pad 7A (the drain bus line terminal in the 589 Patent) by etching only

40 passivation layer 9. Ex. 1006, Figs. 2d, 2e; Ex. 1012, 79. Similarly, in the second embodiment, contact hole 55 is formed above gate pad 2C (labeled as 2B in Figure 3) by etching portions of both gate insulating film 3 and passivation layer 9. Ex. 1006, Fig. 3, 4:53-56, 5:8-22; Ex. 1012, 80. Contact hole 45 and an unlabeled hole ( unnumbered contact hole X in Figure 3 below) are formed above the source pad (equivalent to the drain bus line terminal in the 589 Patent) by etching both the gate insulating film 3 and passivation layer 9. Ex. 1012, As Shin explains, the step of etching the gate insulating layer and the step of etching the passivation layer to expose the pads are [performed] in only one mask step. Ex. 1006, 4: Claim step 1(f) requires that portions of the protection layer are removed above the terminal of the drain bus line (the source pad in Shin), and step 1(f) does not preclude the removal of portions of the gate insulating layer from above the

41 terminal of the drain bus line. Thus the second embodiment of Shin, like the first, discloses Claim step 1(f). Ex. 1012, 81. As to Claim step 1(g), both embodiments in Shin teach forming a pixel electrode 6. Ex. 1006, Figs. 2e, 3; 4:16-26; 5:17-22; Ex. 1012, 82. With regard to Claim 4, Shin teaches semiconductor active layer 4 above the gate and below the source and drain electrodes. Ex. 1006, 3:44-49, 3:54-56, 3:60-4:5, 4:47-5:5; Ex. 1012, 83. Shin also teaches source wiring (called a drain bus line in the 589 Patent; Ex. 1006, 4:1-5; Ex. 1012, 83), and gate lines (Ex. 1012, 83). The prior art shown in Figure 6 of Shin includes gate lines 600 connecting the gate electrodes to a gate pad. See Ex. 1006, 1:22-26; Fig. 6; Ex. 1012, 83. The POSA would understand the invention of Shin to include gate lines connecting the gate electrodes in a given row to the corresponding gate terminal because Shin is an improvement on the prior art shown in Figure 6, and because gate lines connected to gate electrodes are common and required components in a TFT array. Ex. 1012, 83. For similar reasons, the POSA would understand that the matrix layout of the TFT array taught by Shin s two embodiments would be the same as that shown in the prior art upon which Shin improves. Ex. 1012, 84. Figure 6 shows the matrix in schematic form, and Shin expressly states that the Thin film transistors 620, serving as active devices, are located at intersecting portions of gate lines 600 and data lines 610. Ex. 1006, 1:22-24, Fig. 6; Ex. 1012, 84. Because the TFTs contain the

42 operative semiconductors (e.g., semiconductor layers 4 and 5) and are located at (nearby) the intersections of the gate and data lines, Shin teaches that the operative semiconductor is formed where the gate bus line overlaps the drain bus line (data line). Ex. 1012, 84. Claim 5 requires removal of protection film above the source and drain electrodes, which, under the BRC, includes removal of protection film from above only one of the electrodes. See IV.D.4., supra. Shin, like the 589 Patent itself, discloses removing passivation film 9 from above drain electrode 8 to create contact hole 30 (first embodiment) and contact hole 50 (second embodiment). See Figs. 2d, 2e, 3; Ex. 1012, 85. Removal of the passivation film to create holes 30 and 50 is performed by the same etching step as that in Claim element 1(f). Ex. 1006, 4:8-15; 4:53-56; 5:8-15; Ex. 1012, 85. As to Claim 6, the pixel electrode 6 is made of indium tin oxide (ITO). Ex. 1006, 4:16-19; 5:16-19; Ex. 1012, 86. Shin thus anticipates Claims 1 and 4-6. Ex. 1012, 86. Claim 1 Shin (Ex. 1006) A method of The present invention relates to a liquid crystal display fabricating a thin film (LCD) device and a method of manufacturing the same, transistor array and more particularly, to a liquid crystal display device comprising a having a combined source electrode and source pad transparent structure. insulating substrate, a Active matrix thin film displays include thin film plurality of thin film transistors (TFTs) for driving the liquid crystal material in transistors formed on individual pixels of the display. As shown in FIG. 6, a said substrate in a conventional LCD includes an array of pixels each having

43 Claim 1 Shin (Ex. 1006) matrix, a gate bus line connected to gate electrodes of said thin film transistors, a drain bus line connected to drain electrodes of said thin film transistors, and a pixel electrode driven by said thin film transistors, said method comprising the steps of: (a) forming said gate electrodes and said gate bus line on said transparent insulating substrate; (b) forming a gate insulating film over said substrate; (c) forming an operative semiconductor on said gate insulating film; liquid crystal material (not shown) sandwiched between a common electrode provided on a top plate (not shown) and a pixel electrode 6 disposed on a bottom plate. The bottom plate further includes a plurality of gate lines 600 intersecting a plurality of data lines 610. Ex. 1006, 1:8-21; Figs. 2a-2e, 3, 6. Gate Pads 630 and Data Pads 640 are connected to the gate lines and data lines to receive datas from gate driver and data driver respectively. Ex. 1006, 1: The gate electrode is used for applying a voltage in order to drive the active layer in the completed TFT device. Ex. 1006, 3: See also Claim 1(a)-(f), below. Referring first to FIG. 2a, a conductive layer is formed on a transparent glass substrate 1 and patterned to form a gate electrode 2, a storage capacitor electrode 2D, and a gate pad 2C, all of the same material. The gate electrode is used for applying a voltage in order to drive the active layer in the completed TFT device. Ex. 1006, 3: In other words, a conductive layer is formed on a transparent glass substrate 1 and patterned to form gate 2, a storage capacitor electrode 2D, a source pad 2A and a gate pad 2B. Ex. 1006, 4:65-5:1. The bottom plate further includes a plurality of gate lines 600 intersecting a plurality of data lines 610. Ex. 1006, 1:19-21; see also id. at 1:22-30, Fig. 6. As shown in FIG. 2b, a gate insulating film 3 such as a nitride film or an oxide film is formed on the entire surface of the substrate in order to electrically insulate gate 2. Ex. 1006, 3: After forming a gate insulating film 3 on the entire surface of the substrate,.... Id. at 5:1-5. Semiconductor active layer 4 is then formed on insulating gate 2. Active layer 4 is preferably made of amorphous silicon layer deposited by a chemical vapor deposition (CVD) process. Then, in order to reduce the contact resistance between the active layer and the subsequently formed source and drain, an impurity-doped semiconductor layer 5 is formed on amorphous silicon

44 Claim 1 Shin (Ex. 1006) layer 4, as an ohmic contact layer. Impurity-doped semiconductor layer 5 and amorphous silicon layer 4 are etched according to a predetermined active layer pattern. Ex. 1006, 3: After forming a gate insulating film 3 on the entire surface of the substrate, an amorphous silicon layer 4 and an impurity-doped semiconductor layer 5 are sequentially formed thereon. These layers are then etched in accordance with a predetermined active layer pattern. Ex. 1006, 5:1-5. Ex. 1006, Figs. 2b, 3. (d) forming source electrodes, said drain electrodes, and said drain bus line of said thin film transistors on said gate insulating film and said operative semiconductor; (e) forming a protection film over said substrate; (f) removing a portion of both said gate insulating film and said protection film, located above a terminal of said gate bus line, and removing a portion of said protection film located above a terminal of said drain bus line; and As shown in FIG. 2c, a conductive layer for forming source electrode 7 and drain electrode 8 is deposited on the substrate by patterning a sputtered layer of conductive material. Ex. 1006, 3: Then, a conductive layer is formed on the substrate and etched in accordance With a predetermined pattern, thereby forming a source electrode 7 and a drain electrode 8. Ex. 1006, 5:6-8. As shown in FIG. 2d, a passivation layer 9, e.g., a nitride film, is deposited on the entire surface of the substrate by a CVD process. Ex. 1006, 4:6-8. After forming a passivation layer 9 on the entire surface of the substrate.... Ex. 1006, 5:8-10. Then, a predetermined portion of passivation layer 9 and gate insulating film 3 are selectively etched to form first, second and third contact holes 20, 30 and 40, thereby exposing a predetermined region of source pad 7A above gate insulating film 3, a predetermined region of drain electrode 8, and a predetermined region of gate pad 2C. For external electrical connections It [sic] is necessary to exposed pads 7A and 2C. Ex. 1006, 4:8-15. FIG. 3 illustrates a second embodiment of the present invention in which the step of etching the gate insulating layer and the step of etching the passivation layer to expose the pads are preformed [sic] in only one mask step. In particular, source pad 2A is composed of gate material, as in the conventional method, and is formed at the same time as gate 2, storage capacitor electrode 2D and gate pad 2B.

45 Claim 1 Shin (Ex. 1006) After forming first, second, third and fourth contact holes 45, 50, 55 and 60, material for forming the pixel electrode is then deposited. Ex. 1006, 4: After forming a passivation layer 9 on the entire surface of the substrate, passivation layer 9 and gate insulating film 3 are selectively etched, thereby forming a first contact hole exposing the source pad 2A and a third contact hole exposing the gate pad 2B. Ex. 1006, 5:8-13. Ex. 1006, Figs. 2d, 3. (g) forming said pixel electrode on said substrate. As shown in FIG. 2e, an indium tin oxide (ITO) layer is next deposited on the substrate by sputtering or a CVD process and etched according to a predetermined pattern to form a pixel electrode 6. Ex. 1006, 4: ITO is then deposited on the entire surface of the substrate and patterned to form a pixel electrode 6 connected to drain electrode 8 through the contact hole overlying drain electrode 8 in the pixel part. Ex. 1006, 5: Claim 4 Shin (Ex. 1006) The method as set See Claim 1, above. forth in claim 1, Thin film transistors 620, serving as active devices, are wherein said located at intersecting portions of gate lines 600 and data operative lines 610. Gate lines 600 and data lines 610 are connected semiconductor is to the gates and sources, respectively of thin film transistors formed where said 620. Ex. 1006, 1: gate bus line overlaps Source electrode 7 thus forms part of a transistor region said drain bus line. and serves as source pad 7A above the gate insulating film so that the same conductive layer constitutes part of the source wiring and the source electrode of the TFT. Ex. 1006, 4:1-5. Figs. 2a, 3, 6. Claim 5 Shin (Ex. 1006) The method as set See Claim 1, above. forth in claim 1, Then, a predetermined portion of passivation layer 9 and wherein a portion of gate insulating film 3 are selectively etched to form first, said protection film second and third contact holes 20, 30 and 40, thereby located above said exposing a predetermined region of source pad 7A above drain and source gate insulating film 3, a predetermined region of drain

46 Claim 5 Shin (Ex. 1006) electrodes is also electrode 8, and a predetermined region of gate pad 2C. For removed in said step external electrical connections It [sic] is necessary to (f). exposed pads 7A and 2C. Ex. 1006, 4:8-15. FIG. 3 illustrates a second embodiment of the present invention in which the step of etching the gate insulating layer and the step of etching the passivation layer to expose the pads are preformed [sic] in only one mask step. Ex. 1006, 4: After forming a passivation layer 9 on the entire surface of the substrate, passivation layer 9 and gate insulating film 3 are selectively etched, thereby forming a first contact hole exposing the source pad 2A and a third contact hole exposing the gate pad 2B. Since the passivation layer 9 and gate insulating film 3 are preferably etched in a single step, the sidewalls of the first and second contact holes are planar and smooth. Ex. 1006, 5:8-15. Claim 6 Shin (Ex. 1006) The method as set See Claim 1, above. forth in claim 1, As shown in FIG. 2e, an indium tin oxide (ITO) layer is wherein said pixel next deposited on the substrate by sputtering or a CVD electrode is formed of process and etched according to a predetermined pattern to indium tin oxide form a pixel electrode 6. Ex. 1006, 4: (ITO). ITO is then deposited on the entire surface of the substrate and patterned to form a pixel electrode 6 connected to drain electrode 8 through the contact hole overlying drain electrode 8 in the pixel part. Ex. 1006, 5: E. Ground IV: Claim 2 Is Invalid Under 35 U.S.C. 103 As Obvious Over Shin In View Of Hoshino Claim 2 depends from Claim 1, and as described above for Ground III, Shin discloses the method of Claim 1. Claim 2 requires an auxiliary capacitive bus line ( ACBL ) in facing relation to the pixel electrode with gate insulating film in between, and that portions of the gate insulating film and protection film are removed

47 in step (f) of Claim 1. See Ex. 1012, 87. Shin discloses an ACBL and calls it a storage capacitor electrode. See Ex. 1006, 3:46, Figs. 2a-2e (item 20), Fig. 3 (item 2); Ex. 1012, 88 (including footnote explaining that the POSA would understand Figure 3, item 2 to be storage capacitor electrode 2D). As is clear from Figure 2e (a magnified portion of which is shown here), the storage capacitor electrode 2D (red) is formed such that it overlaps i.e., is in facing relation with pixel electrode 6 (blue). Ex. 1012, 89. The gate insulation layer (orange) is disposed between the pixel electrode (blue) and storage capacitor electrode (red). 6 Ex. 1012, 89. The POSA would understand that implementation of the method taught by Shin would utilize a terminal at the end of the ACBL, even though Shin may not expressly describe one, for the same reasons as discussed with respect to Takizawa in 6 Relevant to both the Takizawa and Shin Grounds, the characterization of the ACBL as electrodes versus as a bus line is of no consequence because the same metal pattern constitutes the bus line and electrode. The bus line acts as the electrode where it overlaps the pixel electrode. See Ex. 1012,

48 V.C., supra. See Ex. 1012, 90, A POSA would understand that Shin contemplated the use of a capacitive line terminal because otherwise the disclosed storage capacitor electrodes 2D would not have a beneficial effect. Ex. 1012, 90, Even if it were found that a POSA would not understand that an ACBL terminal would be used in the device fabricated by the method disclosed in Shin, Hoshino expressly discloses both a terminal for the ACBL and removal of films from above the terminal in the same process step as removal of films from above the gate line terminal. Ex. 1012, In both Shin and Hoshino, the ACBL lies in the lower metal layer, which also includes the gate electrode and gate bus line. Id. As described above in Ground II, Hoshino teaches that etching of a contact hole through to the terminal of the ACBL occurs in the same photolithography step as the etching of the contact hole to the gate bus line terminal. See Ex. 1005, Fig. 4(m), (q); Ex. 1012, 92. Thus the POSA implementing the method of Shin would use a terminal for the ACBL as expressly taught by Hoshino for the reason discussed above i.e., to provide a reference voltage. Ex. 1012, 93. The POSA would have reason to etch the ACBL contact hole at the same time as the gate bus line hole, as Hoshino describes, because the stated objective of both Shin and Hoshino is to reduce the number of photolithography steps required. See, e.g., Ex. 1006, Abstract, 2:25-36; Ex. 1005, Abstract, 0003; Ex. 1012, 93. To etch the contact hole in a separate

49 photolithography step would be counter to, and frustrate, this stated objective, and the POSA would know how to etch the hole in the same photolithography step because Hoshino teaches how to do so. Ex. 1005, ; Ex. 1012, 93. Further, as described, the TFT array operates best when the ACBL receives a consistent voltage, which is provided by driving circuitry through the ACBL terminal. Ex. 1012, 93. Thus to create a properly operating device, the POSA would seek out methods of providing a reference voltage to the capacitive electrodes and would incorporate the ACBL terminal of Hoshino into the Shin device. Ex. 1012, 93. Because Hoshino has the same objective of reduced photolithography steps, and addresses the same subject of TFT array fabrication, the POSA would look to Hoshino for ways to implement the method of Shin, and would have reason to implement the advantageous features of Hoshino into the method of Shin. Ex. 1012, 93. Accordingly, the combination of Shin and Hoshino renders obvious Claim 2. Claim 2 Shin (Ex. 1006) In View Of Hoshino (Ex. 1005) The method as set See Claim 1, including 1(f), above. forth in claim 1, Referring first to FIG. 2a, a conductive layer is formed on a wherein said thin transparent glass substrate 1 and patterned to form a gate film transistor electrode 2, a storage capacitor electrode 2D, and a gate pad array further 2C, all of the same material. The gate electrode is used for comprising an applying a voltage in order to drive the active layer in the auxiliary completed TFT device. Ex. 1006, 3: capacitive bus line In particular, source pad 2A is composed of gate material, as formed on said in the conventional method, and is formed at the same time as substrate in facing gate 2, storage capacitor electrode 2D and gate pad 2B. Ex. relation to said 1006, 4: pixel electrode [A] conductive layer is formed on a transparent glass with said gate substrate 1 and patterned to form gate 2, a storage capacitor

50 Claim 2 Shin (Ex. 1006) In View Of Hoshino (Ex. 1005) insulating film electrode 2D,.... Ex. 1006, 4: therebetween, and FIG. 3 illustrates a second embodiment of the present wherein a portion invention in which the step of etching the gate insulating layer of both said gate and the step of etching the passivation layer to expose the pads insulating film and are preformed [sic] in only one mask step.... After forming said protection first, second, third and fourth contact holes 45, 50, 55 and 60, film, located above material for forming the pixel electrode is then deposited. Ex. a terminal of said 1006, 4: auxiliary See also Ex. 1006, Figs. 2e, 3. capacitive bus line, is also removed in Ex. 1005, 0040, (quoted in the claim chart for said step (f). V.C., supra), Figs. 4(o), 4(m), 4(q). F. Ground V: Claim 3 Is Invalid Under 35 U.S.C. 103 As Obvious Over Shin In View Of Takizawa The discussion of Ground III above explains how Shin discloses the limitations of Claim 1. Claim 3 depends from Claim 1 and additionally requires the use of a multi-layered gate insulation layer, which is disclosed by Takizawa. See Ground I, supra; see also Ex. 1003, 15:1-3. As explained below, a POSA would have reason to substitute the multi-layered gate insulator of Takizawa for the single-layer one in Shin as required by Claim 3. Ex. 1012, 94. The POSA would have reason to include a multi-layered gate insulation as taught by Takizawa in the device of Shin because it was known to use multi-layer gate insulation films to achieve known benefits, including (1) a more stable TFT threshold voltage, (2) higher production yields by alleviating pinhole defects, and (3) better transistor characteristics. Ex. 1012, As described in Morimoto (Ex. 1009), the TFT LCD displays of at least six companies were known to use multi

51 layer gate insulators by See Ex at 339; Ex. 1012, 95. Often, SiN x was used as an interface layer, while SiO x, SiO x N y, TaO x, AlO x, and other materials were used as a bulk layer. Ex. 1012, 95. It was also known that gate insulator quality is a very important factor regarding the performance of a TFT. Ex. 1012, 96. For example, when a voltage has been applied to a TFT for a long period of time, the threshold voltage of the TFT may shift. Ex. 1012, 96. This causes the TFT to operate differently and affects the TFT LCD array quality negatively. Ex. 1012, 96. Single layer gate insulation layers experience a threshold voltage shift at lower voltages, while a TFT with an SiO 2 and SiN x (dual layers) gate insulator experiences a much smaller shift. See, e.g., Ex. 1012, 96. The knowledge of the POSA in this regard is demonstrated by Ibaraki (Ex. 1007), which compared single and multiple gate insulating layers. See Ex at 97. Ibaraki observed that The TFT with CVD SiO 2 combined with SiN x shows remarkably small shift compared to TFT with another dielectrics. Ex at 98. Further, Hiranaka (Ex. 1008) taught that multi-layered gate insulating films led to decreased trapped charges and better TFT characteristics. See Ex. 1012, 97. As stated in Hiranaka, [t]his paper reports a-si TFTs with double gate insulators of SiO x N y /SiN x. A thin SiNx layer inserted between the a-si and the SiO x N y gate insulator decreases the density of trapped charges without degrading the switching characteristics. Ex at 229; Ex. 1012,

52 Therefore, in order to achieve the known benefits of double layer gate insulation films, the POSA would combine Shin with Takizawa. Ex. 1012, 98. Such a combination combines known methods (TFT fabrication) with known techniques (multi-layer gate insulation films) to achieve predictable results (better performance). Ex. 1012, 98. Indeed, meeting the claimed limitation is nothing more than substituting one known technique (multi-layer gate insulators) for another (single layers) to achieve those predictable results. Ex. 1012, 98. Claim 3 Shin (Ex. 1006) In View Of Takizawa (Ex. 1003) The method as set forth See Claim 1, including 1(b), above. in claim 1, wherein said Then, the insulating film 14 is formed of a SiN film or gate insulating film is two layers of an SiN film and a SiO2 film in an about formed to have a multilayered structure in Here, the part of the insulating film 14 on the gate 400 nm-thickness on the entire surface by plasma CVD. said step (b). electrode 12a is especially called the gate insulating film 14a. Ex. 1003, 15:1-5. G. Ground VI: Claims 1-4 And 6 Are Invalid Under 35 U.S.C. 102(b) As Anticipated By Hoshino Hoshino discloses a method for fabricating a TFT array having all the components required by the preamble of Claim 1. Hoshino is not redundant to Grounds I-V for several reasons. Hoshino uses a different total number of photolithography steps, performs the steps in a slightly different sequence, and anticipates Claim 2 instead of rendering it obvious. Hoshino invalidates the claims despite these differences because the claims, under their broadest reasonable constructions, do not expressly limit the total number or sequence of

53 photolithography steps. See Ex. 1001, Claim 1, preamble ( said method comprising the steps of ) (emphasis added). It is true that Hoshino was included in the prosecution history for the 589 Patent, and the specification even criticizes it. See Ex. 1001, 2:37-49; Ex. 1012, 99. But the criticisms are irrelevant here because the 589 Patent has no limitations expressly excluding the lift-of process, or limiting the claimed method to any certain number of photolithography steps. Ex. 1012, 99. Hoshino discloses the elements of the preamble to Claim 1, including, for example, a transparent glass substrate 1. Ex. 1005, 0040; Ex. 1012, 100. The patent teaches a method for producing a thin film transistor matrix, and includes Figure 5 as an example TFT array. Ex. 1005, Abstract, Fig. 5, The TFT array includes gate and drain bus lines connected to the gate and drain electrodes, respectively. Ex. 1012, 100. The TFTs are used to drive pixel electrodes connected thereto. Ex. 1005, ; Ex. 1012, 100. The method described in Hoshino begins with depositing metal films onto a transparent glass substrate 1 (shown in yellow in Figure 4(p)). Ex. 1005, 0040; Ex. 1012, 101. A mask and etch step forms gate bus lines 3 (lower red) and auxiliary capacitive bus lines 4 (lower red), and a subsequent deposition and mask step forms the gate electrodes 2 (lower red). Id. at Formation of these structures corresponds to 589 Patent, Claim step 1(a). Ex. 1012,

54 Next, corresponding to Claim step 1(b), a gate insulating film (small orange area on top of gate electrode 2) is formed over the gate electrode by oxidizing the surface of the gate electrode. Ex. 1005, 0042, Figs. 3(b), 3(e); Ex. 1012, 102. Then, and also corresponding to Claim step 1(b), insulating film 5 (orange) is formed by plasma chemical vapor deposition (CVD). Ex. 1005, 0043, Fig. 3(e); Ex. 1012, 103. After these gate insulating layers are formed, an operation semiconductor

55 film 6 (dark green in Figure 4(p), above) 7 and channel protective film (blue, also in Figure 4(p)) are added, also by plasma CVD. Ex. 1005, 0043; Ex. 1012, 104. After etching only the protective film, Hoshino forms layers of n + amorphous silicon ( a- Si, 8a and 8b) (bright green), Titanium ( Ti, 9a, 9b), and Molybdenum ( Mo, 18a, 18b). Ex. 1005, 0046, Fig. 4(p); Ex. 1012, 104. A photolithography step patterns the two upper metal layers (titanium and molybdenum), semiconductor film 6, and n + films 8a-8b. Formation and etching of semiconductor film 6 and n + films 8a-8b corresponds to Claim step 1(c) because disclosure of forming both semiconductor 6 and films 8a-8b are within the BRC of forming an operative semiconductor. Ex. 1012, 105. Formation and etching of the upper metal layers into the source electrodes (9a, 18a) (upper red), drain electrodes (9b, 19b) (upper red), and drain bus lines (19) 7 Hoshino 0043 describes forming an operation semiconductor, which is likely a translation issue and which the POSA would understand to refer to an operative semiconductor. Ex. 1012, 104, n.9. An operative semiconductor is a term in Claim 1(c), but the 589 Patent has defined operative semiconductor to include both the i- type a-si and n + -doped a-si. The operative semiconductor 6 and n + a-si layers 8a and 8b together correspond to the operative semiconductor required by Claim 1, step (c)

56 (upper red) corresponds to Claim step 1(d). Ex. 1005, 0047, Fig. 3(h); Ex. 1012, 105. Next, an ITO layer is deposited on the substrate and etched to form a pixel electrode 21 (blue) and a contact at the end of the drain bus line (also blue). Ex. 1005, 0047, Fig. 4(p) (see above); Ex. 1012, 105. Formation of the pixel electrode in this way corresponds to Claim step 1(g). Ex. 1012, 105. Just before the final photolithography step, a protective film 12 (purple) made of SiN is deposited. Forming this film corresponds to Claim step 1(e). Ex. 1005, 0048, Figs. 4(p), (q), (r); Ex. 1012, 105. A mask is then used to etch through-holes in several locations, which corresponds to Claim step 1(f). Ex. 1012, 106. One hole is etched above the pixel electrode (see Ex. 1005, Fig. 4(l), item 23a), and another is etched above the terminal

57 of the gate bus line (Fig. 4(m), item 23b; Fig. 4(q), item 3a), through the protective film and gate insulation film. See Ex. 1005, Fig. 4(m), (q); Ex. 1012, 106. Third, a hole is etched above the terminal of the auxiliary capacitive bus line (Fig. 4(q), item 4a), again through the protective film and gate insulation film. Ex. 1005, Fig. 4(m), (q); Ex. 1012, 106. Fourth, a hole is etched above the terminal of the drain bus line (Fig. 4(n), item 23d), through the protection film only. See Ex. 1005, Fig. 4(n), (r); Ex. 1012, 106. Hoshino Figures 4(p), (q), and (r) (see preceding pages) illustrate the result of the disclosed method. Ex. 1012, 106. Regarding Claim 2, Hoshino discloses an ACBL in facing relation to (i.e., overlapping) the pixel electrode. Ex. 1012, 108. Figure 4(o) (shown at right) makes clear that the ACBL 4 (red) and pixel electrode 21 (blue) overlap. Ex. 1005, Fig. 4(o); Ex. 1012, 108. As shown

58 in Figure 4(q) (above), the ACBL (4 and 4a) and its terminal are formed on the transparent substrate 1. Ex. 1012, 108. Above the ACBL layer is the gate insulating film 5 (orange). Ex. 1012, 108. Figure 4(p) shows the pixel electrode 21 (blue) above the gate insulating film 5 (orange). Ex. 1012, 108. Hoshino thus discloses the method of Claim 1 further comprising an ACBL in facing relation to the pixel electrode with gate insulation in between. Ex. 1012, 108. Hoshino further discloses removing protection and insulating film above the terminal of the ACBL. Ex. 1012, 109. As shown in Figure 4(m) and (q), hole 23c is etched above the ACBL terminal. Ex 1012, 109. The hole is cut through protection film 12 and gate insulating film 5. Ex 1012, 109. As to Claim 3, Hoshino discloses forming a multilayered gate insulation film in Claim 1, step (b). As described above, the surface of the gate electrode is oxidized, forming a film of TiO (2a) approximately 20 nm thick, and then a gate insulation film (5) is formed. Ex. 1005, , Fig. 3(e) (shown here); Ex. 1012, 110. Hoshino also teaches Claim 4, which requires the operative semiconductor to be formed nearby the place at which the drain bus line and gate bus line overlap. As

59 shown in Figure 4(o) (shown at right), the operative semiconductor (green) is formed near the overlap of the gate bus line (3, red) and drain bus line (19, blue). Ex. 1012, 111. Claim 6 requires a pixel electrode made of ITO. Hoshino also discloses this limitation, expressly describing that pixel electrode 21 is formed from etching of the ITO film. Ex. 1005, 0047, Fig. 4(p); Ex. 1012, 112. The claim chart below further demonstrates how Hoshino, as understood by the POSA, discloses all of the limitations of Claims 1-4 and 6. Claim 1 Hoshino (Ex. 1005) A method of Method For Producing Thin Film Transistor Matrix. Ex. 1005, fabricating a Title. thin film (OBJECT) It is an object to provide a method relating to a transistor method for producing a thin film transistor matrix in which a bus array line is led out of the terminal with one photolithography step. comprising a (CONSTITUTION) The present invention is constituted of a step transparent for forming a gate electrode (2) on a transparent insulating insulating substrate (1) and a gate bus line (3) that connects to the gate substrate, a electrode (2), a step for forming, in a region excluding the end of plurality of the gate bus line (3), gate insulating films (5a, 5b, 5c) with a thin film multilayer structure in which an insulating layer that is the etch transistors stop layer during protective film etching is the topmost layer or an formed on said intermediate layer, a step for forming, after element formation, a substrate in a protective film (12) on the entire surface and forming a mask (13) matrix, a gate having holes in a pixel electrode formation region, the end of the bus line gate bus line and the end of the drain bus line on the protective connected to film (12), and a step for etching to remove the protective film (12) gate electrodes from the holes, and then accumulating a transparent conductive of said thin film on the entire surface to form a pixel electrode (15a) that film connects to the source electrode, a gate bus line contact (15b) and transistors, a a drain bus line contact (15d). Ex. 1005, Abstract

60 Claim 1 Hoshino (Ex. 1005) drain bus line connected to drain electrodes of said thin film transistors, and a pixel electrode driven by said thin film transistors, said method comprising the steps of: (a) forming said gate electrodes and said gate bus line on said transparent insulating substrate; (b) forming a gate insulating film over said substrate; The present invention relates to a method for producing a thin film transistor (hereinafter referred to as TFT) matrix. Ex. 1005, Ex. 1005, Figs. 5, 3(a), 3(d), 3(g), 4(k), 4(o). (0047)... Contact layers (8a, 8b), source electrodes (9a, 18a) and drain electrodes (9b, 18b) are formed to separate the elements, and a drain bus line (10) connected to the drain electrode (18b) is formed. Ex. 1005, (0040)... Using a resist film (not illustrated) as a mask, wet etching is carried out with a liquid mixture of phosphoric acid and hydrofluoric acid as the etchant, and gate bus lines (3, 3a) and auxiliary capacity bus lines (4, 4a) are formed. Ex. 1005, (0040) Refer to Fig 3(a) (c) [ ] A DC magnetron sputtering device is used to continuously form Al films (3, 4) 100 nm thick and Ti films (3a, 4a) 50 nm thick on the glass substrate (1) which has been washed and otherwise surface treated. Using a resist film (not illustrated) as a mask, wet etching is carried out with a liquid mixture of phosphoric acid and hydrofluoric acid as the etchant, and gate bus lines (3, 3a) and auxiliary capacity bus lines (4, 4a) are formed. The resist is then peeled off and washed. (0041) Next, a Ti film (2) 100 nm thick is formed, a resist film (not illustrated) is used as a mask for reactive ion etching with BCl3 + Cl2 gas as the etchant, and a gate electrode (2) is formed. Then the resist film is peeled off and washed. Ex. 1005, (0042) Next, the glass substrate (1) is heated to approximately 300 C in an atmosphere of oxygen and nitrogen to create plasma, oxidizing the surface of the gate electrode (2) and forming a TiO 2 film (2a) approximately 20 nm thick. The steps to this point are the same as in embodiment 1. (0043) Refer to Fig. 3(d) (f) [ ]... [A] gate insulating film (5), an operation semiconductor film (6) and a channel protective film (7) are continuously formed with the plasma CVD method on the entire surface. The gate insulating film (5) is an SiN film that is, for example, 400 nm thick, the operation semiconductor film (6) is an a-si film that is, for example, 15 nm thick, and the channel protective film (7) is an SiN film that is, for example, 140 nm

61 Claim 1 Hoshino (Ex. 1005) thick. Ex. 1005, (c) forming an (0043) Refer to Fig. 3(d) (f) [ ]... [A]n operation operative semiconductor film (6) and a channel protective film (7) are semiconductor continuously formed with the plasma CVD method on the entire on said gate surface. The... operation semiconductor film (6) is an a-si film insulating film; that is, for example, 15 nm thick[.] Ex. 1005, (0046) In an atmosphere of SiH4 doped with PH3, n+ a-si films (8a, 8b) that are, for example, 50 nm thick, are formed with the (d) forming source electrodes, said drain electrodes, and said drain bus line of said thin film transistors on said gate insulating film and said operative semiconductor; (e) forming a protection film over said substrate; (f) removing a portion of both said gate insulating film and said protection film, located above a terminal of said gate bus line, and removing a portion of said protection film plasma CVD method.... Ex. 1005, (0046) In an atmosphere of SiH4 doped with PH3, n+ a-si films (8a, 8b) that are, for example, 50 nm thick, are formed with the plasma CVD method, and Ti films (9a, 9b) that are, for example, 50 nm thick, and Mo films (18a, 18b) that are, for example, 300 nm thick are formed with the DC sputtering method. (0047) Then a resist film (not illustrated) for source/drain electrode formation is formed and used as a mask to reaction ion etch the Mo films, the Ti films, the n+ a-si films and the a-si film (6) using BCl3 + Cl2 gas as the etchant. Contact layers (8a, 8b), source electrodes (9a, 18a) and drain electrodes (9b, 18b) are formed to separate the elements, and a drain bus line (10) connected to the drain electrode (18b) is formed. Ex. 1005, (0048) Refer to Fig. 4(k) (n) [ ]... [A]n SiN film (12) is formed as a protective film on the entire surface[.] Ex. 1005, (0048) [ ]... [A] resist mask (22) is formed thereon [on the protective film 12] having a hole (23a) on the pixel electrode (21), a hole (23b) in the end of the gate bus line (3), a hole (23c) in the end of the auxiliary capacity bus line (4) and a hole (23d) in the end of the drain bus line (19). (0049) Refer to Fig. 4 (o) (r) [ ] The SiN film (12) is etched with BHF (buffered hydrofluoric acid) using the resist mask (22) as a mask. ITO acts as the etch stop layer at the pixel electrode (21) and the end of the drain bus line (19), and the polyimide film (20) acts as the etch stop layer at the end of the gate bus line (3) and the end of the auxiliary capacity bus line (4). Ex. 1005,

62 Claim 1 Hoshino (Ex. 1005) located above a terminal of said drain bus line; and (g) forming said pixel electrode on said substrate Next, an ITO film that is, for example, 300 nm thick is formed on the entire surface with the sputtering method, a mask is used to etch the ITO film, and a pixel electrode (21) connected to the source electrode (18) and a contact (19a) connected to the end of the drain bus line (19) are formed. Ex. 1005, Claim 2 Hoshino (Ex. 1005) The method as See Claim 1, above. set forth in (0040) Refer to Fig 3(a) (c) [ ] A DC magnetron sputtering claim 1, device is used to continuously form Al films (3, 4) 100 nm thick wherein said and Ti films (3a, 4a) 50 nm thick on the glass substrate (1) which thin film has been washed and otherwise surface treated. Using a resist film transistor (not illustrated) as a mask, wet etching is carried out with a liquid array further mixture of phosphoric acid and hydrofluoric acid as the etchant, comprising an and gate bus lines (3, 3a) and auxiliary capacity bus lines (4, 4a) auxiliary are formed. Ex. 1005, capacitive bus (0043) Refer to Fig. 3(d) (f) [ ]... [A] gate insulating film (5), line formed on an operation semiconductor film (6) and a channel protective film said substrate (7) are continuously formed with the plasma CVD method on the in facing entire surface. The gate insulating film (5) is an SiN film that is, relation to said for example, 400 nm thick, the operation semiconductor film (6) is pixel electrode an a-si film that is, for example, 15 nm thick, and the channel with said gate protective film (7) is an SiN film that is, for example, 140 nm insulating film thick. Ex. 1005, therebetween, Next, an ITO film that is, for example, 300 nm thick is formed on and wherein a the entire surface with the sputtering method, a mask is used to portion of both etch the ITO film, and a pixel electrode (21) connected to the said gate source electrode (18) and a contact (19a) connected to the end of insulating film the drain bus line (19) are formed. Ex. 1005, and said (0048) [ ]... [A] resist mask (22) is formed thereon [on the protection film, protective film 12] having a hole (23a) on the pixel electrode (21), located above a a hole (23b) in the end of the gate bus line (3), a hole (23c) in the terminal of end of the auxiliary capacity bus line (4) and a hole (23d) in the said auxiliary end of the drain bus line (19). capacitive bus (0049) Refer to Fig. 4 (o) (r) [ ] The SiN film (12) is etched with

63 Claim 2 Hoshino (Ex. 1005) line, is also BHF (buffered hydrofluoric acid) using the resist mask (22) as a removed in mask. ITO acts as the etch stop layer at the pixel electrode (21) and said step (f). the end of the drain bus line (19), and the polyimide film (20) acts as the etch stop layer at the end of the gate bus line (3) and the end of the auxiliary capacity bus line (4). Ex. 1005, Ex. 1005, Figs. 3(g), 3(h), 4(o), 4(p), 4(q). Claim 3 Hoshino (Ex. 1005) The method as See Claim 1, above. set forth in (0042) Next, the glass substrate (1) is heated to approximately claim 1, 300 C in an atmosphere of oxygen and nitrogen to create plasma, wherein said oxidizing the surface of the gate electrode (2) and forming a gate insulating TiO 2 film (2a) approximately 20 nm thick. The steps to this film is formed point are the same as in embodiment 1. to have a (0043) Refer to Fig. 3(d) (f) [ ]... [A] gate insulating film (5), multi-layered an operation semiconductor film (6) and a channel protective film structure in (7) are continuously formed with the plasma CVD method on the said step (b). entire surface. The gate insulating film (5) is an SiN film that is, for example, 400 nm thick, the operation semiconductor film (6) is an a-si film that is, for example, 15 nm thick, and the channel protective film (7) is an SiN film that is, for example, 140 nm thick. Ex. 1005, Ex. 1005, Figs. 3(b), 3(e), 3(h). Claim 4 Hoshino (Ex. 1005) The method as See Claim 1, above. set forth in Ex. 1005, Figs. 3(g), Fig. 4(k), 4(o). claim 1, (FIG. 3) (a) (j) are plan and cross-section views (part 1) of the wherein said order of steps showing the second embodiment, with Fig. 3(a, d, g) operative being plan views, Fig. 3(b, e, h) being cross-section views of A-A, semiconductor Fig. 3(c, f, i) being cross-section views of B-B and Fig. 3(j) being is formed a cross-section view of C-C. Ex at Brief Description of the where said gate Drawings (following 0052). bus line overlaps said drain bus line. Claim 6 Hoshino (Ex. 1005) The method as See Claim 1, above

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