Parylene-Based Double-Layer Gate Dielectrics for

Transcription

1 Supporting Information Parylene-Based Double-Layer Gate Dielectrics for Organic Field-Effect Transistors Hyunjin Park, Hyungju Ahn, Jimin Kwon, Seongju Kim, and Sungjune Jung *,, Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), 77 Cheongam-Ro, Nam-Gu, Pohang, 37673, Republic of Korea Pohang Accelerator Laboratory, 77 Cheongam-Ro, Nam-Gu, Pohang, 37673, Republic of Korea Department of Creative IT Engineering, Pohang University of Science and Technology (POSTECH), 77 Cheongam-Ro, Nam-Gu, Pohang, 37673, Republic of Korea Department of Mechanical Engineering, Pohang University of Science and Technology (POSTECH), 77 Cheongam-Ro, Nam-Gu, Pohang, 37673, Republic of Korea S-1

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3 Experimental Details Materials: The parylene C (dix-c, Daisankasei Co., Ltd.) and F (VT4, Suzhou Chireach Biomedical Technology Co., LTD.) were prepared as gate dielectric layers. For the bank solution, Cytop (CTL-809M, Asahi Glass) was dissolved in a fluorinate solvent (CT-Solv.180, Asahi Glass) in the volume ratio of 1:2. The semiconductor solution was prepared with a blend of 2.5 mg ml -1 TIPS-pentacene (> 99.9 %, Ossila) and 1.25 mg ml -1 PS (MW ~280,000, Sigma-Aldrich) dissolved in mesitylene (98 %, Sigma-Aldrich). Device Fabrication: The BGTC OFET was fabricated on a glass substrate (Eagle XG, Corning). A 50-nm-thick aluminum gate electrode was thermally evaporated through a shadow mask on the substrate. Parylene films were deposited by means of CVD, using a parylene coater (OBT-PC300, OBANGTECHNOLOGY), at near room temperature. For the DLGD structure, parylene F is deposited and parylene C is deposited. Then, Cytop solution was printed with dispenser equipment (350PC, Musashi Engineering, Inc.) to form the bank layer. The substrate and nozzle temperatures were maintained at 40 C during the dispensing process. After bank layer printing, the device was annealed S-3

4 on a hotplate at 100 C for 10 min to remove residual solvent. The solution of TIPSpentacene:PS blends was printed in the area defined by the bank layer with dispenser equipment. The substrate and nozzle temperatures were maintained at 30 C during the dispensing process. After semiconducting layer printing, the device was annealed on a hotplate at 70 C for 10 min to remove residual solvent. Finally, a 40-nm-thick silver was thermally evaporated through a shadow mask for the source and drain electrodes with channel width and length of 1000 and 50 μm, respectively. Characterization: The thickness of parylene-based films was measured with a stylus surface profiler (DektakXT, Bruker). The electrical characteristics of OFETs were measured in a dark box using a semiconductor parameter analyzer (4200-SCS, Keithley) under ambient conditions. The V GS was normalized to the thickness of parylene-based dielectrics as 1 MV cm -1. The capacitance of MIM capacitors was measured with a precision LCR meter (ZM2376, NF Corporation) within the frequency range of 1 Hz to 1 MHz. AFM images were recorded in tapping mode using an SPM system (Veeco Dimension Nanoscope V, Digital Instruments/Veeco Metrology Group). The crystalline of TIPS-pentacene thin films was observed with a POM (Leica S-4

5 DM2700M, Leica). The 2D GIXRD was measured at the 3C beamline of the Pohang Acceleration Laboratory in Korea. S-5

6 Table S1. Device and electrical parameters of OFETs with parylene SLGDs and DLGDs. The dielectric thickness (t d ), dielectric constant (ε r ), characteristics trapping time constant (τ), and dispersion parameter (β) are averaged over five devices. The threshold electric-field (E TH ), field-effect mobility (μ FET ), on/off current ratio (I on /I off ), and subthreshold swing (SS) are averaged over ten devices. X [t C (t C + t F ) -1 ] t d [nm] ε r at 10 Hz E TH [MV cm -1 ] μ FET [cm 2 V -1 s -1 ] I on /I off [ 10 6 ] SS [V decade - 1 ] τ [ 10 4 s] β 1 (C) S-6

7 (F) * V GS = t d [nm] E GS [MV cm -1 ] * V TH = t d [nm] E TH [MV cm -1 ] S-7

8 Figure S1. Dielectric constants of MIM capacitors with various thickness ratios of parylene DLGDs as a function of frequency. S-8

9 Figure S2. (a-e) AFM images of parylene-based gate dielectrics, where X is the thickness ratio. S-9

10 Figure S3. (a-e) DI water CA measurement images of parylene-based gate dielectrics, where X is the thickness ratio. S-10

11 Figure S4. (a-e) POM images of TIPS-pentacene thin films on parylene-based gate dielectric, where X is the thickness ratio. S-11

12 Figure S5. (a-e) 2D GIXRD patterns of TIPS-pentacene thin films on parylene-based gate dielectrics, where X is the thickness ratio. S-12

13 Figure S6. Out-of-plane XRD patterns of TIPS-pentacene thin films on parylene-based gate dielectrics. S-13