Fabrication and Device Simulation of Single Nano-Scale Organic Static Induction Transistors

Transcription

1 IEICE TRANS. ELECTRON., VOL.E89 C, NO.12 DECEMBER PAPER Special Section on Towards the Realization of Organic Molecular Electronics Fabrication and Device Simulation of Single Nano-Scale Organic Static Induction Transistors Noboru OHASHI a), Masakazu NAKAMURA, Norio MURAISHI, Masatoshi SAKAI, Nonmembers, and Kazuhiro KUDO, Member SUMMARY A well-defined test structure of organic static-induction transistor (SIT) having regularly sized nano-apertures in the gate electrode has been fabricated by colloidal lithography using 130-nm-diameter polystyrene spheres as shadow masks during vacuum deposition. Transistor characteristics of individual nano-apertures, namely nano-sit, have been measured using a conductive atomic-force-microscope (AFM) probe as a movable source electrode. Position of the source electrode is found to be more important to increase current on/off ratio than the distance between source and gate electrodes. Experimentally obtained maximum on/off ratio was 710 (at V DS = 4V, V GS = 0 and 2 V) when a source electrode was fixed at the edge of gate aperture. The characteristics have been then analyzed using semiconductor device simulation by employing a strongly non-linear carrier mobility model in the CuPc layer. From device simulation, source current is found to be modulated not only by a saddle point potential in the gate aperture area but also by a pinch-off effect near the source electrode. According to the obtained results, a modified structure of organic SIT and an adequate acceptor concentration is proposed. On/off ratio of the modified organic SIT is expected to be 100 times larger than that of a conventional one. key words: organic SIT, nanostructures, AFM, colloidal lithography, semiconductor device simulation 1. Introduction Recently, organic field-effect transistors (OTFTs) has been studied extensively by aiming at an application for flexible, low cost and low energy consumption devices. However, various technological problems, such as low on-state conductance, low switching speed, etc., still remain. These negative characters firstly come from the low carrier mobility of organic semiconductors. To compensate the low mobility, fabrication of organic static-induction transistors (OSITs) has been demonstrated [1] [3]. SIT is one of the verticaltype transistors and has advantages of high speed switching and high on-state conductance due to its short channel and wide conduction area nature. In the previous works on OSITs, slit-type gate electrodes were embedded in organic active layers. Since carriers flow through the gap of the gate electrode and the conductance is modulated by changing the saddle-point potential which is in response to the gate bias, the size of the gate gap is critically important for the transistor operation. However, in the early studies, the gate gap was not controlled precisely because it was formed using a slit mask set in front of the substrate with a certain space to arrow the defocusing of edges [1]. To optimize the device structure to obtain the best performance of the OSIT, comparative study between the transistor characteristics and well-defined structures is necessary. In this paper, we have therefore fabricated a test structure of OSIT having regularly sized nano-apertures in the gate electrode by colloidal lithography [4], where polystyrene (PS) spheres are used as shadow masks during vacuum deposition. This technique is valuable to form porous thin-films on large-area flexible substrates [5], [6]. In this study, transistor characteristics of individual nanoapertures were measured using a conductive atomic-forcemicroscope (AFM) probe as a source electrode [7]. Here, we call the device, which is composed of the AFM prove as a source, a single nano-aperture as a gate gap and a bottom electrode as a drain, nano-sit. As compared with slitgate-type OSITs, we could measure reproducible currentvoltage (I-V) characteristics excluding undesirable factors such as a damage caused by metal deposition [8] and a leakage current through pin holes. Using this test device, we have studied the relationship between the device geometry and characteristics. The characteristics was then analyzed using semiconductor device simulation to elucidate the operation mechanism of OSITs and to further improve device performance, current on/off ratio in particular. 2. Experimental 2.1 Device Fabrication and Characterization Figure 1 shows the device structure of nano-sit. Nano-SITs are composed of gold (Au) as drain electrodes, copper ph- Manuscript received June 10, The authors are with Chiba University, Chiba-shi, Japan. a) 03um5609@graduate.chiba-u.jp DOI: /ietele/e89 c Fig. 1 Sectional structure of nano-sit and measurement circuit. Copyright c 2006 The Institute of Electronics, Information and Communication Engineers

2 1766 IEICE TRANS. ELECTRON., VOL.E89 C, NO.12 DECEMBER 2006 thalocyanine (CuPc) as active layers, porous aluminum (Al) as gate electrodes, and gold-coated AFM probes as source electrodes. The diameter of the tip contact area was around 100 nm, which corresponds to the size of the source electrode. A drain electrode and the first CuPc layer of 80 nm thickness were fabricated on a glass substrate by vacuum evaporation under a vacuum of Pa. An Al film with regularly-sized nano-apertures was then fabricated using colloidal lithography. The fabrication process of the gate electrode was as follows: (1) PS spheres of 130 nm in diameter (Immutex UC-PS, JSR) were dispersed in a solvent (water:ethanol = 1:3), (2) the solution was spread over the CuPc layer by spin coating, (3) a 20 nm-thick Al thin-film was evaporated in vacuum, and (4) the PS spheres were removed by sonication in methanol. Figure 2 shows an AFM topographic image of the porous Al film thus prepared. Finally, the second CuPc layer was deposited on the sample. The thickness of the second CuPc layer was varied from 40 to 70 nm. Transistor characteristics of nano-sits were measured using source-meters (Model 617 and Model 6430, Keithley) connected to a vacuum-type AFM instrument (JSTM- 4100, JEOL) [6]. To define the position of the probe source electrode, the location of the embedded gate gap must be confirmed. For this purpose, current images were observed prior to the transistor measurements by applying a negative drain voltage while keeping the gate voltage to zero. Then the conductive AFM probe was fixed to the position near the gate gap and transistor characteristics were measured. 2.2 Device Simulation Two-dimensional semiconductor device simulator (Device- Meister WV, Mizuho Information & Research Institute) was used to simulate transistor operation. Typical physical parameters of α-cupc [9] were selectedandusedfor this study. Carrier mobility and acceptor density are varied sensitively by experimental factors such as deposition conditions or purity of the material. We therefore used an actual acceptor density of the sample measured by capacitance-voltage measurement. Carrier mobility was however changed as a free parameter. In order to reproduce non-linear I-V characteristics, we adopted a Poole-Frenkel type electric-fielddependent mobility model. The equation was given by E µ = µ 0 exp, (1) E 0 where µ 0 and E 0 are constants of the materials and E is the electric field. E 0 is an important factor to reproduce nonlinearity. The curvature of I-V characteristics was fitted by changing E 0 value, then, the magnitude of current by changing µ 0 value. Fig. 2 Surface topography of a porous Al film used for a gate electrode. 3. Results and Discussion 3.1 Experimental Results Topographic and current images simultaneously taken near an embedded nano-aperture are shown in Fig. 3. The brighter spot corresponds to the area where larger sourcedrain current flows. Since the size of the probe contact area is more than 100 nm in diameter, it is conceivable that part of the contact area is still inside the gate gap even if the center of the probe was fixed at edge of the gate gap. This is why the brighter spot appeared larger than the diameter of the aperture, 130 nm. Thus, we can find the embedded nanoaperture of the gate electrode. Transistor characteristics of the nano-sit were then measured at the edge (A or C) or the Fig. 3 (a) Topographic and (b) current images simultaneously taken near an embedded nano-aperture of the gate electrode under the bias voltages of V DS = 4VandV GS = 0V.

3 OHASHI et al.: FABRICATION AND DEVICE SIMULATION 1767 Fig. 4 Transistor characteristics of nano-sits of which thicknesses of the second CuPc layers are (a) 40, (b) 55, and (c) 70 nm. gap, on-state current decreased slowly while on/off current ratio increased drastically. The maximum on/off ratio was 710 at V DS = 4 V. Accordingly, shifting the source electrode to the edge of the gate gap is more effective to gain high on/off ratio than changing the second layer thickness. 3.2 Device Simulation Fig. 5 Transistor characteristics of a nano-sit in which the source electrode is located at the edge of the gate gap. The nano-sit is the same as that used in Fig. 4(b), i.e. the second layer thickness is 55 nm. center (B) of the gate gap. First, dependence of transistor characteristics on the thickness of the second CuPc layer, i.e. the distance between source and drain electrodes, was examined. Those obtained with (a) 40, (b) 55, and (c) 70 nm-thick second layers are shown in Fig. 4. Dimensions of other parts are as shown in Fig. 1, and the source electrode (AFM probe) was fixed at center of the gate gap. Features in these graphs are the nearly exponential curves, relatively high threshold voltage, and the gate bias modulation. By comparing these characteristics, one can see a clear tendency that the on-state current decreases by increasing the second layer thickness. The offstate current however decreases more rapidly, which results in the increase of on/off ratio with the thickness of the second layer. The maximum on/off ratio was 40 at V DS = 4V and the second layer thickness of 70 nm. The on/off ratio depended more on the position of source electrode. Figure 5 shows transistor characteristics of a nano-sit in which the source electrode was located at the edge of the gate gap. The characteristics were taken at the position (A) indicated in Fig. 3, while those in Fig. 4(b) were taken at the position (B) of the same sample. As the probe position shifted from the center to outside of the gate To elucidate the improvement mechanism of the on/off ratio and to optimize the device design for further improvement, semiconductor device simulation modified for organic semiconductors was used. First of all, the experimentally obtained transistor characteristics should be well-reproduced by choosing an appropriate simulation model. There are two considerable approaches to reproduce the strongly nonlinear I-V curves. One is to insert a strongly non-linear contact resistance at the source/semiconductor junction and the other is to introduce strongly non-linear carrier transport into the CuPc active layer itself. We have tried to fit the transistor characteristics by these two approaches and concluded that the former model is not suitable for this device. One of the characteristic feature, high threshold voltage, could not be reproduced only by the non-linear contact resistance. Accordingly, the latter model is used for the present study. Figure 6 shows the experimental, which is taken from Fig. 4(b), and calculated transistor characteristics of the nano-sit. For Poole-Frenkel type non-linear conduction, E 0 and µ 0 were optimized to be 1500 V/cm and cm 2 /Vs, respectively. Considering that a typical E 0 value is in the order of 10 4 V/cm [10], the value used here is relatively small and results in the strong non-linear character under the actual range of electric field in the device. It suggests that the CuPc film in the gate gap contains a number of grain boundaries and defects. In the simulation shown in Fig. 6, effective carrier mobility in the channel region at on-state (V GS =0V,V DS = 4V)was(3 7) 10 5 cm 2 /Vs, which is comparable value to those reported for CuPc TFTs [11]. Experimental characteristics also exhibit relatively linear I-V at off-state. It appeared only when the AFM probe was located at the center of the gate gap. This feature was not able to be reproduced by the simulation. This current component would be a leakage current through defects or

4 1768 IEICE TRANS. ELECTRON., VOL.E89 C, NO.12 DECEMBER 2006 (a) Fig. 6 Comparison between calculated and experimental output characteristics of nano-sit. The parameters used in the simulation were: [second layer thickness] = 55 nm, [acceptor density] = cm 3, E 0 = 1500 V/cm, and µ 0 = cm 2 /Vs. Other dimensions are the same as Fig. 1. (b) Fig. 8 Calculated carrier density distribution at off state,v GS = 2V,V DS = 4 V, for the devices with the source electrode is located (a) at the center and (b) at the edge of gate gap. Fig. 7 Relationship between current on/off ratio and position of source electrode. The width of the source was 100 nm and the zero position means that the center of the electrode is located exactly above the edge of the gate gap. grain boundaries. Since it is not apparent when the AFM probe is located at the edge of the gate gap, we neglected this linear component in the analyses hereafter. Figure 7 shows on/off ratio vs. position of source electrode. As shifting position of the source electrode to the edge, off current rapidly decreases and on/off ratio drastically increases when both source and gate edges are aligned. The tendency is the same as experimental results. The reason of the drastic increase of on/of ratio is explained by calculated carrier density distribution as shown in Fig. 8. The saddle point which act as a bottle neck of carrier path is seen in both devices. Besides the saddle point, a pinch-off point appears when source electrode is located at the edge of gate gap. The pinch-off point also suppresses the current conduction and results in the higher on/off ratio. Fig. 9 Sectional structure of a modified OSIT according to the findings in this work. 3.3 Discussion for Further Improvement of OSIT The obtained results suggest that the position of source electrode is an important factor to increase on/off ratio by the help of a pinch-off effect near the source electrode. Since it is difficult to achieve a high on/off ratio in OSITs as in OTFTs, we should utilize this effect. Here we propose a modified structure of OSIT which is shown in Fig. 9. According to the device simulation with the structure in Fig. 9, on/off ratio of the modified OSIT was 100 times larger than

5 OHASHI et al.: FABRICATION AND DEVICE SIMULATION 1769 Table 1 Calculated on/off ratios with acceptor density and gate-gap width as parameters. On/off ratio was defined by I DS (V GS = 0V)/I DS (V GS = 2 V) (roman numbers) or I DS (V GS = 1V)/I DS (V GS = 0V) (italic numbers) according to the operational mode, normally on or off, respectively. that of the conventional one. Table 1 shows the calculated on/off ratios with acceptor density and gate-gap width as parameters. On state current of normally-off-type devices (displayed as italic numbers) tend to be very small, which diminishes the advantage of OSITs. In this table, one can notice that the acceptor density is also an important parameter to optimize the device characteristics. We therefore propose that the conditions enclosed by a dashed rectangle are the best. 4. Conclusion The relationship between the device geometry and characteristics of OSITs was studied by a comparative study of experiment and simulation. Test structures of OSIT having regularly sized nanoapertures in the gate electrodes were fabricated by colloidal lithography, and transistor characteristics of individual nano-sits were measured using conductive AFM probe as a movable source electrode. Position of the source electrode was found to be more important to increase current on/off ratio than thickness of the second CuPc layer. The device where source electrode was fixed at the edge of gate gap exhibited highest on/off ratio of 710. Semiconductor device simulation was adapted to the CuPc nano-sit by employing a strongly non-linear carrier mobility model in the CuPc layer. The simulation revealed that a pinch-off effect near the source electrode caused the drastic increaseof on/off ratio while maintaining a large onstate current. According to the findings in this work, we have proposed an optimized structure of OSITs, of which on/off ratio is expected to be about 100 times large as conventional OSITs. [2] K. Kudo, M. Iizuka, S. Kuniyoshi, and K. Tanaka, Device characteristics of lateral and vertical type organic field effect transistors, Thin Solid Films, vol.393, pp , Aug [3] K. Kudo, S. Tanaka, M. Iizuka, and M. Nakamura, Fabrication and device characterization of organic light emitting transistors, Thin Solid Films, vol.438, pp , Aug [4] P. Hanarp, D.S. Sutherland, J. Gold, and B. Kasemo, Control of nanoparticle film structure for colloidal lithography, Colloids and Surfaces A, vol.214, pp.23 36, March [5] N. Hirashima, N. Ohashi, M. Nakamura, and K. Kudo, Fabrication of organic vertical-type field effect transistors using polystyrene spheres as evaporation mask, Proc. Int. Symp. Super Functionality Organic Devices, IPAP Conference Series, vol.6, pp , May [6] K. Fujimoto, T. Hiroi, and M. Nakamura, Organic static induction transistors with nano-hole arrays fabricated by colloidal lithography, e-journal of Surf. Sci. Nanotech., vol.3, pp , Nov [7] M. Nakamura, H. Yanagisawa, S. Kuratani, M. Iizuka, and K. Kudo, Characterization of organic nano-transistors using a conductive AFM probe, Thin Solid Films, vol.438, pp , Aug [8] M. Nakamura, N. Goto, N. Ohashi, M. Sakai, and K. Kudo, Potential mapping of pentacene thin-film transistors using purely electric atomic-force-microscope potentiometry, Appl. Phys. Lett., vol.86, pp , March [9] Dielectric constant was 4.3, band gap was 1.6 ev, electron affinity was 3.6 ev, effective DOS was cm 3,diffusion potential was 1 V, respectively. [10] F.T. Reis, D. Mencaradlia, S. Ould Saad, I. Segury, M. Oukachmih, P. Jolinat, and P. Destruel, Electrical characterization of ITO/CuPc/Al diodes using temperature dependent capacitance spectroscopy and I-V measurements, J. Non-Cryst. Solids, vol , pp , June [11] T. Sumimoto, K. Hiraga, S. Kuniyoshi, K. Kudo, and K. Tanaka, Evaluation of electrical properties in p, n-type organic thin films by in-situ field effect measurements, Mol. Cryst. Liq. Cryst., vol , pp , Acknowledgements This work was supported by Grant-in Aid for Scientific Research (No ) and 21st Century Center of Excellence Program Frontier of Super-Functionality Organic Devices from Ministry of Education, Culture, Sports, Science and Technology. Noboru Ohashi received B.E. and M.E. degrees from Chiba University in 2003, 2005, respectively. He is currently working toward the Dr. Eng. degree. He is a member of the Japan Society of Applied Physics. References [1] K. Kudo, D.X. Wang, M. Iizuka, S. Kuniyoshi, and K. Tanaka, Organic static induction transistor for display devices, Synth. Met., vol.111, pp.11 14, June 2000.

6 1770 IEICE TRANS. ELECTRON., VOL.E89 C, NO.12 DECEMBER 2006 Masakazu Nakamura received B.E., M.E., and Dr. Eng. degrees from Osaka University in 1988, 1990, and 1997, respectively. From 1990 to 2000, he was with Toray Research Center, Inc. Since 2000, he has been an associate professor with the Department of Electronics and Mechanical Engineering, Chiba University. From 1994 to 1997, he joined Joint Research Center for Atom Technology (JRCAT) as a research scientist. He is a member of the Japan Society of Applied Physics. Norio Muraishi received B.E. and M.E. degrees from Chiba University in 2002, 2004, respectively. Since 2004, he has been with Ricoh Co. Ltd. Masatoshi Sakai received Dr. Eng. degree from Nagoya University in He is currently a research associate at Chiba University. He is a member of the Physical society of Japan and the Japan Society of Applied Physics. Kazuhiro Kudo received B.E., M.E., and Dr. Eng. degrees from Tokyo Institute of Technology in 1977, 1979, and 1982, respectively. From 1982 to 1987, he was with Matsushita Electric Industrial Co. Ltd. He was with the Department of Electrical Engineering, Chiba University as an associate professor. Since 1998, he has been a professor with the Department of Electronics and Mechanical Engineering, Chiba University. From 1998 to 1999, he joined as a visiting professor of Physics department, University of London. He is a member of the Institute of Electrical Engineering of Japan and the Japan Society of Applied Physics.