Resistive Switching Memory in Integration

Transcription

1 EDS Mini Colloquim WIMNACT 39, Tokyo Resistive Switching Memory in Integration Ming Liu Institute of Microelectronics, CAS Feb.7, 2014

2 Outline Motivation RRAM Integration Self-Rectifying RRAM 1D1R Integration 1k HfO 2 based RRAM Test Chip Summary

3 Flash Memory Concepts proposed by D. Kahng and S. M. Sze, Bell Lab, 1967 Kahng and S. M. Sze, Bell Systems Technical Journal 46 (1967) Uses Fowler-Nordheim tunneling to erase the memory Uses CHE or FN to program the memory Total Semiconductor market : 300 B US$ in 2011; Memory occupied 23.9% semiconductor market. 3

4 Flash Integration Flash - E 2 PROM (NOR Type) Control Gate Floating Gate Select Gate SG (D) NAND - E 2 PROM Control Gate Select Gate WL1 WL2 WL3 WL14 WL15 WL16 SG (S) Drain Bit Line WL1 WL2 Source Basic unit Drain Bit Line SG (D) WL1 WL2 WL3 WL4 Basic unit Source WL3 WL16 WL14 WL15 WL16 SG (D) 1 Transistor / 1 Bit 18 Transistor / 32 Bit NOR Type Flash: High Speed,Random Access per bit, Code Storage NAND Type Flash : High Density,Block Access, Data Storage

5 Challenges of Flash scaling down Crosstalk effect Low No. of electron Leakage current Physical limitations exist! leakage current High voltage operations Charge storage requirements of the dielectrics and reliability issues Slow writing speed

6 3D Flash Architecture Vertical structure

7 1 st Mass Production of 3D VNAND

8 Integration Trend of Memory 3D integration is the mainstream to enhance the storage density of memory. 3D RRAM is one of the most promising candidates of Flash memory.

9 Outline Motivation RRAM Integration Self-Rectifying RRAM 1D1R Integration 1k HfO 2 based RRAM Test Chip Summary

10 What is RRAM? MIM: resistive switching under electric field Bipolar switching Unipolar switching Advantages of RRAM: Simple device structure(mim) Good compatibility with CMOS process Easy scaling down to 8 nm Large on/off ratio (10 3 ~10 6 ) Fast operating speed(~ns) Good endurance (>10 6 ) Good retention (>10years)

11 Opportunities for RRAM Expected RRAM specs Required memory specs Working memory Embedded NVM Stand-alone NVM Working memory Embedded NVM Stand-alone NVM RRAM RRAM is not suitable for working memory, but quite competitive for embedded and stand-alone NVM application.

12 RRAM Integration: Active or Passive Array Active 6~8F 2 Ref. A. Chen, et al., IEDM 2005, pp Passive 4F 2 Ref. ITRS Passive crossbar array structure is the best choice for high storage density application!

13 3D RRAM Integration 2D RRAM crossbar 4F 2 3D RRAM crossbar 4F 2 /n Passive crossbar array structure is the good choice for high storage density application! Ref. ITRS 2010.

14 Sneaking Current in RRAM Integration Vread Open Vread Open HRS HRS HRS LRS V=0 V=0 HRS HRS LRS LRS Open Open When reading a HRS cell, if the surrounded cells are all in HRS, the reading is correct. If some surrounded cells is in LRS and form a sneak current path, the HRS cell will be misread as LRS.

15 How to Suppress Sneaking Current (1). 1D1R solution (2). 1S1R 1E-3 (3). Self- Rectifying Current (A) 1E-5 1E-7 200x 20x bit 1 bit 0 Ref. I. G. Baek, et al., IEDM 2005; B. Cho, et al.,adv. Mater E Voltage (V)

16 How to Suppress Sneaking Current Solutions Schematic of the crosstalk effect 1R: RRAM with self-rectifying effect 1 Selector + 1 RRAM Requirements of Selector: Asymmetric I-V curve High current density (J selector >J reset,rram ) High rectifying ratio or nonlinear factor Compatible with CMOS Low fabrication temperature (<400 set by the copper BEOL)

17 Outline Motivation RRAM Integration Self-Rectifying RRAM 1D1R Integration 1k HfO 2 based RRAM Test Chip Summary

18 RRAM with (Au/ZrO 2 :Au/n+-Si) Au Au NC ZrO n + -Si Device structure Current (A) Set 1 4 Reset TEM image of the device Voltage (V) Typical I-V characteristics of the Au/ZrO 2 :nc-au/n+ Si device, it showed low switch voltage and producible set and reset process. Q Zuo, et al., J. Appl. Phys., 106, (2009).

19 RRAM with (Au/ZrO 2 :Au/n+-Si) Current (A) V V Resistance ( ) V V Time (s) Cycle (#) The Au/ZrO 2 :Au/n+-Si device demonstrated very good cycling and retention characteristics. Q Zuo, et al., J. Appl. Phys., 106, (2009).

20 Self-rectifying Characteristics Current (A) Current (A) V Voltage (V) Switching number The Au/ZrO 2 :Au/n+ Si has a very good rectifying characteristics at LRS. I on /I off ratio is 700. After 100 cycling, its rectifying characteristics is still keeping very well. Q Zuo, et al., J. Appl. Phys., 106, (2009).

21 Comparison in 2 2 Array Resistance ( ) Ron in sigle cell Roff in sigle cell Ron without rectifying Roff without rectifying Ron with rectifying Roff with rectifying 10 1 A B C Group A: HRS and LRS of Single device; Group B: HRS and LRS of 2 2 array without rectifying; Group C: HRS and LRS of 2 2 array with rectifying

22 Self-Rectifying RRAM for WORM Application Resistance ( ) After PRG Before PRG Time (s) Cumulative Probability (%) Area 200x200 m 2 1V After PRG Before PRG x Current (A) 1 V Large rectifying ratio (>10 4 ) Data retention Uniformity of the states before and after program R HRS /R LRS >10 6 High uniformity Long retention time IEEE Electron Device Letters, 2010, 29, 43 US Patent 2012/ Al

23 Self-Rectifying Mechanism Ag CF Ag Ag n + -Si HfO 2 Based on the TEM results, we demonstrated that the CF composition in the oxideelectrolyte-based RRAM mainly consists of the electrode materials when using Cu, Ag or Ni as electrode. By using semiconductor as another electrode, RRAM with self-rectifying effect can be obtained, and the rectifying characteristics is controlled by metal and semiconductor electrodes. Adv. Mater. 24, 1844, 2012

24 The Role of Silicon for Self-Rectifying RRAM n + -Si/a-Si/Ag n + -Si/ZrOx/Pt NiSi/HfOx/TiN APL 2009 JAP 2009 VLSI 2011 Metallic property of conductive filaments Ohmic contact with metal electrode No rectifying characteristics. Highly doped Si is generally needed to guarantee a Schottky contact of CF with c-si. Crystal Si is not expected for 3D integration.

25 A-Si to achieve Self-rectifying RRAM Pt TE BE 4200-SCS DC bias/control Why a-si? WO3 a-si Cu SiO2 Si(100) Pt WO3 a-si Cu 100 nm Requirements of low fabrication temperature (<400 set by the copper BEOL) for 3D integration..cmos compatible;. Low temperature fabricate;. Cheap;. well controlled process;

26 Memory Characteristics Current (A) 10-4 RESET o C 1st cycle after 10 3 pulses after 10 6 pulses Voltage (V) The device exhibits bipolar switch behavior, there is 20 times window between HRS and LRS; Very excellent stability, even after 10 3 and 10 6 switch pulses, there is still no obvious shift.

27 Uniformity of DTD and CTC Resistance ( ) HRS 10x window LRS C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 Voltage (V) SET Voltage RESET Voltage C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 Excellent switching uniformity in cycle-to-cycle and device-to-device. (data were collected from 100 switching cycles in random selected 10 cells) IEEE Electron Device Letters, 2013, 34, 229 International Memory Workshop, 2013 Patent NO

28 Programming Speed and Cycling 10 8 Temp= Temp=25 Resistance ( ) HRS(bit 0 ) LRS(bit 1 ) Resistance ( ) HRS(bit 0 ) LRS(bit 1 ) 1E-8 1E-7 1E-6 1E-5 P/E pulse width (sec) P/E cycles (#) Very fast switching speed, 30 ns both for write and erase; Endurance is more than 10 9 switching cycles. IEEE Electron Device Letters, 2013, 34, 229 International Memory Workshop, 2013 Patent NO

29 Self-Rectifying Characteristics Obvious rectifying characteristics for both HRS and LRS after forming, rectify ratio is 200; Excellent reliability and reproducibility. IEEE Electron Device Letters, 2013, 34, 229 International Memory Workshop, 2013 Patent NO

30 Origin of Self-Rectifying Behavior Current (A) R LRS ~10 5 Ω@0.5V Vf~3.2 V If~10-4 A Pt WO3 V Rini~10 9 Ω@0.5V WCu Voltage (V) Current (A) R LRS ~10 5 Ω@0.5V Vf~6.5 V If~10-4 A Pt WO3 V a-si Rini~10 9 Cu Voltage (V) Current (A) R LRS <10 2 Ω@0.5V Vf~7 V If>10-3 A Pt a-si V Rini<10 6 Ω@0.5V Cu Voltage (V) Both of Cu/WO 3 /Pt and Cu/a-Si/Pt control sample show symmetrical I-V. Rini of Cu/WO 3 /Pt is three orders higher than that of Cu/a-Si/Pt, same with Pt/WO 3 /a-si/cu device, The WO 3 layer is switched into LRS after forming, while the a-si layer still keeps in HRS. The rectifying property of Cu/a-Si/WO 3 /Pt device is from the Schottky contact of CF in WOx with a-si.

31 Mechanism of Resistive Switching The process of O 2- ions trapping andde-trapping on the vacancy site is attributed to the switching behavior. Filament composed of oxygen vacancy is formed in SET process. The recombination of O 2- ions with vacancy corresponds to the RESET process.

32 Comparison of Various Technologies The self-rectifying RRAM is a promising candidate for high density application.

33 Outline Motivation RRAM Integration Self-Rectifying RRAM 1D1R Integration 1k HfO 2 based RRAM Test Chip Summary

34 Comparison of Endurance and Reset Current in unipolar and bipolar RRAM Ref [7]: Ta 2 O 5 /TiO 2 Ref [8]: HfO x Endurance cycles Bipolar RRAM devices: High endurance Low reset current Ref [5]: Ta 2 O 5 /TaO x Ref [6]: TiO x /HfO x Ref [5]: ZrO x /Ta 2 O 5 /AlO Ref [8]: HfO x /AlO y Unipolar RRAM devices: Low endurance High reset current Reset current (ma) Most 1D-1R integration only suitable for Unipolar RRAM. [7] Y. Sakotsubo, et al., VLSI, p. 87, [8] X.A. Tran, et al., VLSI, p. 44, 2011.

35 Bipolar 1D-1R Integration Diode: Ni/TiO x /Ti RRAM: Pt/HfO 2 /Cu Y. T. Li, et al., Nanoscale, 5, 4785 (2013).

36 Diode and bipolar RRAM characteristics (a) Typical I-V characteristics of Ti/TiO x /Ti and Ni/TiO x /Ti devices. (b) Bipolar resistive switching characteristic of the Pt/HfO 2 /Cu RRAM cell. Y. T. Li, et al., Nanoscale, 5, 4785 (2013).

37 Bipolar Resistive Switching of 1D1R Integration The 1D-1R device exhibits bipolar switching characteristic, a selfcompliance behavior can be achieved during the set process; After 100 DC cycling, its bipolar switching characteristics is still keeping very well. Y. T. Li, et al., Nanoscale, 5, 4785 (2013).

38 Uniformity and Retention Bipolar 1D-1R demonstrated very good uniformity and retention characteristics.

39 Programming Speed Voltage (V) Read V1 RRAM OSC Diode V2 Read Rs Reset pulse 100ns/+3V Read HRS Transition from Transition from HRS to LRS LRS to HRS again Set pulse 100ns/-2.5V Time ( s) V1 V2 Fast switching speed, 100 ns both for write and erase.

40 Multi-level storage and low power consumption Current (A) V set =-1.5V V set =-2V V set =-2.5V V reset, I V reset, I V reset, I Voltage (V) Obvious Multi-level storage can be realized by controlling different voltage during the SET process (V set ) ; Reset current (ma) I reset is found to reduce with the decrease of V set AVR: average value STD: standard deviation AVR=0.55mA STD=0.21mA V set =-1.5V AVR=3.17mA STD=1.39mA V set =-2V AVR=9.22mA STD=0.98mA V set =-2.5V

41 Scalability of Ni/TiOx/Ti Selecting Diode The forward current density is over 10 4 A/cm 2 at 1V for 2 2 μm 2 active area; An even higher forward current density over 10 6 A/cm 2 is expected from a smaller area of nm 2. Y. T. Li, et al., Nanoscale, 5, 4785 (2013).

42 Comparison References RRAM RRAM Type Diode Diode Type Compliance current This work Cu/HfO 2 /Pt Bipolar W/TiO x /Ni Schottky Self-compliance [1] Pt/NiO/Pt Unipolar Pt/CuO/IZO/Pt p-n junction External current limiter [2] Pt/NiO/Pt Unipolar Pt/CuO/IZO/Pt p-n junction GIZO transistor [3] Pt/TiO x /Pt Unipolar Pt/TiO x /Pt Schottky External current limiter [4] Pt/ZnO/Pt Unipolar Pt/NiO/ZnO/Pt p-n junction External current limiter [4] Pt/ZnO/Pt Unipolar Pt/WO 3 /ZnO/Pt Tunnel barrier External current limiter 1D1R structure generally can only use unipolar RRAM device, but the bipolar RRAM has superior performance than unipolar RRAM. This work is a first demonstration of a 1D1R structure using bipolar RRAM and Schottky diode.

43 Outline Motivation RRAM Integration Self-Rectifying RRAM 1D1R Integration 1k HfO 2 based RRAM Test Chip Summary

44 1kb RRAM Test Chip Demo RRAM cell Integration solution Cell_fail Write_fail 端口信号线 内部控制信号线 ready clk rst trigger operation Control unit Write_trigger P/E read Write_finish readdata writedata Latch_addr read readout SA trigger P/E read finish WD WD_ref WD 数据线 模拟信号 SA_ref SA data Latch read SA_ref SA WD_ref WD P/E DMA_port1 DMA DMA ARRAY DMA_port2 addr DMA_wlv Address[9:0] Latch Rreadref1 Rreadref2 Rprogramref1 Rprogramref2 Reraseref1 Reraseref2 Periphery circuit design 1kb RRAM test chip

45 Device Structure and Bipolar Switching (c) BL Table. 1 M5 V4 M4 V3 M3 V2 M2 V1 M1 CT 500 nm D TE HfO 2 4 nm Cu 5 nm G S RRAM WL SL Current (A) 400.0u 200.0u u u u Operation V BL V SL V WL Forming SET RESET SET GND GND GND Icc RESET Voltage (V)

46 1kb RRAM Test Chip Demo Layout outlook Data writing

47 Summary RRAM with crossbar architecture attracts significant interests due to its excellent scalability and 3D integration for high-density application. The big challenge of this structure is how to eliminate crosstalk issue. Self-rectifying RRAM and RRAM integration with 1D1R architecture can suppress crosstalk leakage greatly. RRAM with excellent memory performance and good reproducibility are demonstrated with a self-rectifying characteristics, which can suppress crosstalk leakage greatly. Bipolar 1D-1R devices also exhibits good features in uniform switching, satisfactory data retention, fast speed, as well as excellent scalability. HfO 2 based 1k test chip was demonstrated.

48 Thanks for your attention!