Mixed Ionic Electronic Conduction (MIEC) based Access Devices for 3-D Crosspoint Memory
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1 Mixed Ionic Electronic Conduction (MIEC) based Access Devices for 3-D Crosspoint Memory Kumar Virwani, G. W. Burr, R. S. Shenoy, G. Fraczak, C. T. Rettner, A. Padilla, R. S. King, K. Nguyen, A. N. Bowers, M. Jurich, M. BrightSky, E. A. Joseph, A. J. Kellock, N. Arellano, B. N. Kurdi, and K. Gopalakrishnan IBM Almaden Research Center IBM T. J. Watson Research Center Flash Memory Summit 2013
2 Motivation Outline MIEC access device characteristics DC IVs and pulse currents Large array yield and variability Thickness and CD scaling Crosspoint roles of an access device (AD) Long term leakage of un-selected and half-selected states Write operations and recovery to low leakage Read operations Conclusions 1
3 Need for an Access Device Access device needed in series with memory element Cut off current sneak paths that lead to incorrect sensing and wasted power Typically diodes used as access devices Could also use devices with highly non-linear I-V curves 2
4 Access Device for 3D Crosspoint Memory Basic Requirements High ON-state current density > 10 MA/cm 2 for PCM RESET Low OFF-state leakage ON/OFF ratio > 10 7 for large arrays BEOL-compatibility < 400 C processing for 3D memory with multi-layer stacking NVM memory element Access Device (AD) Bipolar operation (required for robust RRAM) à not possible with conventional diodes MIEC-based Access Devices satisfy all 4 criteria à ADs that could enable 3D for any low voltage NVM 3
5 4 Top Electrode MIEC Current - Cu-ion Motion Bottom Electrode + 100µA 10µA 1µA 100nA 10nA 1nA 100pA 200nm inert TEC 10pA 80nm BEC 1pA (K. Gopalakrishnan et al, 2010 VLSI Tech. Sym.) Cu-containing MIEC (Mixed-Ionic-Electronic-Conductor * ) Mobile Cu-ions à transport in E-field Cu interstitials/vacancies can act as dopants and modulate local electron/hole concentration, Schottky barriers at interfaces, etc. TEC MIEC BEC MIEC Device Operation Voltage [V] Applied voltage leads to Transient Cu-ion drift, followed by Steady-state electron/hole current (Gopalakrishnan et al, 2010 VLSI Tech. Sym.) *See I. Riess, Solid State Ionics, 157, 1 (2003) for MIEC models.
6 180 nm CMOS Front-End à 1T1S (1 transistor + 1 selector) MIEC Access Device Fabrication As-deposited 5 Post-CMP CMP process for MIEC material with modified commercial Cu slurry à self-aligned MIEC diode-in-via (DIV) in 200 mm wafer process (Shenoy et al, 2011 VLSI Tech. Sym.)
7 MIEC Device Performance Voltage margin = 1.1V Low (< 10pA) OFF state leakage currents near 0V bias High (> 400μA) ON state currents à current density > 15MA/cm 2 > 10 7 ON / OFF ratio Wide (0.8V) window with low current (<100pA) Endurance > 10 8 ~100μA currents (Shenoy et al, 2011 VLSI Tech. Sym.) 6
8 MIEC Yield & Variability 100% yield and tight distributions in 512 kbit 1T-1MIEC array 7 (Burr et al, 2012 VLSI Tech. Sym.)
9 C-AFM Short Loop for MIEC ADs C-AFM tip TEC Thickness scaling SiN MIEC d min oxide Si wafer BEC CD scaling 8 Conducting atomic force microscopy with doped diamond and / or solid Pt probes Minimal wiring requiring few lithography steps Diode-in-via (DIV) structure the same as transistor arrays à Vary SiN x dielectric thickness for thickness scaling (Virwani et al, 2012 IEDM)
10 Thickness scaling of MIEC ADs High-yield array of C-AFM short-loop devices Good Bad Good 9 SiN oxide Si wafer C-AFM tip TEC MIEC BEC d min MIEC devices work well down to 11nm thickness (6nm may be too thin) (Virwani et al, 2012 IEDM)
11 MIEC Access Devices CD Scaling Scaled MIEC devices also offer 1e7 ON-OFF contrast and high speed Conduct ~150μA pulse currents CDs <30nm demonstrated no lower CD limit yet identified (Virwani et al, 2012 IEDM) 10 MIEC Access Devices for 3-D Crosspoint Memory Flash Memory Summit 2013
12 AD requirements for 3D Crosspoint Memory ü High ON-state current density >10 MA/cm 2 for PCM / RRAM RESET ü Low OFF-state leakage current >10 7 ON/OFF ratio, and wide low-leakage (< 100pA) voltage zone to accommodate half-selected cells in large arrays ü Back-End process compatible <400C processing to allow 3D stacking ü Bipolar operation needed for optimum RRAM operation ü variability? ü yield? ü scalability? ü co-integration with NVM? ü turn-on speed for write? ü endurance? ü manufacturability? long-term leakage? turn-off speed? turn-on speed for read? PCM or RRAM Access Device
13 Crosspoint roles of the MIEC device Log(I) ~½V m 200mV (across un-selected ADs biased NEGATIVE) ~10pA un-select leakage V r V r V c 1. un-selected state shown to be stable over hours V r 12 MIEC VAccess c Devices for V3-D c Crosspoint Memory Flash Memory Summit 2013
14 0Volts Crosspoint roles of the MIEC device V Log(I) ~½V m (across half-selected ADs of same column) ~½V m 200mV (across un-selected ADs biased NEGATIVE) ~½V m (across half-selected ADs of same row) ~10nA half-select leakage ~10pA un-select leakage V V r V r V c 1. un-selected state must be stable over long periods 2. half-selected states must be maintained while same row (or column) is accessed 13 V r 0 à shown to be stable for seconds: millions of successive read/writes MIEC VAccess c Devices for V3-D c Crosspoint Memory Flash Memory Summit 2013
15 Log(I) 0Volts Crosspoint roles of the MIEC device ~½V m + 350mV + (across selected diode) V across selected cell + Required NVM voltage + + voltage drop across wiring V ~3-60uA Read or Write current Log(I) ~½V m (across half-selected ADs of same column) ~½V m 200mV (across un-selected ADs biased NEGATIVE) ~½V m (across half-selected ADs of same row) ~10nA half-select leakage ~10pA un-select leakage V 14 V r V r 0 V r V c 1. un-selected state must be stable over long periods 2. half-selected states must be maintained while same row (or column) is accessed 3. selected (for read or write) must pass desired current quickly then return to low leakage MIEC VAccess c Devices for V3-D c Crosspoint Memory Flash Memory Summit 2013
16 Write pulses depend on overvoltage Turn-ON delay (50uA write pulses) can be greatly reduced by overvoltage Current [ua] Current [ua] 0us 1us 2us No overvoltage Time 3us 4us 5us mV 0 50 uprobe & pad 25 VDUT AFG MIEC 100nm low VWL SCOPE + 750mV Ω V 0ns 250ns (DC) ns Time 750s 1us (Burr et al, 2013 VLSI Tech. Sym.) MIEC Access Devices for 3-D Crosspoint Memory Flash Memory Summit 2013
17 Native response at lower voltages Measured current 50uA 25uA 0uA 50uA 25uA 0uA 50uA 25uA 0uA 16 Native 0.9V 0 5us 10us Native 0.7V 0 1ms 2ms Native 0.5V 0 5ms 10ms (Burr et al, 2013 VLSI Tech. Sym.)
18 Measured current 17 How fast do devices recover after writes? 50uA 25uA 0uA 50uA 25uA 0uA 50uA 25uA 0uA Native 0.9V 0 5us 10us Native 0.7V 0 1ms 2ms Native 0.5V 0 5ms 10ms 50uA then 50uA 0.9V 0.9V 0 1us 2us 0 1us 2us 0.7V 0.7V 0 1us 2us 0 1us 2us 1us 0.5V 0 1us 2us 0 1us 2us then Time After a strong write pulse (50uA for 1us), MIEC AD response is affected: devices remain ON don t require any overvoltage acceleration to turn back ON at lower voltages where leakage should be undetectable, measurable currents can persist. (Burr et al, 2013 VLSI Tech. Sym.)
19 MIEC device recovery dynamics 5uA Leakage current (at 600mV) 3uA Post write (50uA) recovery (Fig. 8) Dotted fits are guide-to-the-eye only 18 1uA 300nA 0 Post read (6uA) recovery (Fig. 11) Static leakage at 600mV 0 500ns 1us 1.5us Recovery time at 0V Recovery even after a 50uA write pulse takes place within 1-2us (Burr et al, 2013 VLSI Tech. Sym.)
20 Read turn-on also accelerated by overvoltage Current 10uA 5uA 0uA 10uA 5uA 0uA 0us Current No overvoltage Time 10us 20us 30us 40us 50us + 300mV Current 15uA 10uA 100ns 50ns 25ns 10uA 5uA 0uA + 600mV 5uA 10uA 5uA 0uA V 0ns 500ns 1us 1.5us 2us 0uA 0ns 100ns Time 0ns 100ns 0ns 100ns Time Time Time Thick (d min ~75 nm) MIEC ADs can be turned ON rapidly with large overvoltage à transition from half-select to ~10uA read currents in <50ns (Burr et al, 2013 VLSI Tech. Sym.)
21 Conductive-AFM testing à thinner MIEC devices uprobe & pad VDUT AFG C-AFM tip MIEC dmin SCOPE 196Ω 100nm VWL TEC dmin MIEC BEC Proximate BEC contact (DC) dmin ~ 75 nm dmin ~ 47 nm 36 nm 28 nm 11 nm (Burr et al, 2013 VLSI Tech. Sym.) 20 5µm MIEC Access Devices for 3-D Crosspoint Memory Flash Memory Summit 2013
22 Thinner MIEC devices are inherently faster 10uA d min = 11nm 28nm Current 5uA 36nm 0uA 47nm 21 Time 0ns 500ns 1us (Burr et al, 2013 VLSI Tech. Sym.)
23 Thin MIEC devices à fast at modest overvoltage 100ns shaped pulse (max. overvoltage: 350mV) 10uA d min = 28nm Current 5uA 0uA Time -100ns 0ns 100ns 200ns 22 (Burr et al, 2013 VLSI Tech. Sym.)
24 Summary: Mixed-Ionic-Electronic-Conduction (MIEC) Access Device Strengths High enough ON currents for PCM cycling of PCM has been demonstrated Low enough OFF current for large arrays Very large (>>1e10) endurance for typical 5uA read currents Voltage margins > 1.5V with tight distributions à sufficient for large arrays CMP process demonstrated 512kBit arrays demonstrated w/ 100% yield Scalable to <30nm CD, <12nm thickness Capable of 15ns write, 50ns read Highly stable in un-/half-select conditions Weaknesses Maximum voltage across companion NVM during switching must be low (1-2V) à influences half-select condition and thus achievable array size Endurance during NVM programming is strongly dependent on programming current Gopalakrishnan, VLSI 2010 Shenoy, VLSI 2011 Burr, VLSI 2012 Virwani, IEDM 2012 Burr, VLSI 2013
25 Acknowledgements Teya Topuria, Phil Rice, Eugene Delenia, Leslie Krupp, David Hepner, and David Erpelding - expert analytical and processing support Microelectronics Research Laboratory (MRL) at IBM T. J. Watson Research Center Stanford Nanofabrication Facility (SNF) Colleagues at IBM Almaden and IBM T. J. Watson Research Centers Management support from Dr. Chung Lam, Dr. Winfried Wilcke, Dr. Spike Narayan, and Dr. T. C. Chen Thank you for your attention! Questions? Please contact kvirwan@us.ibm.com 24
26 For more information & MIEC team Overview of storage class memory and MIEC à G. W. Burr, K. Virwani, R. S. Shenoy, Gloria (Ho) Fraczak, C. T. Rettner, A. Padilla, R. S. King, K. Nguyen, A. N. Bowers, M. Jurich, M. BrightSky, E. A. Joseph, A. J. Kellock, N. Arellano, B. N. Kurdi and K. Gopalakrishnan, "Recovery Dynamics and Fast (Sub-50ns) Read Operation with Access Devices for 3D Crosspoint Memory Based on Mixed-IonicElectronic-Conduction (MIEC)," Symposium on VLSI Technology, T6.4, (2013). K. Virwani, G. W. Burr, Rohit S. Shenoy, C. T. Rettner, A. Padilla, T. Topuria, P. M. Rice, G. Ho, R. S. King, K. Nguyen, A. N. Bowers, M. Jurich, M. BrightSky, E. A. Joseph, A. J. Kellock, N. Arellano, B. N. Kurdi and Kailash Gopalakrishnan, Sub-30nm scaling and high-speed operation of fully-confined Access-Devices for 3-D crosspoint memory based on Mixed-Ionic-Electronic-Conduction (MIEC) Materials, IEDM Technical Digest, 2.7, (2012). Geoffrey W. Burr, Kumar Virwani, R. S. Shenoy, Alvaro Padilla, M. BrightSky, E. A. Joseph, M. Lofaro, A. J. Kellock, R. S. King, K. Nguyen, A. N. Bowers, M. Jurich, C. T. Rettner, B. Jackson, D. S. Bethune, R. M. Shelby, T. Topuria, N. Arellano, P. M. Rice, Bulent N. Kurdi, and K. Gopalakrishnan, Large-scale (512kbit) integration of Multilayer-ready Access-Devices based on Mixed-Ionic- Electronic-Conduction (MIEC) at 100% yield, Symposium on VLSI Technology, T5.4, (2012). R. S. Shenoy, K. Gopalakrishnan, Bryan Jackson, K. Virwani, G. W. Burr, C. T. Rettner, A. Padilla, Don S. Bethune, R. M. Shelby, A. J. Kellock, M. Breitwisch, E. A. Joseph, R. Dasaka, R. S. King, K. Nguyen, A. N. Bowers, M. Jurich, A. M. Friz, T. Topuria, P. M. Rice, and B. N. Kurdi, Endurance and Scaling Trends of Novel Access-Devices for Multi-Layer Crosspoint Memory based on Mixed Ionic Electronic Conduction (MIEC) Materials, Symposium on VLSI Technology, T5B-1, (2011). K. Gopalakrishnan, R. S. Shenoy, C. T. Rettner, K. Virwani, Don S. Bethune, R. M. Shelby, G. W. Burr, A. J. Kellock, R. S. King, K. Nguyen, A. N. Bowers, M. Jurich, B. Jackson, A. M. Friz, T. Topuria, P. M. Rice, and B. N. Kurdi, "Highly-Scalable Novel Access Device based on Mixed Ionic Electronic Conduction (MIEC) Materials for High Density Phase Change Memory (PCM) Arrays," Symposium on VLSI Technology, 19.4, (2010). G. W. Burr, Matt J. Breitwisch, Michele Franceschini, Davide Garetto, K. Gopalakrishnan, B. Jackson, B. Kurdi, C. Lam, Luis A. Lastras, A. Padilla, Bipin Rajendran, S. Raoux, and R. Shenoy, "Phase change memory technology," Journal of Vacuum Science & Technology B, 28(2), , (2010). G. W. Burr, B. N. Kurdi, J. C. Scott, C. H. Lam, K. Gopalakrishnan, and R. S. Shenoy, "An overview of candidate device technologies for Storage-Class Memory," IBM Journal of Research and Development, 52(4/5), 449 (2008). S. Raoux, G. W. Burr, M. J. Breitwisch, C. T. Rettner, Y. Chen, R. M. Shelby, M. Salinga, D. Krebs, S. Chen, H. L. Lung, and C. H. Lam, "Phase-change random access memory a scalable technology," IBM Journal of Research and Development, 52(4/5), 465,, (2008). Rich Freitas and Winfried Wilcke, Storage Class Memory, the next storage system technology, IBM Journal of Research and Development, 52(4/5), 439, (2008).
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