RRAM for Future Memory and Computing Applications

Transcription

1 RRAM for Future Memory and Computing Applications Ming Liu Key Lab. of Microelectronic Devices &Integrated Technology, (CAS) Institute of Microelectronics, CAS Macao University, July7.2018

2 Outline 2 Computing System s Challenge RRAM: Memory/Storage Convergence RRAM: Memory/Computing Convergence Summary

3 Big Data comes 3 Media Big Data Machine EB ZB ~180 ZB in 2025 now Social Historical Data volume in ZB Forecast Source: IDC From 2013, data nearly doubles every two years In 2025, it s expected that the data volume will reach ~180 ZB Powerful and Energy Efficiency Computing to Process Big Data!

4 Computing challenge in Big Data era 4 CPU Input Memory Bus Output Computing performance improved times in past 60 years. Device: energy efficiency slow down due to power constraints at 22nm; Architecture: CPU and memory was physically separated. An increasing performance gap between CPU and memory, which is known as the memory wall.

5 Memory hierarchy 5 5X 20X 2000X 50X Processor <1 ns Speed SRAM 5 ns ~ MB DRAM 100 ns ~ GB Flash 20 μs ~100GB Hard Drive 1 ms ~ TB Volume Memory Hierarchy: tradeoff between speed and density, bottleneck to limit the computing performance. Universe memory: blurs distinction between memory (fast, volatile and low density) and storage (slow, non-volatile and high density). NVM play more important role in future computing!

6 NVM: a solution to future computing 6 CPU Memory Storage Memory Hierarchy: more date movement CPU NVM M/S Convergence: less data movement NVM- CPU M/C Convergence: no data movement Near term: M/S convergence by new NVM, simplifying memory hierarchy, less data movement, high performance; Long term: M/C convergence by integrating memory and computation in one device, Memory Wall problem can be solved.

7 Outline 7 Computing System s Challenge RRAM: Memory/Storage Convergence RRAM: Memory/Computing Convergence Summary

8 RRAM: a promising candidate 8 RRAM: Promising Emerging Memory Technology!

9 RRAM s history and future 9 First array demonstration First publication Journal of Applied Physics, 1962,33:9 History Panasonic IEDM Elpida announces RRAM chip, aims to enter market 2015 Now RRAM for embedded application Near future IMECAS RRAM for standalone application Future RRAM for computing Our group started the joint development of RRAM in embedded and stand-alone applications with industry from 2015.

10 Probability (%) 28 nm RRAM integration 10 (1) W plug formation (2) Cell trench open (3) Deposit TMO/TE (4) CMP to form cell US Patent, One extra mask Resistance Initial resistance Ta IL Ti IL 0 nm 1.5 nm 3 nm 5 nm IL Thickness RRAM built between CT and Metal 1, W as BE, TMO as switching layer and M1 as TE Interfacial layer between TMO and TE: Initial Resistance more uniform and sensitive to the thickness of Ti or Ta ; Block TE migration at BEOL thermal process. PECVD, High T Q time, Ashing, alloy. More than 90 min annealing at 400 o C. 0 W/O W/ BEOL thermal budget Rinitial ( ) IEDM 2017, 36-39

11 Cumulative Probability (%) Electrical test on the 1T1R array LRS HRS SET: 3V/100ns RESET: -3V/100ns Read@RT Resistance ( ) HRS and LRS distribution in 1Mb array by 3V/100ns SET and -3V/100ns RESET pulse. IEDM 2017, 36-39

12 RRAM: a good choice for 3D stacking 12 3D X-point 3D V-RRAM Suitable for 3D integration;either in 3D X-point or BiCS 3D NAND like vertical array (VRRAM). RRAM devices linear I-V in LRS, unselected cells in LRS, sneaking current could be generated. A high performance nonlinear selector or self-selective RRAM cell.

13 Current (A) Solution for the sneak current issues 13 RRAM with Diode p-n type diodes, Schottky diodes, Heterojunction Generally, applying to the unipolar RRAM rectifying ratio is defined as R -V /R V W/TiO x /Ni diode with selfcompliance to integrate bipolar Cu/HfO 2 /Pt Nanoscle, 2013, 5:4785 RRAM with switch- based selector Mater insulator transition (MIT) Threshold switch (TS) threshold switch be as volatile switch applying to the unipolar or bipolar RRAM rectifying ratio is defined as R V/2 /R V Pd/TaO x /Ta/Pd with non-linearity of Nanoscle, 2015, 7:4964 Resistive switch: Mixed ionic electronic (MIEC) Complementary resistive switch structure Reduce off-state leakage TE (Pt) Tunneling layer (HfO ) TS layer (Doped HfO ) BE (Cu) Threshold Switching Voltage (V) applying to the unipolar or bipolar RRAM rectifying ratio is defined as R V/2 /R V Cu doped HfO x with nonlinearity >10 7, Jon>1MA/cm Jon >1 MA/cm 2 leakage current With Bipolar ~pa level operation IEDM 2015, >10 7 Self-Selective Cell Top Electrode (TE) Memory layer (ML) Selective layer (ML) Bottom Electrode(BE) Hybrid selective layer and memory layer Nonlinearity ratio is defined as I@Vread/Vread/2 The only choice for 3D Vertical RRAM. V rea d V read /2 Self-rectifying RRAM: Pt/WO 3 /a-si/cu Self-rectifying Au/ZrO 2 :nc- Au/n+-Si JAP, 2009, 106:073724; IEEE EDL, 2010, 31:344; IEEE EDL, 2013, 34:229

14 Current(A) Current(A) (A) Threshold Switching in Cu doped HfO x nm Cu plug Pt Single TS layer HfO2 Cu 5 nm TS layer + Tunneling layer HfO2 layer Doped (2nm) Doped (2nm)+undoped (2nm) Undoped (4nm) Modeling data Voltage(V) Threshold switching W annealing W/O annealing W annealing W/O annealing Memory switching Pt HfO 2 (2nm) Cu Voltage(V) Voltage (V) Reduce off-state leakage TE (Pt) Tunneling layer (HfO ) TS layer (Doped HfO ) BE (Cu) Threshold Switching Cu doped HfO x RRAM fabricated in 130nm BEOL. TS observed after annealing 30min at C. Introducing the 2nd tunneling layer, the leakage current was reduced by 5 orders. IEDM 2015,

15 Current (A) Bilayer Selector Device A Jon >1 MA/cm 2 leakage current ~pa level With Bipolar operation >10 7 Ideal Selector Voltage (V) Non-linearity >10 7, Jon>1MA/cm 2, Leakage current: pa level. Asymmetrical I-V curve might be resulted from the barrier height between top electrode and the tunneling layer. IEDM 2015,

16 Current (A) Cumulative Probability Resistance( ) Current(A) Selector Array Peak :1V Period:100ns Width:50ns Read@0.3V Read@0.6V Cycle number array Voltage (V) Consecutive DC switching cycles o C Distribution of on and off states current read@0.3v read@0.6v Current(A) read@0.3v read@0.6v Stress time(s) Endurance: 10 10, high temperature without degradation. 1 kb selector array with 1T-1S: High nonlinearity, High on-current density, tight distributions on and off current. Switching voltage variation, limited voltage window for reading. IEDM 2015,

17 Band Gap (ev) Interface type selector 17 (a) Ru TaOx TaOx-y W (b) Stoichiometric phase Ru TaOx W A B 5 nm (c) W Sub-oxide phase Trapezoidal Band TaOx Ru (d) Deficient Stoichiometry O/Ta ratio Good uniform and larger R window, Lower nonlinear and on-current. Trapezoidal band shape: high nonlinear and on-current compared to uniform or crested barrier. O- gradually changed TaO x layer: in surface, Ta was fully oxidative, oxygen component decreased as depth increased.

18 c na Percentiles Reference Line 300 Count Vread DC I-V cycles Turn-on On-state Voltage Selectivity -8 DC I-V Vm~3V cycles 10 Off-state /2Vread Voltage(V) Voltage(V) b = = e Probebility ormal Percentiles unt 1 = E-10 = E Turn-on voltage (V) selectivity (~5 104), lager A higher d current99.999density (~1 MA),e high f 1.0 voltage margin VM (3V) achieved curve is almost overlapped, After 10 successive DC cycles, each I-V standard deviation 10 is negligible, showing 0.6 excellent uniformity. 200 Percentiles Reference Line ercentiles Current(A) Current(A) a Normal Percentiles Device performance 95 70

19 Current(A) Current (A) Endurance and High T Operation V read =1.5V 1/2V read =0.75V V READ 1/2V READ Pulse Cycle (#) Stress time (s) Endurance as high as has been achieved. High temperature without degradation is allowed.

20 Current (A) Nonlinearity Current (A) Cumulative Probability (%) 1S 1R integration in 1kb Array S in 1k Array READ=0.75V READ=1.5V Voltage (V) Current (A) 10 4 nonlinearity was achieved in 1S1R with excellent uniformity. The read region is from 1.2V to 3.8V. The read region with nonlinearity higher than 10 3 is from 1.2V to 2.4V. 95 a c RRAM only 1S1R self-compliance Read region Voltage (V) -4 b d

21 Self-selective Cell (SSC) for VRRAM 21 Holes WL n+ 3 WL n+ 2 WL n+ 1 BL BL Memory layer Selective layer BL Electrode Self-selective cell WL n In 3D VRRAM, intermediate electrode is not allowed, memory cells on the same BL will be shorted, connecting with the same selector. The self-selective memory cell with rectifying or build-in nonlinearity is the only choice for 3D VRRAM.

22 Intensity (a.u.) Current (A) Voltage (V) Typical I-V curve of bilayer SSC 22 TiN CuGeS HfO 2 W Ti O Hf Cu S Ge W Depth (nm) TiN 50 nm TEM and EDS of bilayer device Ultra-low half-select leakage (<0.1 pa) HfO 2 CuGeS Very high nonlinearity (>10 3 ) Low operation current (below na) W Read region V P LRS HRS V S CuGeS thickness (nm) NL>10 3 Half-select Leakage<0.1pA Voltage (V) V P I-V curve of bilayer SSC V s

23 3D VRRAM Integration of SSC 23 (a) (b) (c) (d) (h) BL BL BL Step 1 Step 2 Step 3 Inline check 1 Inline check 2 Inline check 3 (e) (f) (g) BL (i) WL2-0~WL2-7 WL1-0~WL1-7 4x8x32 WL 1 WL 2 WL 3 WL 4 4 layer D VRRAM array HfO 2 /CuGeS bi-layer SSC with TE deposited on sidewall by sputtering. Each horizontal WL was opened by selective etching. Staircase WL contacts on each layer are formed. IEDM 2015,

24 Resistance ( ) Resistance ( ) Reliability test of SSC HRS SET with -4V/1μs RESET with 4V/500ns LRS -1.4 V Switching Cycles (#) V Time (s) Endurance of SSC with Retention of SSC for 10000s. Each layer devices exhibit stable and uniform characteristics. IEDM 2015,

25 Weight (%) 8 layer integration of 3D VRRAM 25 (a) (b) 100 nm 0.5 um 50 nm (c) Hf Ta W O (d) (e) TiN HfO 2 TaO x Ti TiN Distance (nm) W N Wt% O Wt% Hf Wt% Ta Wt% W Wt% Ti Wt% An 8-layer integration of 3D VRRAM achieved. High uniformity with on/off ratio ( 100 times) and 100x nonlinearity. IEDM 2017, 48-51

26 Outline 26 Computing System s Challenge RRAM: Memory/Storage Convergence RRAM: Memory/Computing Convergence Summary

27 Ways of Memory/computing convergence 27 Digital Analog Brain inspired Source: Nat, Borghetti J Source: EDL, Gao Li Source: Nat. Nanotech, Tuma T In memory computing, to eliminate the energy-intensive and timeconsuming data movement. Focused on identifying novel logic gate concepts with lower energy and area consumption. RRAM s advantages, as direct access by interconnect lines, capability to electrically reconfigure device, and nanoscale miniaturization.

28 RRAM-based logic unit V-R logic gate R-R logic gate 28 Source: Nanotech, E. Linn A considerable saving of static power Low requirement of device characteristics Input (voltage) and output (resistance) signals are physically different. Additional hardware burden, time and power dissipation will be cost. Source: Adv. Mater, P. Huang Only physical variable-resistance. gate cascading can be achieved easily Devices with high uniform characteristics are necessary

29 High uniformity of RRAM 29 Cu/α-Si/α-C/Pt cycles LRS@Read at 0.2V HRS@Read at 0.2V Positive Pulse@3.5 V 100ns Negative Pulse@ -2 V 100ns HRS Retention@100ºC Retention@85ºC > 10 years LRS Cu/α-Si/α-C/Pt shows good endurance, retention and uniformity.

30 NAND logic gate 30 Based on principle of resistance interaction, NAND operation was realized. Device A and B hold input signal and device R store operation result. NAND is basic operation of all the Boolean logic, other logics can achieve by proper cascading.

31 Implementation of 16 Boolean logic 31 Resistance states of RRAM for representation of logic 0 and 1 ; Via cascade of logic units, 16 Boolean logic can be implemented; 10 logic can be accomplished in 1 step.

32 Implementation of 16 Boolean logic 32 Implementation of NXOR is the most complex one, it needs 5 devices in 3 steps.

33 Realization of 1 bit full adder 33 1 bit full adder needs 5 devices and 1 reference resistor, operation is finished in 6 steps. Unpublished

34 Brain-inspired computing with RRAM Spiking neural networks 34 Synapses Neurons The human neural system is inherently memory/computation convergence. Basic elements: neurons(receives, processes, stores and transmits information via its synapses), and synapses (connections between neurons). In spiking neural networks (SNN), the neurons integrate inputs from neurons in the previous layer and fires when a threshold value is reached, while synapses are connections between neurons.

35 Synaptic functions DEVICE STUCTURE I-V Voltage(V) x Voltage(V) V 0.5us LTD 1x Pulse number Voltage (V) LTP RESET 10-9 SET Pd HfO2 W Voltage (V) 1 2 t>0 post-synaptic spike μ 15.0μ 20.0μ t (s) pre-synaptic LTD 50 t<0 post-synaptic spike 0 pre-synaptic spike t>0 post-synaptic spike 0 Conductance ( S) 10-5 pre-synaptic spike spike Pulse Number (#) V V Number (#) 300 IEEE EDL, 2017, 38:1208 Adv. Funct. Mater., 2018, 28: ; Nanoscale, 2017, 9: t ( s) t < t > t ( s) W (%) Voltage (V) t<0-10.0μ -5.0μ pre-synaptic spike post-synaptic spike x x x10-4 LTP x10-5 Current (A) Current (A) 4.0x us 150 Conductance ( S) 0 0.2V 0.2V W (%) V 200 Weight change (%) Conductance (us) 600 STDP(overlapping) Current(uA) Current(uA) 800 Current (A) Pd HfO2 WOX W LTP&LTD 500 Cu a-si Pt Pd HfO2 TiN 35

36 Artificial neuron circuit 36 Threshold switching Neuron design Operating principle and similarity to bio-neuron According to the integration and fire model, a simply neuron circuit is constructed with 1 TSM, 1 capacitor and 1 resistor. IEEE EDL, 2018, 39:308

37 Functions of artificial neuron 37 Capacitor charging/ discharging Output spike Spiking under different input intensities The TSM neuron successfully achieved four key behaviors of bio-neurons: the all-or-nothing spiking, threshold-driven spiking, a refractory period, and a strength-modulated frequency response. IEEE EDL, 2018, 39:308

38 Digit recognition simulation 38 Digit recognition simulation with TSM neurons demo. on an array with 1 input layer (30 synapses) and 1 output layer (10 neurons); Lateral inhibition is implemented with the winner-take-all rule. IEEE EDL, 2018, 39:308

39 Outline 39 Computing System s Challenge RRAM: Memory/Storage Convergence RRAM: Memory/Computing Convergence Summary

40 Summary 40 Computing technology improved times in past 60 years, face big challenge: Moore law slow-down ( trade off between performance and power density), Limitation of traditional memories (fast, high density, cheap, non-volatile) Von Neumann architecture( performance gap between memory and CPU) M/S convergence to reduce memory hierarchy and M/C convergence to realize brain-like high efficiency computing. RRAM as a new Memory technology, has already entered niche market for embedded application. Highly promising, significant efforts are still needed to address the interdisciplinary challenges of device optimization, circuit design, and system management.

41 Acknowledgement 41 Group Members: Prof. shibing Long, Qi Liu, Hangbing Lv Dr. Jinshun Bi, Feng Zhang, Jing Liu, Yuanlu Xie, Xiaoxin Xu, Qing Luo, Tuo Shi, etc. Graduated Students: Weihua Guan, Yingtao Li, Sen Zhang, Ming Wang, Qingyun Zuo, Meiyun Zhang, Sen Liu, Xiaolong Zhao, Tiancheng Gong, Xumeng Zhang, Rongrong Cao, Rui Wang, etc. Collaborator: Funding: National Natural Science Foundation of China (NSFC) National Basic Research Program of China (973 Program) Hi-Tech Research And Development Program Of China (863 Program) National Key Project (NKP)

42 Thanks for your attention!