Neuromorphic Computing based Processors

Transcription

1 Neuromorphic Computing based Processors Hao Jiang A collaborative research among San Francisco State University, EI-Lab at University of Pittsburgh, HP Labs, and AFRL Outline Why Neuromorphic Computing? Challenges and New Opportunity Spiking Neuromorphic Design A Framework of Heterogeneous Computing Systems Conclusion 2 1

2 Why Neuromorphic Computing? Computation & Control Tape Head Von Neumann arch. is facing severe challenges Von Neumann bottleneck Inefficient in cognitive computations Human brain: high efficiency 100 TFLOPS vs. 20 Watt Highly connected: 50B neurons & synapses Very light: 3 lbs Neuromorphic Design by Leveraging Memristor Technology 3 Brain The Most Efficient Computing Machine Brain: 15 30B neurons Extremely complex 4km/mm 3 35w Gray matter White matter Neocortex 6 layers Signals travel within and between layers Neuron: Process signals from other neurons. Synapse: Memory Weight signals Neural Network 4 2

3 Brain like Neuromorphic Circuits Slow progress in neuromorphic hardware implementation Lack of efficient synapse design Not supportive to mass connection Highly parallel Ultra power efficient Real world input Data friendly Human friendly output Flexible Extremely robust 5 Outline Why Neuromorphic Computing? Challenges and New Opportunity Spiking Neuromorphic Design A Framework of Heterogeneous Computing Systems Conclusion 6 3

4 Challenges in Traditional Approach Developing and implementing neural network models on large scale computer clusters or supercomputers. Performance (100M MIPS) Challenge Energy Challenge Megawatts U.S. households 7 Traditional Analog Approach Weight matrix W Y = f (W X) X Y Implementation Difficulties Scaling Weight floating gates, capacitor, etc. Volatile data, low precision, control signal O(N 2 ) for weight carrier Compute op-amps, analog voltage multipliers and differentiators Voltage offset, noise generation, voltage saturation O(N 2 ) for voltage multiplier Successful in small scale systems Intrinsic, hard to overcome Design complexity, power, and area grow very fast 8 4

5 Latest Progress IBM TrueNorth Numenta HTM Micron Automata 9 Memristor Rebirth of Analog Approach Memristor Memristor Crossbar M = R L α + R H (1- α) Natural weight carriers: Non volatility, high density Analog resistance states Two terminal programming I = V M1 /M1 + V M2 /M V Mn /M n Natural weight summation MIMO: avoid sneak path Cost ~ O(N), not O(N 2 ) 10 5

6 Memristor Rebirth of Neuromorphic Circuits Memristor Synapse Two terminal, high density Non volatility Analog/multi level states Crossbar Network Natural matrix function A MIMO system Good combination with memristor TaN1+x EI lab, APL 13 HP lab, N1 V I BL j N2 Resistance ( ) Voltage (V) N3 N4 Ni Ni+1 WL i m i,j Pulse number TiN-TaOx device, pulses grows linearly in amplitude EI lab & HP lab Nn V O N1 N2 N3 Nj-1 Nj Nn-1 Nn EI lab, DAC Outline Why Neuromorphic Computing? Challenges and New Opportunity Spiking Neuromorphic Design A Framework of Heterogeneous Computing Systems Conclusion 12 6

7 Spiking based Neuromorphic Computing Why spiking? Inspired by human brains Minimized transition electrical charge Reduced data communication distance High parallelism in processing Approaches in hardware system Analog and digital circuit blocks, capacitors Crossbar array basing on SRAM, PCM, Memristor cell In this work: Memristor based crossbar array as synapse 13 Spiking Neuromorphic System Matrix computation transformation Spiking based computation system 010 Mathematical matrix computation 101 V 1 g 11 g 12 g 1n Integrate and Fire V 2 g 21 g 22 g 2n Counters 100 V m M Σ i=1 g ij V i g m1 g m2 g mn I 1 I 2 I n Memristor based crossbar array for matrix computation Closer to biological system Power efficiency High reliability 14 7

8 Computation Methodology Working mechanism: t s T m i = 2 V m C m V th V out V m < V th C m integrates V m V th A spike is fired out, then C m is rest to 0 Spike occurs: Weighted current to integrator No spike: No current to & from integrator Traditional integrate and fire model Rate coding N Ideal:n j Σ i=1 g ij m i 15 Memristor crossbar array structure 1S1M memristor based cell Current (A) Alleviate the impact of sneak path leakage A thin film based selector after each memristor Minimal unit cell area of 4F Voltage (V) Memristor Selector Selector property and operation Spike occurs: Selector ON,andR s_on <<R M Nospike:Selector OFF,andR s_off >> R M g ij g g s ij g~ ij = g ij + g s 16 8

9 High speed Integrate and Fire Circuit (H IFC) V REF =33% of vin 17 Integrate and Fire Circuit V Cm Vout R mem V Cm C m V TH V OUT Structure and property V in Comparator Integrate capacitor, Reset transistor, Comparator with positive feedback I in High speed V th is much smaller than V dd Power and area ~100μW 28μm 12μm (180μm Technology) 18 9

10 System Verification Spiking Inputs... g 11 g 12 g 1n g 21 g 22 g 2n g n1 g n2 g nn C m Fire Circuit I 1 I 2... I n I&F I&F I&F 19 Output Pulse Number Pulse Duration Input Voltage Output Pulse Number Sensing Capacitance Comparator Trigging Voltage Memristor Conductance Selected Row 20 10

11 Theoretical Computation vs. Simulation Results Output Spike Number Simulation Result Ideal Linear Curve N 10 i=1 m i g -4 ij Parameters V th 0.5V C m 50fF V dd 1.8V Real: Nonlinearity Sums of weighted signal dependent Reasons: Reset time IFCdelay Optimization: LargerC m Higher speed of IFC Be used in neural network 21 Adaptability in Neuron Network WL1 WL1 WL2... WL31 WL2... WL31 WL32 WL32 V out (ns) (a) V out (ns) (c) WL1 WL2... WL31 WL32 V out (ns) (b) Output Spike Number (n j ) a 19 b 20 c 19 Good adaptability in neural network 22 11

12 Outline Why Neuromorphic Computing? Challenges and New Opportunity Spiking Neuromorphic Design A Framework of Heterogeneous Computing Systems Conclusion 23 Our Approach A framework of heterogeneous computing systems enhanced with neuromorphic computing accelerators (NCAs). Purpose: To combine the flexibility of conventional architecture in logic and scientific computation and the efficiency of neuromorphic architecture for ANN applications

13 Frontend: Prepare Data & Instructions Training bool RecallBSB(float *vec, float *wm) { /* simulate the synapse network*/ for(i=0;i<bsbsize;++i) wx[i] += wm[i*bsbsize+j] * vec[j]; /* activation fu nction*/ fo r(i=0;i<bsb Size; ++i) wx[i] = ALPHA*wx[i] + LAMDA*vec[i]; /* check convergence */ for(i=0;i<bsbsize;++i) if(fabsf(vec[i])!= 1.0) return false; return true; } Source to source translation bool RecallBSB(float *vec) { /*inputs to NCA*/ Send(NCA.id, vec); /*outpus from NCA*/ return Receive(NCA.id) } NCA aware compilation ; send each input from register to input ; buffer associated with specific NCA LW R1, $(vec) MOVD NCA.id, R1 ; launch the NCA SET NCA.id, #VAL LAUNCH ; put the output from output buffer of ; NCA to register, here is only one output DEQ R1, NCA.id RET Instruction Type Description set p reg Configuration Place the routing information stored at register reg to central router movd #(reg) I/O Load the data from memory to NCA launch Configuration Notify the central router to start transmitting deq reg I/O Dequeue the head data of Out queue and write it to register reg 25 Backend: System Design General Purpose Processor Bridge ADC NCA I/O Cfg Buffers Arbiter NCA I/O Cfg Buffers Arbiter SRAM I/O Bridge ADC NCA I/O Cfg Buffers Arbiter NCA I/O Cfg Buffers Arbiter Conventional Processing Neuromorphic Computing Accelerators Fetch Decode Issue Execute Memory RF NCA $ Write back NCA Tightly coupled design Invoked by special inst. Pipeline RF 26 13

14 NCA Architecture A hierarchical structure of MBC arrays Group Router Group Router Central Router SUM AMP Group Router Group Router Mixed signal NoC Analog computation Digital control and routing signal transition MBC arrays connected in a metamorphous centralized mesh (MCMesh) manner 27 System Level Evaluation Two implementations representing tradeoffs between computation performance and accuracy Multi-layer perception (MLP) Auto-associative memory (AAM) Benchmark Description 7 classification benchmarks Classification rate is used as reliability metric cancer connect-4 gene lymphography MNIST mushroom thyroid breast cancer diagnose connect-4 game nucleotide sequences detection lymph diagnose digit recognition poisonous mushroom discrimination thyroid diagnose 28 14

15 Experimental Setup The Design Parameters of NCA Components The Benchmark Implementation Details 29 Impact of Deficient Hardware Programming precision due to limited device resolution Device variations and signal fluctuations AAM is more robust than MLP 30 15

16 MBC Size Exploration Larger array size is preferable from performance perspective However, as array size increases the classification rate degrades induced by the aggravated variations 31 Comparison w/ Other Designs Baseline: CPU as general purpose processor D NPU: a popular digital neuromorphic accelerator (MICRO 12) Weight buffer Multiply-add Input buffer PE PE PE PE Accumulator Register Output buffer Sigmoid Unit PE PE PE PE PE PE PE PE PE PE PE PE MBCs+D Net: MBC arrays w/ digital NoC in order to evaluate the efficiency of mixed signal NoC NCA: our design w/ MBC arrays and mixed signal NoC 32 16

17 Comparison w/ Other Designs NCA Improvement MLP AAM Speedup Energy Saving D NPU is limited by the computational bandwidth. MBCs+D Net is limited by the costly AD/DA conversions. 33 Outline Why Neuromorphic Computing? Challenges and New Opportunity Spiking Neuromorphic Design A Framework of Heterogeneous Computing Systems Conclusion 36 17

18 Conclusion & Perspective Invention of new devices inspires the study of the next generation neuromorphic computing systems. A spiking neuromorphic computing system by leveraging the memristor crossbar array is demonstrated. We propose a heterogeneous system that combines the flexibility of conventional architecture and the efficiency of neuromorphic architecture. In the future research, we plan to extend the investigation to larger scale ANN applications. The techniques to enhance the run-time robustness in training and testing procedures will be studied. 37 Thank You and Questions? 38 18