Mixed-Signal-Electronics

Transcription

1 1 Mixed-Signal-Electronics PD Dr.-Ing. Stephan Henzler

2 2 Chapter 6 Nyquist Rate Analog-to-Digital Converters

3 3 Pipelined ADC 2

4 4 High-Speed ADC: Pipeline Processing

5 Stephan Henzler Advanced Integrated Circuit Design 2011/12 5 Robertson Diagram with Threshold Error

6 Stephan Henzler Advanced Integrated Circuit Design 2011/12 6 Impact of Comparator Offset on ADC Performance As soon as the residue leaves the convergence region the result suffers from major errors

7 Stephan Henzler Advanced Integrated Circuit Design 2011/12 7 Impact of Comparator Offset on ADC Performance Comparator offset reflects in non-linearity of ADC characteristic

8 Stephan Henzler Advanced Integrated Circuit Design 2011/12 8 Impairments in SAR Algorithms Finding: Each error in the amplifier gain or quantizer threshold causes divergence of the convergence algorithms and thus major conversion error How can we make SAR algorithms more robust Redundancy Redundant SAR algorithms Architecture implications Subranging ADC Pipeline ADC

9 Stephan Henzler Advanced Integrated Circuit Design 2011/12 9 How can we Strengthen the Algorithm? Gain and offset errors shift the algorithm out of the convergence window. Does an additional threshold help? No, not necessarily. Important is that the residue is not scaled back fully.

10 Redundant SAR Algorithms Stage quantizer with B bit (here B=2) Gain factor = 2 B Sensitive to thresh. var. Stephan Henzler Mixed-Signal-Electronics 2011/12 Stage quantizer with B bit (here B=2) Gain factor < 2 B redundant SAR not sensitive to thres. var. 10

11 Redundant Pipeline ADC Algorithm Redundant algorithm Two thresholds Gain ( = 2 ) does not scale residue back to full scale Stage resolution 1 bit Information contained in b i is 1.5 bit Redundancy Residue stays in convergence box even with strong gain and offset variations Stephan Henzler Mixed-Signal-Electronics 2011/12 11

12 12 Subranging Principle quantization error Principle: Coarse quantization in frontend ADC and fine quantization of residue in backend ADC Pipelining possible (s&h between frontend and backend Generalization to multi-stage ADC ( pipeline ADC)

13 13 Model of Frontend ADC

14 14 Linear Model of Subranging ADC

15 15 What is the Digital Result Combiner? Output of forward and backward ADC from last slide: Multiply result of backend ADC by 1/a and add to B out,1 Overall quantization error only depends on quantization error of backend ADC Quantization error of backend ADC is scaled by 1/a Resolution:

16 16 Linear Model of Subranging ADC Effective resolution of frontend ADC is ld(a) not necessarily the same as the number of bits of B out,1 Analog and digital gain must match, otherwise leakage of quantization error of frontend ADC

17 matching 17 Reconstruction of Signal Error free reconstruction requires matching between analog gain a and digital gain a d In the context of variations this requires calibration

18 18 General Pipeline SAR ADC

19 19 General Pipeline SAR ADC II As long as analog and digitals gains match all intermediate terms vanish Resolution R: Gain elements determine resolution, not the stage quantizers Effective stage resolution: Last stage must not saturate under all circumstances!

20 20 Background Calibration for Stage Gain Digital gain is continuously adjusted, i.e. even slow transient variations are corrected Li et al., Background Calibration Techniques for Multistage Pipelined ADCs With Digital Redundancy, TCAS II, 9/2003. Fu et al., A Digital Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters, JSSC, 12/1998 Liu et al., A 15b 40MS/s CMOS Pipelined ADC with Digital Background Calibration, JSSC, 5/2005 many more

21 Classification of Callibration Techniques Calibration comprises two phases Error estimation Error correction Analog approach additional analog components, noise, power, distortion, etc. Digital approach: Works on reults only, i.e. does not interfere with analog signal processing Calibration Foreground Background Virtual True Ginés et al., A Survey on Digital Background Calibration of ADCs, ECCTD, Stephan Henzler Mixed-Signal-Electronics 2011/12 21

22 22 Summary Pipeline ADC Stage errors can be tolerated if the residue stays inside the convergence region Minimum requirement is that the residue is back in the convergence region before the final quantizer) Take care for nonlinearity which is not revealed by the linear model Trade-off sampling frequency resolution latency Number of stages, i.e. number of elements grows linearly with resolution (not exponentially, ref flash ADC) Accurate sample-and-hold elements required (That s the reason why pipelined time-to-digital converters do not exist)

23 23 Nyquist Rate Analog-to-Digital Converters Flash Converter

24 Flash Converter Generate all switching thresholds in parallel and compare them to input voltage in parallel very fast, but high effort in terms of power, area, noise generation, clock distribution, input buffering high speed applications with moderate resolution implemented as parallel connection of 2 unit resistors Stephan Henzler Mixed-Signal-Electronics 2011/12 24

25 25 Properties of Flash ADC Advantages parallel processing very fast no analog post-processing Disadvantages: Huge hardware effort and power consumption (2 N ) high input capacitance synchronous routing of clock signal Good for high-speed converters with low # of bits

26 26 thermometer code one-hot code Flash Converter Thermometer-to-binary decoder often implemented in 2 steps thermo one-hot one-hot binary Allows for insertion of bubble correction in between decoders transition detector

27 27 Bubble Correction in Flash Converter

28 28 Bubble Correction in Flash Converter Bubbles in flash converters: Source of bubbles: noise meta-stability x-talk mismatch Basic bubble correction with 3-input NAND gate: transition only detected if more than one high signal occurs. More complex encoders require to eliminate long distance errors

29 29 Interpolating Flash Converter Preamp. with moderate gain to provide smooth transition region Latch for sign detection Resistive interpolation to create additional transition curves in between 2 regular ones

30 30

31 31 Interpolating Flash Converter Interpolation does not work at boarders Overrange amplifiers required

32 32 Interpolating Flash Converter (cont) additional series resistors to balance delays in high-speed interpolating flash converters

33 33 Kickback Effect Especially in flash converters Clocked comparators produce lots of noise at their inputs when toggling from track to latch mode. Different impedance seen from both comp inputs (input drive vs. resistor ladder) Differential error that may corrupt next conversion Decay of error sets max sample rate