EE247 Lecture 22. Techniques to reduce flash ADC complexity (continued) Multi-Step ADCs

Transcription

1 EE247 Lecture 22 Converters Techniques to reduce flash complexity (continued) MultiStep s TwoStep flash Pipelined s Effect of sub, subac, gain stage nonidealities on overall performance Error correction by adding redundancy igital calibration EECS 247 Lecture 22 Pipelined s 28 H.K. Page Two Stage Example 2bit 2bit AC 2bit Coarse ε q Fine ε q ε q2 out = ε q ε q ε q2 Use AC to compute missing voltage Add quantized representation of missing voltage Why does this help? How about ε q2? EECS 247 Lecture 22 Pipelined s 28 H.K. Page 2

2 Two Stage Example ε q /2 2 2 Second Fine First Coarse Fine is reused 2 2 times Fine 's full scale range needs to span only LSB of coarse quantizer ref 2 ref ε q2 = = EECS 247 Lecture 22 Pipelined s 28 H.K. Page 3 Residue or MultiStep Type Issues in Coarse (BBit) AC (BBit) Residue Fine (optional) (B2Bit) Bit Combiner (BB2)Bit Operation: Coarse determines MSBs AC converts the coarse output to analog Residue is found by subtracting ( AC ) Fine converts the residue and determines the LSBs Bits are combined in digital domain Issue:. Fine has to have precision in the order of overall /2LSB 2. Speed penalty Need at least clock cycle per extra series stage to resolve one sample EECS 247 Lecture 22 Pipelined s 28 H.K. Page 4

3 Solution to Issue () Reducing Precision Required for Fine 2bit Coarse 2bit AC ε q G=2 B 2bit Fine ε q ε q2 ε q ε q2 out = ε Advantages: q Accuracy needed for fine relaxed by introducing interstage gain Example: By adding gain of x(g=2 B =4) prior to fine in (22)bit case, precision required for fine is reduced from 4 to 2bit only! Fullscale input same for both coarse and fine can be identical stages Same reference voltage used for all stage w/o need for scaling down of ref EECS 247 Lecture 22 Pipelined s 28 H.K. Page 5 Solution to Issue (2) Increasing Throughput 2bit Coarse 2bit AC T/H(G=2 B ) ε q Fine T/H 2bit out = ε q ε q ε q2 Conversion time significantly decreased by employing T/H between stages All stages busy at all times operation concurrent uring one clock cycle coarse & fine s operate concurrently: First stage samples/converts/generates residue of input signal sample # n While 2 nd stage samples/converts residue associated with sample # n EECS 247 Lecture 22 Pipelined s 28 H.K. Page 6

4 Pipelined A/ Converters Ideal operation Errors and correction Redundancy igital calibration Implementation Practical circuits Stage scaling EECS 247 Lecture 22 Pipelined s 28 H.K. Page 7 Pipeline Block iagram Stage B Bits Stage 2 B 2 Bits res2 Stage k B k Bits MSB......LSB Align and Combine ata igital Output (B B 2..B k ) Bits Idea: Cascade several low resolution stages to obtain high overall resolution (e.g. bit can be built with series of s each bit only!) Each stage performs coarse A/ conversion and computes its quantization error, or "residue All stages operate concurrently EECS 247 Lecture 22 Pipelined s 28 H.K. Page 8

5 Pipeline Characteristics Number of components (stages) grows linearly with resolution Pipelining Trading latency for resolution Latency may be an issue in e.g. control systems Throughput limited by speed of one stage Fast ersatile: 8...6bits,...2MS/s One important feature of pipeline : many analog circuit nonidealities can be corrected digitally EECS 247 Lecture 22 Pipelined s 28 H.K. Page 9 Pipeline Concurrent Stage Operation φ φ 2 acquire convert Stage B Bits convert acquire Stage 2 B 2 Bits Stage k B k Bits CLK φ φ 2 Align and Combine ata igital output (B B 2... B k )Bits Stages operate on the input signal like a shift register New output data every clock cycle, but each stage introduces at least ½ clock cycle latency EECS 247 Lecture 22 Pipelined s 28 H.K. Page

6 Pipeline Latency Note: One conversion per clock cycle & 8 clock cycle latency [Analog evices, A 9226 ata Sheet] EECS 247 Lecture 22 Pipelined s 28 H.K. Page φ φ 2 Pipeline igital ata Alignment acquire convert Stage B Bits convert acquire Stage 2 B 2 Bits Stage k B k Bits CLK φ φ 2 out CLK CLK CLK igital shift register aligns subconversion results in time EECS 247 Lecture 22 Pipelined s 28 H.K. Page 2

7 Cascading More Stages ref /2 B /2 (BB2) /2 (BB2B3) B bits B 2 bits B 3 bits AC LSB of last stage becomes very small Impractical to generate several All stages need to have full precision EECS 247 Lecture 22 Pipelined s 28 H.K. Page 3 Pipeline InterStage Gain Elements B bits 2 B B 2 bits 2 B2 2 B3 B 3 bits AC Practical pipelines by adding interstage gain use single Precision requirements decrease down the pipe Advantageous for noise, matching (later), power dissipation EECS 247 Lecture 22 Pipelined s 28 H.K. Page 4

8 Complete Pipeline Stage ε q G res Bbit Bbit AC Residue Plot E.g.: B=2 G=2 2 =4 res EECS 247 Lecture 22 Pipelined s 28 H.K. Page 5 Pipeline Single Stage Model ε q G res ε q out res = Gxε q EECS 247 Lecture 22 Pipelined s 28 H.K. Page 6

9 Pipeline Errors Nonidealities associated with subs, subacs and gain stages error in overall pipeline performance Need to find means to tolerate/correct errors Important sources of error Sub errors comparator offset Gain stage offset Gain stage gain error SubAC error EECS 247 Lecture 22 Pipelined s 28 H.K. Page 7 Pipeline MultiStage Model, ε q res2 res(n) G G 2 G n ε q2 ε q(n) 2 (n) n ε qn out /G d /G d2 /G d(n) G ε G q2 2 out = in, εq G d G d G d2 ε G... G G ε q(n ) (n ) qn n 2 n dj d(n ) j= j= G dj EECS 247 Lecture 22 Pipelined s 28 H.K. Page 8

10 Pipeline Model If the "Analog" and "igital" gain/loss is precisely matched: εqn out = in, n G j j= rms FS Signal. R. = 2log = 2log rms Quant. Noise B B log2 2 n Bn n G j j= n B log G = 2 j= j n n B log G j= j ref 2 ref n Bn G j= j = 2log Bn n G j j= EECS 247 Lecture 22 Pipelined s 28 H.K. Page 9 Pipeline Observations The aggregate resolution is independent of sub resolution! Effective stage resolution B j =log 2 (G j ) Overall conversion error does not (directly) depend on sub errors! Only error term in out contains quantization error associated with the last stage So why do we care about sub errors? Go back to two stage example EECS 247 Lecture 22 Pipelined s 28 H.K. Page 2

11 Pipeline Sub Errors, B =2bits 2bits qn out = in, n G j j= out = in, ε ε G q2 ref ε q2 Grows outside ½ LSB bounds EECS 247 Lecture 22 Pipelined s 28 H.K. Page 2 Pipeline st Stage Comparator Offset Problem: exceeds 2 nd pipeline stage overload range res2 Overall Transfer Curve First stage Levels: (Levels normalized to LSB) Ideal comparator threshold:,, Comparator threshold including offset:,.3, Missing Code! EECS 247 Lecture 22 Pipelined s 28 H.K. Page 22

12 Pipeline Three Ways to eal with Errors All involve "sub redundancy Redundancy in stage that produces errors Choose gain for residue to be processed by the 2 nd stage < 2 B Higher resolution sub & subac Redundancy in succeeding stage(s) EECS 247 Lecture 22 Pipelined s 28 H.K. Page 23 () InterStage Gain Following st Stage <2 B B bits Choose G less than 2 B Effective stage resolution could become noninteger B eff =log 2 G E.g. if G =3.8 B eff =.8bit ε q2 Ref: A. Karanicolas et. al., JSSC 2/993 EECS 247 Lecture 22 Pipelined s 28 H.K. Page 24

13 Correction Through Redundancy enlarged residuum still within input range of next stage res2 Overall Transfer Curve If G=2 instead of 4 Only bit resolution from first stage (3bit total) In spite of comparator offset: No overall error! EECS 247 Lecture 22 Pipelined s 28 H.K. Page 25 (2) Higher Resolution Sub B bits Keep G precise power of two (e.g. G =4) Add extra decision levels in sub (e.g. add extra bit to st stage) E.g. B =B eff ε q2 Ref: Singer et. al., SLI 996 EECS 247 Lecture 22 Pipelined s 28 H.K. Page 26

14 (3) OverRange Accommodation Through Increase in Following Stage Resolution, B bits No redundancy in stage with errors Add extra decision levels in succeeding stage ε q2 Ref: Opris et. al., JSSC 2/998 EECS 247 Lecture 22 Pipelined s 28 H.K. Page 27 Redundancy The preceding analysis applies to any stage in an nstage pipeline Can always perceive a multistage pipelined as a single stage backend B bits B 2 bits B 3 bits B 4 bits B bits B 2 B 3 B 4 bits EECS 247 Lecture 22 Pipelined s 28 H.K. Page 28

15 Redundancy In literature, sub redundancy schemes are often called "digital correction" a misnomer! No error correction takes place We can tolerate sub errors as long as: The residues stay "within the box", or Another stage downstream "returns the residue to within the box" before it reaches last quantizer Let's calculate tolerable errors for popular ".5 bits/stage" topology EECS 247 Lecture 22 Pipelined s 28 H.K. Page 29.5 Bits/Stage Example Comparators placed strategically to minimize overhead G=2 B eff =log 2 G=log 2 2= B=log 2 (2)= os = /8.5bit redundancy Ref: Lewis et. al., JSSC 3/992 EECS 247 Lecture 22 Pipelined s 28 H.K. Page 3

16 3Stage.5bitperStage Pipelined res2 res3 Overall Transfer Curve All three stages Comparator with offset Overall transfer curve No missing codes Some NL error Ref: S. Lewis et al, A b 2MS/s Analogtoigital Converter, J. SolidState Circ., pp. 358, March 992 EECS 247 Lecture 22 Pipelined s 28 H.K. Page 3 Summary So Far Pipelined A/ Converters B bits 2 Beff B 2B2 2 2 bits 2 B2eff B 3 bits 2 B3eff AC Cascade of low resolution stages Stages operate concurrently trades latency for resolution Throughput limited by speed of one stage Fast Errors and correction Builtin redundancy compensate for sub inaccuracies (interstage gain: G=2 Bneff, B neff < B n ) EECS 247 Lecture 22 Pipelined s 28 H.K. Page 32

17 Pipeline Errors Nonidealities associated with subs, subacs and gain stages error in overall pipeline performance Need to find means to tolerate/correct errors Important sources of error Sub errors comparator offset Gain stage offset Gain stage error SubAC error EECS 247 Lecture 22 Pipelined s 28 H.K. Page 33 InterStage Amplifier Offset os AC os G res os Input referred converter offset usually no problem Equivalent sub offset accommodated through adequate redundancy EECS 247 Lecture 22 Pipelined s 28 H.K. Page 34

18 Pipeline Errors Nonidealities associated with subs, subacs and gain stages error in overall pipeline performance Need to find means to tolerate/correct errors Important sources of error Sub errors comparator offset Gain stage offset Gain stage gain error SubAC error EECS 247 Lecture 22 Pipelined s 28 H.K. Page 35 Gain Stage Gain Error, ε q res res2 res(n) G δ G 2 G n ε q2 ε q(n) 2 (n) n ε qn out /(G d δ ) /G d2 /G d(n) G = ε G out in, q d δ δ ε G ε G G G G q2 2 q( n ) ( n ) qn... n 2 n d d2 d( n ) G dj Gdj j= j= Small amount of gain error can be tolerated ε EECS 247 Lecture 22 Pipelined s 28 H.K. Page 36

19 Interstage Gain Error First Stage Residue (Gain Error) Converter Transfer Function (Gain Error) res out.5.5 in.5.5 in out(ideal) out Transfer Function Error(Gain Error) in EECS 247 Lecture 22 Pipelined s 28 H.K. Page 37 Gain Stage Gain Inaccuracy Gain error can be compensated in digital domain "igital Calibration" Problem: Need to measure/calibrate digital correction coefficient Example: Calibrate bit first stage Objective: Measure G in digital domain EECS 247 Lecture 22 Pipelined s 28 H.K. Page 38

20 Model bit = = bit AC G G in 2 res = G Backend ( ) in back AC G in AC AC ( = ) = ( = ) = ref / 2 EECS 247 Lecture 22 Pipelined s 28 H.K. Page 39 Gain Stage Inacurracy Calibration Step = const. G () Backend back () bit M U X bit AC () res () back = G = G ( in ref / 2) ( / 2) in ref ref store EECS 247 Lecture 22 Pipelined s 28 H.K. Page 4

21 Gain Stage Inacurracy Calibration Step 2 = const. G (2) Backend back (2) bit M U X bit AC (2) res (2) back = G = G ( in ) ( ) in ref store EECS 247 Lecture 22 Pipelined s 28 H.K. Page 4 Gain Stage Inacurracy Calibration Evaluate () back (2) back () back = G = G (2) back ( / 2) in ( ) in ref ref ref = G 2 To minimize the effect of backend noise perform measurement several times and take the average EECS 247 Lecture 22 Pipelined s 28 H.K. Page 42

22 Accuracy Bootstrapping, ε q res2 res(n) G G 2 G n ε q2 ε q(n) 2 (n) n ε qn out /G d /G d2 /G d(n) G ε G G = q2 2 q( n ) ( n ) qn out in, ε q... n 2 n Gd Gd Gd 2 Gd ( n ) G dj Gdj j= j= Highest sensitivity to gain errors in frontend stages ε ε EECS 247 Lecture 22 Pipelined s 28 H.K. Page 43 "Accuracy Bootstrapping" irection of Calibration Sufficiently Accurate Stage Stage 2 Stage 3 Stage k B n bits Ref: A. N. Karanicolas et al. "A 5b Msample/s digitally selfcalibrated pipeline," IEEE J. Of SolidState Circuits, pp. 275, ec. 993 E. G. Soenen et al., "An architecture and an algorithm for fully digital correction of monolithic pipelined s," TCAS II, pp. 4353, March 995 L. Singer et al., "A 2 b 65 MSample/s CMOS with 82 db SFR at 2 MHz," ISSCC 2, igest of Tech. Papers., pp. 389 (calibration in opposite direction!) EECS 247 Lecture 22 Pipelined s 28 H.K. Page 44

23 Pipeline Errors Nonidealities associated with subs, subacs and gain stages error in overall pipeline performance Need to find means to tolerate/correct errors Important sources of error Sub errors comparator offset Gain stage offset Gain stage error SubAC error EECS 247 Lecture 22 Pipelined s 28 H.K. Page 45 AC Errors G Backend B bit B bit AC ε AC out /G back Can be corrected digitally as well Same calibration concept as gain errors ary AC codes & measure errors via backend EECS 247 Lecture 22 Pipelined s 28 H.K. Page 46

24 AC Calibration Step = const. G Backend B bit M U X B bit AC ε AC () out /G back ε AC () equivalent to amp. offset ignore EECS 247 Lecture 22 Pipelined s 28 H.K. Page 47 AC Calibration Step B = const. G Backend B bit M U X B bit AC ε AC (...2 B )...2 B Cal. Register out /G back Stepping through AC codes...2 (B) yields all incremental correction values Measurements repeated and averages to account for variance associated with noise EECS 247 Lecture 22 Pipelined s 28 H.K. Page 48

25 Pipeline Example: Calibration Hardware Above block diagram may seem extensive however, in current fineline CMOS technologies digital portion of a pipeline s consume insignificant power and area compared to the analog sections Ref: E. G. Soenen et al., "An architecture and an algorithm for fully digital correction of monolithic pipelined s," TCAS II, pp. 4353, March 995 EECS 247 Lecture 22 Pipelined s 28 H.K. Page 49 Pipelined Error Correction/Calibration Summary OS a 3 3 IN G RES AC ε gain ε ε AC Error ε, os ε gain ε AC Interstage amplifier nonlinearity Redundancy either same stage or next stage igital adjustment Correction/Calibration Either sufficient component matching or digital calibration? EECS 247 Lecture 22 Pipelined s 28 H.K. Page 5

26 Interstage Gain Nonlinearity Invert gain stage nonlinear polynomial Express error as function of RES Push error into digital domain through backend Ref: B. Murmann and B. E. Boser, "A 2b, 75MS/s Pipelined using OpenLoop Residue Amplification," ISSCC ig. Techn. Papers, pp , 23 EECS 247 Lecture 22 Pipelined s 28 H.K. Page 5 a 3 X 3 Interstage Gain Nonlinearity X 2 3 ε gain RES Backend p 2 B a = (2 ε gain ) (...) B,corr ε( B, p 2 ) ε(b,p2) = p2b 3p2 B 2p2 B... Precomputed table lookup p 2 continuously estimated & updated (account for temp. & other variations) Ref: B. Murmann and B. E. Boser, "A 2b, 75MS/s Pipelined using OpenLoop Residue Amplification," ISSCC ig. Techn. Papers, pp , EECS 247 Lecture 22 Pipelined s 28 H.K. Page 52

27 Interstage Gain Nonlinearity Compensation Proof of Concept Evaluation Prototype Reused 4bit in.35μm from Analog evices [Kelly, ISSCC 2] Modified only st stage with 3b eff openloop amplifier built with simple diffpair resistive load instead of the conventional feedback around highgain amp Conventional 9b eff backend, 2bit redundancy in st stage Realtime postprocessor offchip (FPGA) Ref: B. Murmann and B. E. Boser, "A 2b, 75MS/s Pipelined using OpenLoop Residue Amplification," ISSCC ig. Techn. Papers, pp , 23 EECS 247 Lecture 22 Pipelined s 28 H.K. Page 53 Measurement Results 2bit w Extra 2bits for Calibration (a) without calibration INL [LSB] RNG= RNG= Code (b) with calibration.5 (b) with calibration INL [LSB] Code C d EECS 247 Lecture 22 Pipelined s 28 H.K. Page 54