ELEN 610 Data Converters

Transcription

1 Spring 2014 S. Hoyos-ECEN ELEN 610 Data Converters Sebastian Hoyos Texas A&M University Analog and Mixed Signal Group

2 Folding Spring 2014 S. Hoyos-ECEN-610 2

3 Spring 2014 S. Hoyos-ECEN Inefficiency of Flash ADC V FS V i Strobe 2 N -1 f s Encoder D o D o 2 N -1 comparators 0 V FS V i Only comparators in the vicinity of V in are active at a time low efficiency.

4 Spring 2014 S. Hoyos-ECEN Segmented Quantization 2 N -1 V FS D o Segment indicator (M bits) V i Analog pre-processing divides V in into 2 M uniformly-spaced segments. Fine quantization (N-M) bits

5 Spring 2014 S. Hoyos-ECEN Signal Folding 2 N -1 V FS D o Analog pre-processing folding amplifier Folding factor (F) is equal to the number of folded segments V i Fine quantization N-log 2 (F) bits Segment indicator (log 2 (F) bits)

6 Spring 2014 S. Hoyos-ECEN Folding ADC Architecture V R V i Reference Ladder Fine ADC Coarse ADC MSB s F = 8 5 bits LSB s 3 bits Digital Logic 8 bits D out The fine ADC performs amplitude quantization on the folded signal. The coarse ADC differentiates which segment V in resides in.

7 Spring 2014 S. Hoyos-ECEN Folding Amplifier R L R L V o + V o - F = 3 M 1 M 2 M 3 M 4 M 5 M 6 I S V R 1 I S V R 2 I S V R 3 V i V o I S R L 0 V i -I S R L V R /6 V R /2 5V R /6

8 Spring 2014 S. Hoyos-ECEN Signal Folding Pros Folding reduces the comparator number by the folding factor F, and also reduces the number of preamplifiers by F but adds F folder amplifiers. Cons Multiple differential pairs in the folder increases the output loading. Frequency multiplication at the folder output.

9 Spring 2014 S. Hoyos-ECEN Frequency Multiplication f max fin sin 1 (2 ) F

10 Spring 2014 S. Hoyos-ECEN Folding Amplifier R L R L V o + V o - F = 3 M 1 M 2 M 3 M 4 M 5 M 6 V i I S V R 1 I S V R 2 I S V R 3 Zero-crossings are still precise! V o I S R L 0 V i -I S R L V R /6 V R /2 5V R /6

11 Spring 2014 S. Hoyos-ECEN Zero-Crossing Detection V o 0 V i F = 3, P = 4 Only detect zero-crossings instead of fine amplitude quantization insensitive to folder nonlinearities. P parallel folding amplifiers are required.

12 Spring 2014 S. Hoyos-ECEN Offset Parallel Folding V R V i F = 3, P = 4 Folder 1 V 1 c 0 V i Reference Ladder Folder 2 V 2 Folder 3 V 3 c c 0 0 V i V i Folder 4 V 4 c 0 V i Total # of zero-crossings = Total # of preamps = P*F Parallel folding saves the # of comparators, but not the # of preamps still large C in.

13 Spring 2014 S. Hoyos-ECEN Folding + Interpolation V i Cross-connect P & N sides at the endpoints c V i

14 Spring 2014 S. Hoyos-ECEN Rounding Problem V o 0 V i F = 3 2 2(V gs -V th ) V o 0 V i F = 9 2 2(V gs -V th ) Large F results in signal rounding, causing gain and swing loss. Max. folding factor is limited by V ov of folder and supply voltage.

15 Spring 2014 S. Hoyos-ECEN Folding vs. Interpolation/Averaging Folding Folding works better with non-overlapped active regions between adjacent folders. Large V ov (for high speed) of folders and low supply voltage limit the max. achievable F. Interpolation/Averaging Work better with closely spaced overlapped active region between adjacent folding signals. Observation Small F and large P (parallel folders) will help both folding and interpolation/averaging, but introduces large C in. What else can we do?

16 Spring 2014 S. Hoyos-ECEN Cascaded Folding V o 0 V i F = 3 c V o 0 V i F = 9 Ideal: A large folding factor F can be developed successively. Small F in the 1 st -stage folder large V ov, less capacitive loading, and less frequency multiplication effect.

17 Spring 2014 S. Hoyos-ECEN Cascaded Folder Architecture (I) F =? Gilbert four-quadrant multiplier based folding amplifier Only works with even P, requires a lot of headroom

18 Spring 2014 S. Hoyos-ECEN Cascaded Folder Architecture (II) F =? V o + V o - V i Simple differential pair-based folding amplifiers Only works with odd P, compatible with low supply voltage.

19 Spring 2014 S. Hoyos-ECEN Mechanical Model of Cascaded Folding Bult (JSSC 97)

20 Spring 2014 S. Hoyos-ECEN Distributed Preamplification Comparators Interpolation and Averaging Interpolation and 2 nd -stage Folding 1 st -stage Folding and Averaging c c c Gain Input and Reference Ladder c Large signal gain developed gradually along the signal path from soft to hard decision

21 Spring 2014 S. Hoyos-ECEN Cascaded Offset Bit Alignment V R V i Reference Ladder 1 st -stage Folders (P*F1) 2 nd -stage Folders (F2) Fine Comparators LSB s Digital Logic D out F1 Cmp s P Cmp s Bit Alignment MSB s Two-step offset bit alignment large offset tolerance on F 1 coarse comparators and medium tolerance on P comparators.

22 Spring 2014 S. Hoyos-ECEN Useful Formulas Assuming a two-stage cascaded folding & interpolating ADC, F 1 = 1 st -stage folding factor, F 2 = 2 nd -stage folding factor, P = # of offset parallel folders (P>F 2 ), I = total interpolation factor, then total # of decision level = P*F 1 *I, ADC Resolution = Log 2 (P*F 1 *I), total # of preamps in 1 st folder = P*F 1, total # of preamps in 2 nd folder = P, total # of fine comparators = P*I/F 2, total # of coarse comparators = F 1 *F 2, F 1 +F 2, or F 1 +P?

23 Spring 2014 S. Hoyos-ECEN Cascaded Offset Bit Alignment V i A B C D V FS 0 D C B A Margin A OF UF F 1 coarse comparators at input and P coarse comparators at 1 st -stage folder outputs resolve F 1 *P (>F 1 *F 2 ) folds. One fine comparator output is utilized to perform offset bit alignment.

24 Spring 2014 S. Hoyos-ECEN References 1. R. J. van De Plassche et al., JSSC, vol. 14, pp. 938, issue 6, R. E. J. van De Grift et al., JSSC, vol. 19, pp , issue 3, R. E. J. van De Grift et al., JSSC, vol. 22, pp , issue 6, R. J. van de Plassche et al., JSSC, vol. 23, pp , issue 6, J. van Valburg et al., JSSC, vol. 27, pp , issue 12, B. Nauta et al., JSSC, vol. 30, pp , issue 12, A. G. W. Venes et al., JSSC, vol. 31, pp , issue 12, M. P. Flynn et al., JSSC, vol. 31, pp , issue 9, P. Vorenkamp et al., JSSC, vol. 32, pp , issue 12, K. Bult et al., JSSC, vol. 32, pp , issue 12, M. P. Flynn et al., JSSC, vol. 33, pp , issue 12, M.-J. Choe et al., VLSI, 1999, pp R. C. Taft et al., JSSC, vol. 39, pp. 2107, issue 12, 2004.

25 Nyquist-Rate ADC s Word-at-a-time (1 step) Flash Folding Interleaving Level-at-a-time (2 N steps) Integrating (Serial) Bit-at-a-time (N steps) Successive approximation Algorithmic (Cyclic) Partial word-at-a-time (1<M N steps) Subranging Pipeline the number in the parentheses is the latency of conversion, not throughput. Spring 2014 S. Hoyos-ECEN

26 Spring 2014 S. Hoyos-ECEN Resolution-Conversion Speed Tradeoff Resolution [Bits] 20 Integrating 1 level/t clk 1 word/osr*tclk 1 bit/t clk 15 Oversampling Partial word/t clk 10 5 Nyquist Oversampling Successive Approximation Algorithmic Subranging Pipeline 1 word/t clk Flash Folding & Interpolating Interleaving 0 1k 10k 100k 1M 10M 100M 1G 10G Sample Rate [Hz]

27 Integrating ADC Spring 2014 S. Hoyos-ECEN

28 Spring 2014 S. Hoyos-ECEN Single-Slope Integrating ADC V i V Y V X f clk Control Counter D o I C Counter keeps counting until comparator output toggles. Simple, inherently monotonic, but very slow (2 N *T clk /sample).

29 Spring 2014 S. Hoyos-ECEN Single-Slope Integrating ADC V X slope=i/c V Y t V i I C D o t 1 1, Do Tclk C I T clk t V. i t 1 start stop t INL depends on the linearity of the ramp signal. Precision capacitor (C) and current source (I) are required. Comparator must handle large common-mode input.

30 Spring 2014 S. Hoyos-ECEN Dual-Slope Integrating ADC C V i -V R R V X Control Counter D o f clk CT RC integrator replaces the current integrator. Input and reference voltages experience the same signal path. Comparator only detects zero-crossing (constant input CM).

31 Spring 2014 S. Hoyos-ECEN Dual-Slope Integrating ADC V X V os V m t 1 t t V m Vin RC D o t 1 N N 2 1 VR t2 RC t2 V t V 1 in R. Exact values of R, C, and T clk are not required. Comparator offset doesn t matter. Op-amp offset introduces gain error and offset. Op-amp nonlinearity introduces INL error.

32 Spring 2014 S. Hoyos-ECEN Subranging Dual-Slope ADC SHA V t V i C 1 C S V X C 2 f clk Control Logic Cnt 1 (8 bits) Carry Cnt 2 (8 bits) MSB s LSB s I I 256 Much faster conversion speed. Two matched current sources and two comparators are required.

33 Spring 2014 S. Hoyos-ECEN Subranging Dual-Slope ADC V X V t 1 2 t 1 t 2 t dvx dt dvx dt D o 1 2 N I, C I. 256C W 1 N 2 Precise V t is not required if carry is propagated. Matching between the current sources is critical if I 1 = I, I 2 = (1+δ) I/256, then δ 0.5/256.

34 Spring 2014 S. Hoyos-ECEN Subranging Multi-Slope ADC SHA V i C S V X Cnt 1 4 Bits f clk Control Logic Cnt 2 4 Bits I I 16 I 256 Cnt 3 4 Bits Ref: J.-G. Chern and A. A. Abidi, "An 11 bit, 50 ksample/s CMOS A/D converter cell using a multislope integration technique," in Proceedings of IEEE Custom Integrated Circuits Conference, 1989, pp. 6.2/1-6.2/4.

35 Spring 2014 S. Hoyos-ECEN Subranging Multi-Slope ADC V X t dvx dt dvx dt dvx dt I, C I, 16C I. 256C t 1 t 3 t 2 D o N1 W1 N2 W2 N3 Single comparator detects zero-crossing. Comparator response time is greatly relaxed. Matching between the current sources is still critical.

36 Spring 2014 S. Hoyos-ECEN Successive Approximation ADC

37 Spring 2014 S. Hoyos-ECEN Successive Approximation ADC V i V X V DAC b 1 DAC D o b N Shift Register Binary search algorithm N*T clk to complete N bits. Conversion speed is limited by comparator, DAC, and SAR (successive approximation register)

38 Spring 2014 S. Hoyos-ECEN Binary Search V DAC V i V FS V FS MSB T clk LSB t DAC output gradually approaches the input voltage. Comparator differential input gradually approaches zero.

39 Spring 2014 S. Hoyos-ECEN Charge Redistribution SA ADC Φ 1e V X 8C 4C 2C C C SAR D o V R V i Φ 1 Φ 1 Φ 1 Φ 1 Φ 1 4-bit binary-weighted capacitor array DAC. Capacitor array samples input when Φ 1 is asserted (bottom-plate).

40 Spring 2014 S. Hoyos-ECEN Charge Redistribution (MSB) SAR D o Φ 1e V X 2C C C 8C 4C V R V i Φ 1 Φ 1 Φ 1 Φ 1 Φ 1 i R j j j j i R X j j X X R j j i V V C C V C V V C V C V V C V

41 Spring 2014 S. Hoyos-ECEN Comparison (MSB) V X 1 0 t Sample 1 MSB MSB TEST : V X V 2 R V i If V X < 0, then V i > V R /2, and MSB = 1, C 4 remains connected to V R. If V X > 0, then V i < V R /2, and MSB = 0, C 4 is switched to ground.

42 Spring 2014 S. Hoyos-ECEN Charge Redistribution (MSB-1) Φ 1e V X 8C 4C 2C C C SAR D o V R V i Φ 1 Φ 1 Φ 1 Φ 1 Φ 1 V i 16C V R VX 12C VX 4C VX V R 12C Vi 16C 16C VR Vi 3 4

43 Spring 2014 S. Hoyos-ECEN Comparison (MSB-1) V X t Sample 1 0 MSB MSB TEST : V X 3 V 4 R V i If V X < 0, then V i > 3V R /4, and MSB-1 = 1, C 3 remains connected to V R. If V X > 0, then V i < 3V R /4, and MSB-1 = 0, C 3 is switched to ground.

44 Spring 2014 S. Hoyos-ECEN Charge Redistribution (Other Bits) Φ 1e V X 8C 4C 2C C C SAR D o V R V i Φ 1 Φ 1 Φ 1 Φ 1 Φ 1 Test completes when all four bits are determined w/ four charge redistributions and comparisons.

45 Spring 2014 S. Hoyos-ECEN After Four Clock Cycles V X t Sample MSB LSB Usually, half T clk is allocated for charge redistribution and half for comparison + digital logic. V X always converges to 0 (V os if comparator has nonzero offset).

46 Spring 2014 S. Hoyos-ECEN Bottom-Plate Parasitics Φ 1e C P 8C 4C 2C C C V os SAR D o V R V i Φ 1 Φ 1 Φ 1 Φ 1 Φ 1 If V os = 0, C P has no effect; otherwise, C P attenuates V X. AZ can be applied to the comparator to reduce offset.

47 Spring 2014 S. Hoyos-ECEN Summary on SA ADC Power efficiency only comparator consumes DC power. DAC nonlinearity limits the INL and DNL of the SA ADC N-bit precision requires N-bit matching from the cap array. Calibration can be performed to remove mismatch errors (Lee, JSSC 84). If C P =0, comparator offset V os introduces an input-referred offset V os ; for nonzero C P, input-referred offset is larger than V os (δ~c P /ΣC j ). If V os =0, CP has no effect (V X 0 at the end of search); otherwise, charge sharing occurs at summing node (V X is attenuated). Binary search is sensitive to intermediate errors made during search DAC must settle into ½ LSB within the time allowed. Comparator offset must be constant (no hysteresis). Nonbinary search can be used (Kuttner, ISSCC, 2002).

48 Spring 2014 S. Hoyos-ECEN References 1. R. E. Suarez, P. R. Gray, and D. A. Hodges, JSSC, pp , issue 6, J. L. McCreary and P. R. Gray, JSSC, pp , issue 6, H.-S. Lee, D. A. Hodges, and P. R. Gray, JSSC, pp , issue 6, M. de Wit, K.-S. Tan, and R. K. Hester, JSSC, pp , issue 4, C. M. Hammerschmied and H. Qiuting, JSSC, pp , issue 8, S. Mortezapour and E. K. F. Lee, JSSC, pp , issue 4, G. Promitzer, JSSC, pp , issue 7, F. Kuttner, ISSCC, 2002, pp

49 Algorithmic ADC Spring 2014 S. Hoyos-ECEN

50 Spring 2014 S. Hoyos-ECEN Algorithmic (Cyclic) ADC V i SHA V X 2X V o Sample mode 1-b V FS /2 V FS /2 DAC 0 b j Input is sampled first, then circulates in the loop for N clock cycles. Conversion takes N cycles with one bit resolved in each T clk.

51 Spring 2014 S. Hoyos-ECEN Modified Binary Search Algorithm V i SHA V X 2X V o Conversion mode 1-b V FS /2 V FS /2 DAC 0 b j If V X < V FS /2, then b j = 0, and V o = 2*V X. If V X > V FS /2, then b j = 1, and V o = 2*(V X -V FS /2).

52 Spring 2014 S. Hoyos-ECEN Modified Binary Search Algorithm V X 1 X2 2 X2 3 X2 4 X2 5 X2 6 V FS V i V FS MSB LSB T clk Constant threshold (V FS /2) is used for each comparison. 2X gain is provisioned each time residue circulates around the loop.

53 Spring 2014 S. Hoyos-ECEN Loop Transfer Function V o V i SHA V X 2X V o c V FS b j =0 b j =1 1-b V FS /2 V FS /2 DAC 0 b j 0 V FS /2 V FS V i If V X < V FS /2, then b j = 0, and V o = 2*V X. If V X > V FS /2, then b j = 1, and V o = 2*(V X -V FS /2).

54 Spring 2014 S. Hoyos-ECEN Offset Errors Ideal RA offset CMP offset V o V o V o V FS b=0 b=1 V FS b=0 b=1 V os V FS b=0 b=1 V os 0 V FS /2 V FS V i 0 V FS /2 V FS V i 0 V FS /2 V FS V i D o D o D o 0 V FS /2 V FS V i V FS /2 V i 0 V FS 0 V FS /2 V FS V i V o = 2*(V i - b j *V FS /2) V i = b j *V FS /2 + V o /2

55 Spring 2014 S. Hoyos-ECEN The Multiplier DAC (MDAC) Φ 2 V i Φ 1 C 1 -V R /4 Φ 1 C 2 A V o V R /4 Φ 1e -V R 0 V R Decoder Φ 2 2X gain + 3-level DAC + subtraction all integrated. A 3-level DAC is perfectly linear w/ fully-differential signals.

56 Spring 2014 S. Hoyos-ECEN The 1.5-Bit Architecture V R V R /2 -V R /2 -V R b=0 b=1 b=2 V o V R /4 V R /4 V R V i 3 decision levels ENOB = log 2 3 = Max tolerance on comparator offset is ±V R /4. An implementation of the Sweeny-Robertson-Tocher (SRT) division principle. The conversion accuracy solely relies on the loopgain error, i.e., the gain error and nonlinearity. A 3-level DAC is required. Architecture can be generalized to n.5-b per conversion.

57 Spring 2014 S. Hoyos-ECEN Error Mechanisms of RA Φ 1 C 1 Φ 2 V o C1 C C 1 2 V i C C 2 b 1 VR 1 V i -V R /4 V R /4 Φ 1 C 2 Φ 1e A V o Capacitor mismatch Op-amp finite-gain error and nonlinearity -V R 0 V R Decoder Φ 2 Charge injection and clock feedthrough Finite circuit bandwidth V o t C C V b 1 2 C 1 i 1 C C1 C2 A V o 2 V R ΔV V i

58 Spring 2014 S. Hoyos-ECEN RA Gain Error and Nonlinearity V R V R /2 b=0 b=1 b=2 V o D o 0 V i -V R /2 -V R -V R /4 V R /4 V R 0 -V R V i V R Raw accuracy is usually limited to bits w/o error correction.

59 Spring 2014 S. Hoyos-ECEN N 1 N N 2 b 2 b 2 b b 2 1 Do 1 N 1 N N 3 b 3 b 3 b b 3 2 Do 1 bit and 1.5-b with Offset Tolerance 1.5-b without Offset Tolerance

60 Effect of Offset Spring 2014 S. Hoyos-ECEN

61 Effect of Offset Spring 2014 S. Hoyos-ECEN

62 Spring 2014 S. Hoyos-ECEN References 1. P. W. Li, et al., JSSC, vol. 19, pp , issue 6, C. Shih, et al., JSSC, vol. 21, pp , issue 4, H. Ohara, et al., JSSC, vol. 22, pp , issue 6, H. Onodera, et al., JSSC, vol. 23, pp , issue 1, B.-S. Song, et al., JSSC, vol. 23, pp , issue 6, B. Ginetti, et al., JSSC, vol. 27, pp , issue 7, S. H. Lewis, et al., JSSC, vol. 27, pp , issue 3, A. N. Karanicolas, et al., JSSC, vol. 28, pp , issue 12, H.-S. Lee, JSSC, vol. 29, pp , issue 4, S.-Y. Chin et al., JSSC, vol. 31, pp , issue 8, O. E. Erdogan, et al., JSSC, vol. 34, pp , issue 12, 1999.

63 Spring 2014 S. Hoyos-ECEN Algorithmic ADC Hardware-efficient, but relatively low conversion speed. Binary search algorithm. Loopgain (2X) requires the use of a residue amplifier, but greatly simplifies the DAC 1-bit, inherently linear. Residue gets amplified each time it circulates the loop; the gain makes the later conversion steps (the LSB s) insensitive to circuit noise and distortion. Conversion errors (residue error due to loopgain nonidealities and comparator offset) made in the earlier conversion cycles also get amplified again and again overall accuracy is usually limited by the MSB resolving and residue generation step. Digital redundancy is often used to treat comparator/loop offsets. Trimming/calibration/ratio-independent techniques are often used to treat loopgain error.

64 Precision Techniques Spring 2014 S. Hoyos-ECEN

65 Spring 2014 S. Hoyos-ECEN Ratio-Independent Multiply-By-N Circuit (1) (2) (3) C 2 C 2 C 1 C 1 C 1 C 2 V i A V o (1) V o (2) A A V o (3) Sampling Charge transfer C 1 -C 2 exchanged Steps (1) and (2) are repeated for N times. C 2 functions as a temporary charge storage.

66 RA Gain Trimming V i + C 1 C 2 Trim array V X + V X - A V o + V o - C 1 /C 2 = 2 nominally V i - C 1 C 2 Precise gain-of-two is achieved by adjustment of the trim array. Finite-gain error of op-amp is also compensated (not nonlinearity). Spring 2014 S. Hoyos-ECEN

67 Spring 2014 S. Hoyos-ECEN Split-Array Trimming DAC V i + 1.2C 2C V X + C 2C 4C 8C C 2C 4C 8C 8-bit gain setting + sign C 2C 4C 8C C 2C 4C 8C V i - 1.2C 2C V X - Successive approximation is performed to find the correct gain setting. Coupling cap is slightly increased to ensure segment overlap.

68 Spring 2014 S. Hoyos-ECEN Digital Calibration V R MSB=0 V o MSB=1 D o S 1 S 2 MSB=1 0 V i MSB=0 S 1 S 2 0 -V R V R -V R V i V R RA gain is set lower than 2X, forcing missing codes but NOT missing decision levels. Calibration is performed by measuring distance between S 1 and S 2 ; (S 2 -S 1 ) is later subtracted from D o (gain error and offset remain).

69 Spring 2014 S. Hoyos-ECEN Digital Calibration Φ 1e Φ 2 C 3 Φ 2 Φ 1 C 2 Φ 1e C 1 = C 2 V i -V R V R Decoder Φ 1 C 1 Φ 2 Residue Amplifier A V o V o C 3 = βc 1 AZ SC amplifier C C V 2b 1 2 C 2 C 2Vi 2b1 V 1 β i R 3 1 C V 1 R

70 Capacitor Error-Averaging Φ 1 Φ 2 Φ 3 C 1 C 1 C 2 C 2 C 2 C 1 V i V R V x1 V R V x2 A 1 A 1 A 1 V x 1 1 δ C, C2 1 +Δ -Δ 2V i -V R V x1 C 1 C2 Vi C 1 C 2 V R 2V i V R δv V, i R Φ 1 Φ 2 V x 2 C C Φ 3 V x2 1 Vi C 2 2 C V 1 R 2V i V R δv V. i R Inherently linear capacitor error-averaging techniques for pipelined A/D conversion Yun Chiu;Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on Volume 47, Issue 3, March 2000 Page(s): Spring 2014 S. Hoyos-ECEN

71 Spring 2014 S. Hoyos-ECEN Capacitor Error-Averaging Φ 2 Φ 3 C 3 C 3 C 4-1 C 4 V x1-1 V x2 V o A 2 A 2 V o C 3 2C4, 2V i -V R C C V C V C, Vx1 3 4 o 3 x2 4 Φ 1 Φ 2 Φ 3 V o V x1 V 2 x2 2V i V R,

72 Spring 2014 S. Hoyos-ECEN Capacitor Error-Averaging C C1 C C1 1 δ 1 2 δ 2 C 2C1 C C1 3 δ 3 4 δ 4 Assume,,, δ, are zero mean Gaussian with variance. δ1 δ δ Find an expression for Vo and comment on the effectiveness of the capacitor error-averaging technique.

73 Spring 2014 S. Hoyos-ECEN References 1. P. W. Li, et al., JSSC, vol. 19, pp , issue 6, C. Shih, et al., JSSC, vol. 21, pp , issue 4, H. Ohara, et al., JSSC, vol. 22, pp , issue 6, H. Onodera, et al., JSSC, vol. 23, pp , issue 1, B.-S. Song, et al., JSSC, vol. 23, pp , issue 6, B. Ginetti, et al., JSSC, vol. 27, pp , issue 7, S. H. Lewis, et al., JSSC, vol. 27, pp , issue 3, A. N. Karanicolas, et al., JSSC, vol. 28, pp , issue 12, H.-S. Lee, JSSC, vol. 29, pp , issue 4, S.-Y. Chin et al., JSSC, vol. 31, pp , issue 8, O. E. Erdogan, et al., JSSC, vol. 34, pp , issue 12, 1999.

74 Subranging ADC Spring 2014 S. Hoyos-ECEN

75 Spring 2014 S. Hoyos-ECEN Subranging ADC Architecture V RT V RB Coarse Encoder MSB s V i Fine Flash Coarse Flash Fine Encoder LSB s

76 Spring 2014 S. Hoyos-ECEN Subranging ADC Pros Reduced complexity 2*(2 N/2-1) comparators Reduced C in, area, and power consumption No residue amplifier required Cons Typically 3 clock phases per conversion Sample Coarse comparison Fine comparison THA required (two-stage S/H if the front-end SHA only holds for one phase) Offset tolerance on fine comparators is at N-bit level. Offset tolerance on coarse comparators is also at N-bit level without digital redundancy.

77 Spring 2014 S. Hoyos-ECEN Example Block Diagram V RT V i Reference Ladder MUX SHA SHA Coarse ADC Fine ADC MSB s 4 bits LSB s 5 bits Encoder 8 bits D o V RB Redundancy in fine ADC provided by over- and under-range comparators

78 Spring 2014 S. Hoyos-ECEN Digital Redundancy of Fine ADC V R 1 V R 2 To Coarse CMP s V i Extra CMP s Fine Encoder + Error Correction Extra CMP s Search range of the fine ADC is extended on both sides.

79 Spring 2014 S. Hoyos-ECEN Two-Step ADC V i SHA SHA 2 n 1 Fine ADC LSB s RA Coarse ADC D/A V R MSB s V R Coarse-fine two-step subranging architecture Conversion residue is produced instead of switching reference taps. A DAC and a subtraction circuit are required. Residue gain can be provisioned to relax offset tolerance in fine ADC.

80 Spring 2014 S. Hoyos-ECEN Timing Diagram Sample V i Coarse ADC DAC + RA Fine ADC Four conversion steps can be pipelined. Usually DAC + RA settling takes the longest time. RA is often omitted (residue gain of one) to speed up conversion.

81 Spring 2014 S. Hoyos-ECEN References 1. A. G. F. Dingwall et al., JSSC, vol. 20, pp , issue 6, J. Doernberg et al., JSSC, vol. 24, pp , issue 2, B.-S. Song et al., JSSC, vol. 25, pp , issue 6, T. Matsuura et al., CICC, 1990, pp. 6.4/1-6.4/4. 5. B. Razavi et al., JSSC, vol. 27, pp , issue 12, C. Mangelsdorf et al., ISSCC, 1993, pp W. T. Colleran et al., JSSC, vol. 28, pp , issue 12, K. Kusumoto et al., JSSC, vol. 28, pp , issue 12, K. Sone et al., ISSCC, 1993, pp , R. Jewett et al., ISSCC, 1997, pp , B. P. Brandt et al., JSSC, vol. 34, pp , issue 12, H. Pan et al., JSSC, vol. 35, pp , issue 12, R. C. Taft et al., JSSC, vol. 36, pp. 331, issue 3, H. van der Ploeg et al., JSSC, vol. 36, pp , issue 12, J. Mulder et al., JSSC, vol. 39, pp , issue 12, 2004.

82 Pipeline ADC Spring 2014 S. Hoyos-ECEN

83 Pipeline ADC Architecture n 1 bits n 2 bits n 3 bits n k bits V in Stage V 1 Stage V 2 Stage V 3 V k Stage k V 1 S/H 2 n 2 V 2 A/D n 2 bits D/A Residue amp A multi-stage subranging ADC with inter-stage gain An unrolled algorithmic ADC Spring 2014 S. Hoyos-ECEN

84 Spring 2014 S. Hoyos-ECEN Pipeline Timing Diagram Φ 1 S1 samples S1 samples S2 DAC+RA S3 samples Φ 2 S1 DAC+RA S2 samples S1 DAC+RA S2 samples S3 DAC+RA S1 CMP S2 CMP S1 CMP S3 CMP Two-phase nonoverlapping clock is typically used, with the coarse ADC s operating within the nonoverlapping times. All pipeline stages operate simultaneously, increasing throughput (at the cost of latency).

85 Spring 2014 S. Hoyos-ECEN b/s Residue Amplifier Φ 2 V i Φ 1 C 1 -V R /4 Φ 1 C 2 A V o V R /4 Φ 1e -V R 0 V R Decoder Φ 2 Inter-stage digital redundancy relaxes the tolerance on CMP offset. 2X gain + 3-level DAC + subtraction all integrated.

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93 Spring 2014 S. Hoyos-ECEN b/s Residue Amplifier Φ 2 V i Φ 1 C 1 Φ 1 C 2 V R 1 V R 6... Φ 1 C 3 6 CMP s Φ 1 C 4 A V o -V R Φ 2 Φ 1e 0 V R Decoder Φ 2 Φ 2

94 Spring 2014 S. Hoyos-ECEN b/s RA Transfer Characteristic V R V o b=0 b=1 b=2 b=3 b=4 b=5 b=6 V R /2 0 V i -V R /2 -V R -5V R /8-3V R /8 -V R /8 V R /8 3V R /8 5V R /8 V R 6 comparators + 7-level DAC are required. Max tolerance on comparator offset is ±V R /8.

95 Spring 2014 S. Hoyos-ECEN b/s RA Transfer Characteristic HW: - Plot the transfer functions of the 2.5-b stage with redundancy and without redundancy. Also plot the plain 2-b transfer function. - Use a tone test input signal and introduce a V R /8 Offset in the comparators. Plot Vo and the SNR in each case.

96 Spring 2014 S. Hoyos-ECEN RA Gain Error and Nonlinearity V R V R /2 b=0 b=1 b=2 V o D o 0 V i -V R /2 -V R -V R /4 V R /4 V R 0 -V R V i V R Raw accuracy is usually limited to bits w/o error correction. Similar correction techniques applied to algorithmic ADC can be used.

97 Spring 2014 S. Hoyos-ECEN Front-End Clock Skew bits/stage err.-corr. ±V FS ±V FS ±V FS range # of cmps Digital redundancy allows tolerance on sampling clock skew. Dedicated front-end SHA can be used to eliminate the problem, but introduces power and area overhead.

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99 Spring 2014 S. Hoyos-ECEN Pipeline ADC Pros Architecture complexity is proportional to the resolution N = Σn j. Small C in, area, and power consumption Throughput is greatly improved with pipelining. Comparator offset tolerance is greatly relaxed with inter-stage gain and digital redundancy. Inter-stage gain enables the stage scaling to further save power. Cons Typically 3 conversion operations involved (slower than flash) Sample Coarse comparison DAC and residue generation High-gain op-amps are required to generate accurate residue signals, which limits the conversion speed. Long latency may be problematic for certain applications.

100 Stage Scaling of Pipeline ADC Stage size, power, area... stage 1 stage 2 stage 3 stage k-1 stage k S 1 Input-referred kt/c noise... Same C for all the stages. Assume 1.5 b/s architecure, the total noise is : N Total KT... C 4C 16C All stages are identically sized same capacitors, op-amps, comparators. Later stages are obviously oversized due to inter-stage gains. Spring 2014 S. Hoyos-ECEN

101 Spring 2014 S. Hoyos-ECEN Stage Scaling of Pipeline ADC Stage size, power, area... stage 1 stage 2 stage 3 stage k-1 stage k S n 2 2 j Input-referred kt/c noise... C is scaled by the squared of the gain for all the stages. Assume 1.5 b/s architecure, the total noise is : N Total KT... k KT / C C C C Stages are sized such that the input-referred noises are the same. Later stages are overly sized optimum scaling factor S 2 n j.

102 Spring 2014 S. Hoyos-ECEN Stage Scaling of Pipeline ADC If C is scaled by the gain for all the stages and assuming 1.5 b/s architecure, the total noise is : N Total Optimum scaling will be somewhere from scaling by the gain squared and scaling by just the gain KT... C C C Need to take into account other sources of noise in the overall expression. Example: for 6 stages of 2.5b/s, if we assume scaling by interstage gain of 16 to get equal noise contribution from each stage. Total noise will be: NTotal KT... 6n f KT / C C C C Vpp SNR 6KT C C in in 2.5pF 2 / V pp 2V

103 Spring 2014 S. Hoyos-ECEN OTA Design Single path At 500MHz, settling time 1ns For 13b, output should settle to 0.01% accuracy, nearly 9*ζ 2.5b stage feedback factor is ¼ GBW 5.73GHz

104 Spring 2014 S. Hoyos-ECEN OTA Design Dual path Time interleaving At 250MHz, settling time 2ns For 13b, output should settle to 0.01% accuracy, nearly 9*ζ 1.5b stage feedback factor is 1/2 GBW 1.43GHz

105 Spring 2014 S. Hoyos-ECEN Possible Topologies Reverse Nested Miller Compensated for high gain Single stage will have the best settling behavior With calibration, DC gain can be reduced to increase GBW Folded Cascode

106 Spring 2014 S. Hoyos-ECEN References D. W. Cline and P. R. Gray, "A power optimized 13-b 5-Msamples/s pipelined analog-to-digital converter in 1.2-μm CMOS," IEEE Journal of Solid-State Circuits, vol. 31, no. 3, pp , Mar kt/c Constrained Optimization of Power in Pipeline ADCs - Yu Lin, Vipul Katyal, Randall Geiger Dept. Electrical and Computer Engineering, Iowa State University Ames, IA, 50010, USA Mark Schlarmann Freescale Semiconductor, Inc. Kwok, P.T. F. and Luong, Howard C, Power Optimization for Pipeline Analog-to-Digital Converters, IEEE transactions on circuits and systems II: Analog and digital signal processing, Vol. 46, No. 5, May 1999, pp Background Digital Error Correction Technique For Pipelined Analog-digital Converters Sameer R. Sonkusale and Jan Van der Spiegel Digital Background Calibration Technique for Pipeline ADCs with Multi-bit Stages Antonio J. Ginés, Eduardo J. Peralías and Adoración Rueda

107 Spring 2014 S. Hoyos-ECEN Pipeline Calibration Methods Foreground Calibration Background Calibration Interruption of ADC signal Cannot correct for environmental changes and variations with time E.g. Radix based Works without interruption of normal operation E.g. - LMS based

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111 Spring 2014 S. Hoyos-ECEN LMS based calibration n Ref. ADC Analog Input ADC x(n) Adaptive Dig. Filter y(n) n d(n) e(n) Channel Adaptive Equalizer

112 Spring 2014 S. Hoyos-ECEN Single Stage Calibration Calibration of a single stage at a time Different variations of LMS to reduce computational complexity

113 Spring 2014 S. Hoyos-ECEN Simultaneous Multistage Calibration

114 Spring 2014 S. Hoyos-ECEN Matlab Simulations Amplitude DFT plot before calibration frequency SNR 45.74dB Amplitude DFT plot after calibration Frequency SNR 77.26dB Without offset and finite gain

115 Spring 2014 S. Hoyos-ECEN Matlab Simulations 0.01 Error between filter output and expected output Weights Error Weight value Iteration Iteration Final Weights Non-ideal Weights

116 Spring 2014 S. Hoyos-ECEN Matlab Simulations 100 DFT plot before calibration 100 DFT plot after calibration Amplitude Amplitude frequency SNR db Frequency x 10 8 SNR db With offset and finite gain errors

117 Spring 2014 S. Hoyos-ECEN Matlab Simulations 0.08 Error between filter output and expected output Error Iteration

118 Spring 2014 S. Hoyos-ECEN Matlab Simulations 0.35 Alpha 1.4 Beta Value Value Iteration x Iteration x 10 4 Weights Alpha and Beta

119 Spring 2014 S. Hoyos-ECEN Code-Domain Adaptive Equalization n Ref. ADC Analog Input ADC x(n) Adaptive Dig. Filter y(n) n d(n) e(n) Channel Adaptive Equalizer Speed and Accuracy decoupled Simple analog circuits can be used for high speed Precision shifted from analog domain to digital domain

120 Spring 2014 S. Hoyos-ECEN Multi-Stage ADC Gain Error 1-bit/stage Ideal ADC ADC with gain error D o D o D1 D2 D3 D D1 D2 D3 D a a a a a a Accumulated Gain Mismatch

121 Spring 2014 S. Hoyos-ECEN ADC Calibration: Filtering Approach Ref. Path Analog Input ADC x(n) Digital Correction y(n) d(n) e(n)

122 Spring 2014 S. Hoyos-ECEN ADC Calibration: Filtering Approach Ref. Path Wiener Filter Analog Input ADC x(n) Digital Correction y(n) d(n) e(n) Unknown System System Inversion System inversion is a well known filtering problem Also known as Equalization in digital communication

123 Spring 2014 S. Hoyos-ECEN Code-Domain Adaptive Equalization n Ref. ADC Analog Input ADC x(n) Adaptive Dig. Filter y(n) n d(n) e(n) Channel Adaptive Equalizer Speed and Accuracy decoupled Simple analog circuits can be used for high speed Precision shifted from analog domain to digital domain

124 LMS Digital Filter Architecture Pipelined ADC S 1 S 2 S 3 S 4 S 5 S 6 S D i d D o D out n Reference ADC + error Nonlinear LMS Filter Linear LMS Filter Digital Error Correction 1.5b/s, 2.5/s Calibrate from LSB to MSB stage Last two stages are not calibrated Spring 2014 S. Hoyos-ECEN

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147 Spring 2014 S. Hoyos-ECEN References 1. S. H. Lewis et al., JSSC, vol. 27, pp , issue 3, S. Sutarja et al., JSSC, vol. 23, pp , issue 6, B.-S. Song et al., JSSC, vol. 23, pp , issue 6, Y.-M. Lin et al., JSSC, vol. 26, pp , issue 4, A. N. Karanicolas et al., JSSC, vol. 28, pp , issue 12, K. Sone et al., JSSC, vol. 28, pp , issue 12, J. Wu et al., ISCAS, 1994, pp vol T.-H. Shu et al., JSSC, vol. 30, pp , issue 4, T. B. Cho et al., JSSC, vol. 30, pp , issue 3, P. C. Yu et al., JSSC, vol. 31, pp , issue 12, D. W. Cline et al., JSSC, vol. 31, pp , issue 3, L. A. Singer et al., VLSI, 1996, pp S.-U. Kwak et al., JSSC, vol. 32, pp , issue 12, K. Y. Kim et al., JSSC, vol. 32, pp , issue 3, J. M. Ingino et al., JSSC, vol. 33, pp , issue 12, 1998.

148 Spring 2014 S. Hoyos-ECEN References 16.I. E. Opris et al., JSSC, vol. 33, pp , issue 12, I. Mehr et al., JSSC, vol. 35, pp , issue 3, D. Miyazaki et al., ISSCC, 2002, pp , B.-M. Min et al., JSSC, vol. 38, pp , issue 12, B. Murmann et al., JSSC, vol. 38, pp , issue 12, X. Wang et al., CICC, 2003, pp J. Li et al., CICC, 2003, pp Y. Chiu et al., JSSC, vol. 39, pp , issue 12, E. Siragusa et al., JSSC, vol. 39, pp , issue 12, C. R. Grace et al., ISSCC, 2004, pp , 539.