A 14b 40Msample/s Pipelined ADC with DFCA

Transcription

1 A 14b 40Msample/s Pipelined ADC with DFCA Paul Yu, Shereef Shehata, Ashutosh Joharapurkar, Pankaj Chugh, Alex Bugeja, Xiaohong Du, Sung-Ung Kwak, Yiannis Papantonopoulos, Turker Kuyel Texas Instruments, Inc., Dallas TX

2 Outline Description of a Pipelined Architecture Error Sources in a Pipelined ADC Technique I: DAC and Feedback Capacitor Averaging (DFCA) Technique II: Mismatch Noise Cancellation (MNC) Conclusion Paul Yu 2 paulyu@alum.mit.edu

3 A Pipelined Architecture Stage 1 Stage 2 Stage 3 V IN SHA Σ 2 m1-1 V RES1 ADC DAC m1 bits MSB m1 bits m2 bits mn bits LSB Paul Yu 3 paulyu@alum.mit.edu...

4 Outline Description of a Pipelined Architecture Error Sources in a Pipelined ADC Technique I: DAC and Feedback Capacitor Averaging (DFCA) Technique II: Mismatch Noise Cancellation (MNC) Conclusion Paul Yu 4 paulyu@alum.mit.edu

5 Error Sources in Pipelined ADC Problems Comparator Offsets Finite Op-Amp Gain kt/c Noise Capacitor Mismatch DAC Error Interstage Gain Error Solutions Digital Error Correction High Gain Op-Amps Large Cap Trimming/Calibration, or DFCA, DFCA+MNC (SFDR), (SFDR/SNR) Paul Yu 5 paulyu@alum.mit.edu

6 High Resolution ADC Techniques Techniques Pro Con Factory Calibration/ Trimming Digital Self Calibration Simple Test Time, Extra Analog Hardware Min. Analog User Burden Background Calibration Test Time, Background DAC or Interstage Gain Only CFCS Simple DNL Only Proposed DFCA + MNC Test Time, Background Min. Analog Extra Digital Paul Yu 6 paulyu@alum.mit.edu

7 Block diagram of the ADC Chip I with DFCA Chip II with DFCA + MNC V IN Stage 1 Stage 2 Stage 3 Stage 6 PNG Digital Error Correction 12 M N C 14 Paul Yu 7 paulyu@alum.mit.edu

8 Outline Description of a Pipelined Architecture Error Sources in a Pipelined ADC Technique I: DAC and Feedback Capacitor Averaging (DFCA) Technique II: Mismatch Noise Cancellation (MNC) Conclusion Paul Yu 8 paulyu@alum.mit.edu

9 Implementation of 2.8b/Stage Feedback Capacitor DAC Capacitors C 1 C 2 V IN C 3 C 4 S Sampling Phase a VREF b VREF c VREF V OUT Paul Yu 9 paulyu@alum.mit.edu C 2 C 3 C 4 Convention al : a,b,c DFCA : a,b,c { 1,0, 1} { 1,0, 1}, f = 2 DFCA Amplifying Phase C 1

10 DAC Errors Only C2 V REF C1 V RES1 V IN Ideal C2 = 1 + ε C3 = 1 - ε D OUT V IN Paul Yu 10 paulyu@alum.mit.edu

11 Interstage Gain Error Only V RES1 4 1 C C1 i V IN Ideal C1 = 1 - ε C1 = 1 + ε D OUT V IN Paul Yu 11 paulyu@alum.mit.edu

12 6 Pre-Amps 3b ADC f1 a1 b1 c1 f0 a0 b0 c0 Parallel Shuffling PN1 PN2 PN1 PN2 Example: PN3 PN3 PN3 PN3 Paul Yu 12 a1 c1 f1 b1 a0 c0 f0 b0 V REF+ V CM C 1 C 2 C 3 C 4 PN1 = 1, PN2 = 1, PN3 = -1 a1a0 = +1, b1b0 = 0, c1c0 = 0 V REF- VOUT

13 Analog Domain Shuffling V REF+ V CM V IN V REF- V OUT Preamps Parallel Shuffling Network 3b ADC Latch Bank Cap Select Logic C 1 C 2 C 3 C 4 V OUT φ1 φ2 Paul Yu 13 paulyu@alum.mit.edu

14 (db) DFCA Results (Chip I) f s = 5MSample/s f in th 3rd (MHz) 5th f in 3rd (MHz) DFCA SFDR SNR THD DFCA SFDR SNR THD Off 83 db 77 db 81 db On 95 db 74 db 93 db Paul Yu 14 paulyu@alum.mit.edu

15 DFCA Results (Chip I) (db) f s = 40 MSample/s f in f in 3rd 3rd 5th 5th (MHz) DFCA SFDR SNR THD (MHz) DFCA SFDR SNR THD Off 78 db 77 db 77 db On 84 db 73 db 80 db Paul Yu 15 paulyu@alum.mit.edu

16 SFDR vs. Conversion Speed (Chip I) f in =1MHz DFCA ON DFCA OFF db Msample/s Paul Yu 16 paulyu@alum.mit.edu

17 Outline Description of a Pipelined Architecture Error Sources in a Pipelined ADC Technique I: DAC and Feedback Capacitor Averaging (DFCA) Technique II: Mismatch Noise Cancellation (MNC) Conclusion Paul Yu 17 paulyu@alum.mit.edu

18 Transmit Noise Cancellation CDMA Analogy X: Y: PN: Receive Y: X: PN: Paul Yu 18 paulyu@alum.mit.edu

19 V IN ADC m1 bits a 1 = b -1 DAC Noise Cancellation a b PN Stage PN Σ Small D2 Accum & Avg Galton, IEEE CAS II, March 2000 Paul Yu 19 paulyu@alum.mit.edu Σ V 2 m1-1 IN V RES1 :D2 = Q V PN Stage 2... RES ADC DAC Noise ' + PN 1 2 D2

20 Mismatch Noise Cancellation V IN ADC m1 bits Stage 1 DAC Σ 2 m1-1 V RES1 Gain Noise Σ DAC Noise Stage 2... A D2 D C V RES1 { V ' (Gain Noise) DACNoise} D2 = Q RES1 + i D2 Accum i & Avg PN i PN i Paul Yu 20 paulyu@alum.mit.edu

21 MNC Architecture in Chip II V RES1 Stage 1 Stages 2-6 Estimation Logic PN i PN i 3 Accumulate & Average i (Cap Mismatch) Cancellation Logic 14 Paul Yu 21 paulyu@alum.mit.edu

22 MNC Experimental Results (Chip II) (db) (MHz) (MHz) (MHz) DFCA SFDR SNR DFCA SFDR SNR MNC SFDR SNR Off 48dB 55dB ON 80dB 50dB ON 80dB 73dB Paul Yu 22 paulyu@alum.mit.edu

23 Chip II Micrograph Pipelined Stages 1-6 M N C Clock Paul Yu 23 paulyu@alum.mit.edu

24 Conclusion DFCA Increases SFDR Parallel Shuffling Reduces Number of Switches in Series Analog Domain Operation Minimizes Non-Overlapping Time MNC Increases SNR by Digitally Removing both DAC and Gain Noise DFCA+MNC Background Calibration Enables High SFDR, High SNR ADC s Paul Yu 24 paulyu@alum.mit.edu

25 Acknowledgement Discussion of DNC and MNC with Dr. Ian Galton is greatly appreciated. Discussion with Dr. Ranjit Gharpurey and other Members of the Mixed Signal Product Group at TI is acknowledged. Paul Yu 25