High-speed ADC techniques - overview and scaling issues - Vladimir Stojanovic

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1 High-speed ADC techniques - overview and scaling issues - Vladimir Stojanovic

2 Outline High-Speed ADC applications Basic ADC performance metrics Architectures overview ADCs in 90s Limiting factors Conclusion 06/14/2001 Vladimir Stojanovic 2

3 High-speed ADC applications Wireless LAN Data Channel (1-50MS/s, 6-10b) Magnetic Storage Read Channel ( MS/s, 6-8b) ADSL data channel (3-10MS/s, 12-16b) Digital Multi-Standard TV Baseband ADC (20MS/s, 8-10b) CATV Decoder Modem ADC (10-20MS/s, 8-10b) HDTV various apps (50-75MS/s, 10b) Digital-IF for Multi-standard Broadcast TV rcvr ( Mb/s, 8-12b) Serial high-speed links with MPAM modulation (5-10Gs/s, 4-6b) 06/14/2001 Vladimir Stojanovic 3

4 Basic ADC performance metrics Aperture time uncertainty Peak SNR SNRp=6.02N+1.76 [db] Aperture time uncertainty Aperture time Effective # of bits SNDR=6.02ENOB+1.76[dB] Digital out MSB Dynamic range DR=P full scale sin /P sin@0db SNR Spurious Free Dynamic Range LSB Gain error 100 Static errors: DNL - differential non-linearity INL - integral non-linearity Offset INL DNL+LSB Analog in Gain error V FS /8 V FS /2 V FS 06/14/2001 Vladimir Stojanovic 4

5 Flash Interpolation Averaging Folding Architectures Folding and Interpolation Two-step Subranging Flash Pipeline Per-stage calibration 06/14/2001 Vladimir Stojanovic 5

each comparator Flash ADC comparator 0 0 0 0 1 1 1 1 Example: 3 bit Flash ADC

6 Best up to 8 bits: + Speed + Simplicity - Exponential complexity - Big input capacitance - Bubbles in thermo code - Power - Difference in signal delay to each comparator Flash ADC comparator Example: 3 bit Flash ADC 2 3 pre-amplifiers 2 3 comparators pre-amplifier 06/14/2001 Vladimir Stojanovic 6

7 Interpolation in Flash ADC V r12 V r1 V r2 Reduced # of pre-amps smaller input capacitance less power than full flash Improved DNL due to distribution of errors 06/14/2001 Vladimir Stojanovic 7

8 Averaging in Flash ADC Pre-amps reduce effect of comparator offset (~ 15-50mV) But introduce offsets (~3mV-10mV) Solution Average out the pre-amplifier offsets with resistor network 06/14/2001 Vladimir Stojanovic 8

9 Effect of Averaging 06/14/2001 Vladimir Stojanovic 9

10 Averaging effect on offset, INL, DNL neighboring signals highly correlated after averaging =(V n-2 -V n+3 )/5 and σ σ = average individual 5 DNL improves with # of averaging stages INL, offset improve with square-root of averaging stages 06/14/2001 Vladimir Stojanovic 10

11 Folding and Two-step ADCs Two architectures, same idea: - Folding - Two-step - Coarse ADC gets MSBs and residue - Fine ADCs get LSBs from residue 06/14/2001 Vladimir Stojanovic 11

12 Folding ADC FM FP FP FM Example: 3bit, 4x Folding ADC Folder 1 06/14/2001 Vladimir Stojanovic 12

13 Folding ADC: Block Diagram Folding tradeoff + Fewer comparators - Faster signals Fold x 4 + From 8 to 2 comparators - max. Fout > 4 Fin Critical issue is to match timing of coarse ADC and fine (folded) ADCs Non-linearity around the folding point significantly reduces performance if amplitude is quantized 06/14/2001 Vladimir Stojanovic 13

14 Folding & Interpolating ADC Example: 6bit, 4x fold, 2x interpolate ADC With interpolation only detect zero crossing points 06/14/2001 Vladimir Stojanovic 14

15 Two-step: subranging ADC + 2(2 N/2-1) comparators Coarse bank selects which part of reference ladder to connect to fine bank - Speed limited by settling of fine references parasitic capacitance from > 2 N switches + large kickback 06/14/2001 Vladimir Stojanovic 15

16 Two-step: Flash ADC Two-step ADC accuracy challenges 06/14/2001 Vladimir Stojanovic 16

17 Pipelined ADC All stages process different data simultaneously - throughput only depends on speed of each stage - complexity traded for latency 06/14/2001 Vladimir Stojanovic 17

18 Effect of stageadc non-linearity errors 06/14/2001 Vladimir Stojanovic 18

19 Removing stageadc non-linearity errors 06/14/2001 Vladimir Stojanovic 19

20 Interstage gain error propagation G E models interstage gain error Only need to correct for the red block in each stage! 06/14/2001 Vladimir Stojanovic 20

21 Interstage gain error calibration 06/14/2001 Vladimir Stojanovic 21

22 Time-Interleaved, pipelined ADCs Gain mismatch => Amplitude Modulation Offset mismatch => Additive Tones Timing mismatch => Phase modulation 06/14/2001 Vladimir Stojanovic 22

23 Gain and offset calibration 06/14/2001 Vladimir Stojanovic 23

24 Calibration results SNDR limited by mismatches SNDR limited by non-linear mismatches 06/14/2001 Vladimir Stojanovic 24

25 Analyzed a bunch of ADCs different technologies different specs Use metrics from digital domain to see how ADCs scale with mainstream digital CMOS Two main metrics: ADCs in 90s } How to compare? Delay of fan-out of 4 inverter (FO4) Energy dissipated driving the gate of minimum size inverter (MSI) 06/14/2001 Vladimir Stojanovic 25

26 Unit Delay Unit Energy Approach: Metrics 500 ps FO4 = Lch [ µ m] µ m 2 ff 12 ff = ( 4 + 8) λ = Lch[ m] µ m µ m Normalize sampling period to FO4 Energy/sample=Power/Rate Normalize Energy/sample by MSI ED=normalized Energy * normalized Sampling period Figure of merit FM~ Resolution*ln2 ln(ed) 06/14/2001 Vladimir Stojanovic 26 Cg 6 ff MSI = Lch [ µ m] Vdd µ m MSI µ 2

27 ADCs in 90s: Raw data Author Conf/Jour. ResolutionSpeed [MS/sTech. [um] P [mw] Vdd [V] A [mm2] INL [LSB] DNL [LSB] ENOB SNDR SFDR Cin [ff] M. Choi ISSCC G. Geelen ISSCC K. Nagaraj JSSC Y. Tamba ISSCC K.Yoon ISSCC B. Song VLSI K. Nagaraj JSSC M. Flynn ISSCC S.Tsukamot ISSCC J. Spalding ISSCC R. Roovers JSSC S.Tsukamot JSSC Style Full-Flash with preamp & two stage averaging Flash, 3 avg, 2 interpolate, distrib T/H Flash, interleaved S/H, interpolation Flash, offset comp. per comp, distrib T/H Flash, interpol., auto-zero (bg), intern T/H Flash,Current Interpolation, low-supply Flash with 1-bit folding Flash,Folding,interpolating current mode Full-Flash with interleav. auto-zero error cor Full-Flash, auto-zero comparators Current Interpolation Full-Flash, interl auto-zero, chopper comp J. Ming ISSCC K. Yoon VLSI Y-T. Wang JSSC M-J. Choe VLSI W. Bright ISSCC K. Nagaraj JSSC A. Venes ISSCC M.Flynn ISSCC B. Nauta ISSCC M.Pelgrom JSSC C. Conroy JSSC Y. Park ISSCC B. Brandt ISSCC H. v.d.ploegisscc K. Dyer ISSCC D. Fu ISSCC A. Abo VLSI K. Bult ISSCC pipelined, inter-stage bg calibration Flash, fold. & interpol, w. equalizing preamp Sliding window pipe. interpolation, dual ch. pipelined folding parallel, pipelined, dual sampling, 1.5b/stage parallel, pipelined, dual sampling, 1.5b/stage folding&interp, distrib T/H folding&interp, current mode interpolation folding&interpolating Full-Flash optimized for random offset 4-way interleaved, pipelined 1.5b/stage pipelined, 1.5b/stage, no calibration Two-step, subranging, interpolated comps Two-step, offs comp res. amp, ladder sharing 3-way interl, pipelined, mix signal bg calib 2-way interl, pipelined, digital bg calib LMS pipelined, 1.5b/stage, no calib, low power Flash, improved averaging, folding 06/14/2001 Vladimir Stojanovic 27

28 ADCs in 90s: Scaled data Labels Author Resolution Ts [FO4] Tech. [um] Vdd [V] A [M ] ED/s E/s[k MSI] Emsi [fj] E/s [fj] FM [6_1] M. Choi [6_2] G. Geelen [6_3] K. Nagaraj [6_4] Y. Tamba [6_5] K.Yoon [6_6] B. Song [6_7] K. Nagaraj [6_8] M. Flynn [6_9] S.Tsukamoto [6_10] J. Spalding [6_11] R. Roovers [6_12] S.Tsukamoto x100 [8_1] J. Ming [8_2] K. Yoon [8_3] Y-T. Wang [8_4] M-J. Choe [8_5] W. Bright [8_6] K. Nagaraj [8_7] A. Venes [8_8] M.Flynn [8_9] B. Nauta [8_10] M.Pelgrom [8_11] C. Conroy x1000 [10_1] Y. Park [10_2] B. Brandt [10_3] H. v.d.ploeg [10_4] K. Dyer [10_5] D. Fu [10_6] A. Abo [10_7] K. Bult Style Full-Flash with preamp & two stage averaging Flash, 3 avg, 2 interpolate, distrib T/H Flash, interleaved S/H, interpolation Flash, offset comp. per comp, distrib T/H Flash, interpol., auto-zero (bg), intern T/H Flash,Current Interpolation, low-supply Flash with 1-bit folding Flash,Folding,interpolating current mode Full-Flash with interleav. auto-zero error cor Full-Flash, auto-zero comparators Current Interpolation Full-Flash, interl auto-zero, chopper comp pipelined, inter-stage bg calibration Flash, fold. & interpol, w. equalizing preamp Sliding window pipe. interpolation, dual ch. pipelined folding parallel, pipelined, dual sampling, 1.5b/stage parallel, pipelined, dual sampling, 1.5b/stage folding&interp, distrib T/H folding&interp, current mode interpolation folding&interpolating Full-Flash optimized for random offset 4-way interleaved, pipelined 1.5b/stage pipelined, 1.5b/stage, no calibration Two-step, subranging, interpolated comps Two-step, offs comp res. amp, ladder sharing 3-way interl, pipelined, mix signal bg calib 2-way interl, pipelined, digital bg calib LMS pipelined, 1.5b/stage, no calib, low supply Flash, improved averaging, folding 06/14/2001 Vladimir Stojanovic 28

29 Sampling period vs. technology - 6bit 25 Ts [FO4] 20 [6_12] [6_11] [6_3] [6_4] [6_9] [6_10] [6_8] 5 0 Flash, full Flash, interpolating Folding & interpolating [6_2] [6_1] [6_5] L [µm] /14/2001 Vladimir Stojanovic 29

30 Sampling period vs. technology - 8bit Ts [FO4] [8_10] [8_2] Flash, full Flash, interpolating Folding & interpolating Pipelined [8_1] [8_5] [8_7] [8_4] [8_3] [8_9] [8_6] [8_8] [8_11] L [µm] /14/2001 Vladimir Stojanovic 30

31 Sampling period vs. technology - 10bit Ts [FO4] [10_3] [10_2] [10_6] [10_1] Folding & interpolating Pipelined Two-step Sub-ranging [10_7] [10_4] [10_5] L [µm] /14/2001 Vladimir Stojanovic 31

32 10 3 x Energy* Delay vs. technology - 6bit ED [MSI*FO4] [6_12] [6_9] [6_10] [6_4] [6_11] [6_3] Flash, full Flash, interpolating Folding & interpolating [6_2] [6_1] [6_8] [6_5] L [µm] /14/2001 Vladimir Stojanovic 32

33 10 5 x Energy* Delay vs. technology - 8bit ED [MSI*FO4] Flash, full Flash, interpolating Folding & interpolating Pipelined [8_2] [8_7] [8_4] [8_5] [8_1] [8_3] [8_9] [8_10] [8_11] [8_6] [8_8] L [µm] /14/2001 Vladimir Stojanovic 33

34 10 6 x Energy* Delay vs. technology - 10bit ED [MSI*FO4] Folding & interpolating Pipelined Two-step Sub-ranging [10_3] [10_6] [10_1] [10_2] 10 0 [10_4] [10_7] [10_5] L [µm] 06/14/2001 Vladimir Stojanovic 34

35 16 Figure of merit vs. technology FM [-ln(msi*fo4)] [6_1] [6_3] [6_2] [6_4] [6_9] [8_2] [6_8] [8_4] [10_7] [8_5] [8_7] [6_12] [6_5] [8_3] [6_10] [6_11] [8_9] [8_6] [8_8] [10_5] [10_4] [8_11] 8 [8_1] [10_2] [8_10] [10_1] [10_3] [6_6] [6_7] [10_6] Flash, full Flash, interpolating Folding & interpolating Pipelined Two-step Sub-ranging L [µm] 06/14/2001 Vladimir Stojanovic 35

36 Timing errors 1. Sampling clock jitter Limiting factors 2. Limited rise/fall time of sampling clock 3. Skew of clock & input signal at different places on the chip (1ps = µm on a die) 4. Signal-dependent delay Distortion errors 1. Sampling comparators aperture time 2. Distortion in the linear part of the input amplifier 3. Changes in the reference voltage values & comparator offsets, also kickback 4. Delays of analog signal and clock signal 06/14/2001 Vladimir Stojanovic 36

37 Timing Error performance limitations Definition A: SNR = 20 log10(2πf in εt _ rms) ε t _ rms < 10 (6.02 ENOB 2πf Definition B: in ) / 20 N For max fin=1ghz A:ε trms [ps] B:ε trms [ps] C:ε trms [ps] πf A t < 1LSB = in 2 2 A N Definition C: ε < t _ rms 3π 1 2 N f in ε < t _ rms 3π 2 1 LENOB / 2 f in Taking into account both transmitter and receiver noise and budgeting 50% for other noise 06/14/2001 Vladimir Stojanovic 37

38 Conclusion Future very high speed ADCs Digitally corrected interpolated Flash Time-Interleaved pipelined ADC with channel mismatch calibration Big problem timing errors Most of all jitter after all it is Gaussian noise limit Jitter is less of a problem for digital data communications Spectrum allocation limitations for wireless Most of ADCs need not be very, very high speed 06/14/2001 Vladimir Stojanovic 38

39 6 bit Converters References [6_1] M. Choi and A. Abidi A 6b 1.3GSample/s A/D Converter in 0.35µm CMOS, ISSCC 2001, paper 8.1 [6_2] G. Geelen A 6b 1.1GSample/s CMOS A/D Converter, ISSCC 2001, paper 8.2 [6_3] K. Nagaraj et al. Dual Mode A/D Converter, JSSC 2000, December, vol. 35, no. 12, pp [6_4] Y. Tamba and K. Yamakido A CMOS 6b 500MSample/s ADC for a Hard Disk Drive Read Channel, ISSCC 1999, paper 18.5 [6_5] K. Yoon et al. A 6b 500MSample/s CMOS Flash ADC with a Background Interpolated Auto-Zeroing Technique, ISSCC 1999, paper 18.6 [6_6] B. Song et al. A 1V 50MHz Current-Interpolating CMOS ADC, VLSI Symposium 1999, paper 8.3 [6_7] K. Nagaraj et al. Efficient 6-b A/D Converter Using a 1-bit Folding Front End, JSSC 1999, August, vol. 34, no. 8, pp [6_8] M. P. Flynn and B. Sheahan A 400MSample/s 6b CMOS Folding and Interpolating ADC, ISSCC 1998, paper 9.7 [6_9] S. Tsukamoto et al. A CMOS 6b 400MSample/s ADC with Error Correction, ISSCC 1998, paper 9.8 [6_10] J. Spalding and D. Dalton A 200MSample/s 6b Flash ADC in 0.6um CMOS, ISSCC 1996, paper 19.5 [6_11] R. Roovers and M. S. J. Steyaert A 175Ms/s, 6 b, 160 mw, 3.3 V CMOS A/D Converter, JSSC 1996, July, vol. 31, no. 7, pp [6_12] S. Tsukamoto et al. A CMOS 6-bit, 200Msample/s, 3 V-Supply A/D Converter for a PRML Read Channel LSI, JSSC 1996, November, vol.31, no. 11, pp bit Converters [8_1] J. Ming and S. H. Lewis An 8b 80MSample/s Pipelined ADC with Background Calibration, ISSCC 2000, paper 2.5 [8_2] K. Yoon et al. An 8-bit 125Ms/s CMOS Folding ADC for Gigabit Ethernet LSI, VLSI Symposium 2000, paper 16.2 [8_3] Y. Wang and B. Razavi An 8-bit 150-MHz CMOS A/D Converter, JSSC 2000, March, vol. 35, no. 3, pp [8_4] M. Choe et al. An 8b 100MSample/s CMOS Pipelined Folding ADC, VLSI Symposium 1999, paper /14/2001 Vladimir Stojanovic 39

40 References [8_5] W. Bright 8b 75MSample/s 70mW Parallel Pipelined ADC Incorporating Double Sampling, ISSCC 1998, paper 9.5 [8_6] K. Nagaraj et al. A 250-mW, 8-b, 52-Msample/s, Parallel-Pipelined A/D Converter with Reduced Number of Amplifiers, JSSC 1997, March, vol. 32, no. 3, pp [8_7] A. G. W. Venes and R. J. van de Plassche An 80MHz 80mW 8b CMOS Folding A/D Converter with Distributed T/H Preprocessing, ISSCC 1996, paper 19.4 [8_8] M. P. Flynn and D. J. Allstot CMOS Folding ADCs with Current-Mode Interpolation, ISSCC 1995, paper 16.2 [8_9] B. Nauta and A. G. W. Venes A 70MSample/s 110mW 8b CMOS Folding Interpolating A/D Converter, ISSCC 1995, paper 16.3 [8_10] M. Pelgrom et al. A 25-Ms/s 8-bit CMOS A/D Converter for Embedded Application, JSSC 1994, August, vol. 29, no. 8, pp [8_11] C. Conroy et al. An 8-bit 85MS/s Parallel-Pipeline A/D Converter in 1-um CMOS, JSSC 1993, April, vol. 28, no. 4, pp bit Converters [10_1] Y. Park et al. A 10b 100MSample/s CMOS Piplined ADC with 1.8V Power Supply, ISSCC 2001, paper 8.3 [10_2] B. Brandt and J. Lutsky A 75mW 10b 20MSample/s CMOS Subranging ADC with 59dB SNDR, ISSCC 1999, paper 18.4 [10_3] H. van der Ploeg and R. Remmers A 3.3V 10b 25MSample/s Two-Step ADC in 0.35um CMOS, ISSCC 1999, paper 18.2 [10_4] K. Dyer et al. Analog Background Calibration of a 10b 40MSample/s Parallel Pipelined ADC, ISSCC 1998, paper 9.3 [10_5] D. Fu et al. Digital Background Calibration of a 10b 40MSample/s Parallel Pipelined ADC, ISSCC 1998, paper 9.2 [10_6] A. M. Abo and P. R. Gray A 1.5V, 10-bit, 14MS/s CMOS Pipeline Analog-to-Digital Converter, VLSI Symposium 1998, paper 14.2 [10_7] K. Bult et al. A 170mW 10b 50MSample/s CMOS ADC in 1mm 2, ISSCC 1997, paper /14/2001 Vladimir Stojanovic 40

Another way to implement a folding ADC

Another way to implement a folding ADC J. Van Valburg and R. van de Plassche, An 8-b 650 MHz Folding ADC, IEEE JSSC, vol 27, #12, pp. 1662-6, Dec 1992 Coupled Differential Pair J. Van Valburg and R. van