2.5GS/s Pipelined ADC with Background. Linearity Correction

Transcription

1 A14b25GS/s8-Way-Interleaved 2.5GS/s Pipelined ADC with Background Calibration and Digital it Dynamic Linearity Correction B. Setterberg 1, K. Poulton 1, S. Ray 1, D.J. Huber 1, V. Abramzon 1, G. Steinbach 1, JP J.P. Keane 1, B. Wuppermann 1, M. Clayson 1, M. Martin 2, R. Pasha 2, E. Peeters 3, A. Jacobs 3, F. Demarsin 3, A. Al-Adnani 3, P. Brandt 3 1 Agilent Technologies, Santa Clara, CA 2 Agilent Technologies, Colorado Springs, CO 3 Agilent Technologies, Rotselaar, Belgium

2 Background ADC for Test and Measurement Applications: 2.5 GS/s 14 bits Less than 1 metastable error per year (10-17 metastable error probability) 75 db SFDR from DC to 1 GHz 60 db SNR Works with arbitrary input signals Silicon BiCMOS Process Technology: 150 GHz f T Bipolar NPN 130 nm CMOS 2

3 Problem: Design Considerations Comparator regeneration time constants are too slow to meet the metastability error rate goals at 25GS/s 2.5 GS/s. Solution: Use a time-interleaved i t dadc architecture. t Consequence: Need to address interleaving artifacts. 3

4 Time-Interleaved ed Architecturere ADC Slice 0 ADC Slice ADC Slice N De-interleave Interleave ADC slices need to be very well matched in offset, gain, sample time and bandwidth. 4

5 Interleaving Strategy Achieve an aggregate 2.5 GS/s by interleaving eight MS/s slices. Input 8X MS/s ADC Slices MS/s ADC 5

6 Slice ADC Architecture In 3.5 bits + Voltage to redundancy current 15-level flash converter Stage 1 Gm 1 bit per stage, radix-1.7 current-mode pipeline 1 Stages Radix Conve erter Binary Output Background Calibration Engine 1 K. Poulton, et al., A 4GSample/s 8b ADC in 0.35µm CMOS, ISSCC Dig. Tech. Papers, vol. 45, pp , Feb

7 ADC First Stage Block Diagram To Radix Converter DAC Permuter CLK IN Dither Permute e Address Background Calibration Engine Residue Amp 7

8 ADC Stages 2-16 D D In Dith 1.7 X In 1.7 X Res Res Stg 2 Stg 3 Stg 11 Stg 12 Stg 16 D D D D D In Res Dith In Res Dith In Res Dith In Res In Background Calibration Engine Uncalibrated Stages 8

9 Interleaving Errors Mismatched paths cause: Distortion and jitter Spurs in the spectrum Gain Error (need < 0.01% gain matching) Offset Error Sampling Instant Error (need < 100 µv offsets) (need < 20 fs timing skew) 9

10 Minimize Sampling Time Errors with a 2-rank Track and Hold Input Rank 1 T/H 2.5GS/s Low- Jitter Sampling Clock (<70 fs RMS) ) 8X MS/s ADC Slices Rank 2 T/H MS/s ADC First rank T/H clocked at full system sample rate Sampling instant defined by first T/H Insensitive to errors from slice-rate clocks 10

11 Slice-to-Slice Gain & Offset Alignment Dither DAC Dither Chop PRBS ADC Ga ain Of ffset Background Calibration Engine Injected dither provides an absolute gain reference Chopping allows offset calibration with arbitrary input 11

12 Chop and Dither Injection M3 R1 R2 M4 Dither Out Bootstrap amplifiers Q1 Q3 Q2 Q4 Chop PRBS In In M1 M2 Liability: Large V ds swings on M3 and M4 induce 0.1% PRBS-modulated thermal transients. 12

13 Chopper Transient Removal Uncorrected transient degrades SNR by 6 db. Transient removed with a poly-phase p fast FIR filter. Foreground self-calibration finds filter coefficients. Dithe er DAC Dither Chop PRBS 8 Slices Chop Filter ADC Background Calibration Engine 13

14 Output MUX Output MUX Dynamic Linearity Corrector 14 ADC Block Diagram Per-slice DSP Chop Filter Gain Radix Converter ADC Chop Offset Dither Dither DAC Dither Chop PRBS Background Calibration Engine

15 Digital Dynamic Linearity Correction Analog circuit nonlinearities include: Nonlinear settling Track switch nonlinearity Signal-modulated aperture time Error characteristics: Functions of signal history Frequency-dependent Partially correctable if we know both the sample and its derivative 15

16 Digital Dynamic Linearity Correction Slope est. filter dx/dt x x Programmable Correction Coefficients Estimate the derivative of the signal. Calculate selected 2 nd - and 3 rd -order products of the signal and its derivative. Calculate the correction as a weighted sum of the product terms. x x Product Term Multipliers ( ) (x ) 2 x 2 x (x ) ( ) 2 x 3 2 x x 2 3 Input x Out 16

17 Slope Estimation Filter Infinitely long impulse response Ideal H(f) ) H(f) = j2πf Practical 0 Fs/2 Truncated impulse response H(f) H(f) j2πf 0 Fs/2 17

18 SFD DR (db B) 95 Dynamic Linearity Corrector Performance (-1 dbfs Input) SFDR with DLC 60 SFDR without DLC Input Frequency (MHz) 18

19 INL with a 450 MHz Input Signal b LS SB) INL ( Code 19

20 Magnit tude (d dbfs) Power Spectrum -1 dbfs at 1052 MHz RBW = 2.44 MHz Without calibration or DLC With calibration and DLC HD2 HD Frequency (MHz) 20

21 (db) SFDR Performance Comparison Time-interleaved i dadcs Published ADCs (ISSCC and VLSI) This work MHz 100MHz 1GHz 10GHz 100GHz Bandwidth Source: B. Murmann, "ADC Performance Survey

22 Power Dissipation by Function Function Power (Watts) 2-Rank Track & Hold 2.5 Clock Distribution and Clock Divider ADC Slices 13.1 Digital Signal Path and DSP 2.6 Background Calibration 2.7 Output Data Ports 1.2 Total 23.9 Interleaving is expensive! 22

23 Die Photograph 7.4 mm x 14.0 mm SiGe BiCMOS 23

24 Performance Summary Sample Rate 2.5 GS/s Resolution 14 bits Signal to Noise Ratio (SNR), 0dBFS Input 61 db Noise Spectral 2.5 GS/s -152 dbfs/hz Spurious Free Dynamic Range (SFDR) DC - 1 GHz, -1 dbfs Input 78 db INL ±1.5 LSB Sampling Clock Random Jitter 70 fs RMS Metastable Error Rate (extrapolated from <10-17 over-clocking experiments) (<1 error/year) Input Impedance 50 Ω differential Outputs t LVDS Performance maintained with continuous background calibration. 24

25 Summary High performance time-interleaving: 2-rank track and hold Extensive background calibration (224 loops) Background calibrations operate continuously regardless of input signal statistics Digital dynamic linearity correction Results: Highest reported SFDR for a time-interleaved i t ADC Highest reported SFDR at 1 GHz bandwidth 25

26 Acknowledgements The authors thank the following individuals for their valuable contributions to this work: Mauro Berdondini Steven Coenen Lewis Dove Bart Gybels Jeanne Kaneyuki Pete Martinez Brad McCormack Don Pettengill Mike Rytting Jimmy Storie Gary Thomas Joseph Tran Ramesh Vema Lynne Viaggi Yunqiang Yang 26