EE247 Lecture 16. EECS 247 Lecture 16: Data Converters- DAC Design & Intro. to ADCs 2009 Page 1

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1 EE47 Lecture 6 D/A Converters (continued) Self calibration techniques Current copiers (last lecture) Dynamic element matching DAC reconstruction filter ADC Converters Sampling Sampling switch considerations Thermal noise due to switch resistance Clock jitter related non-idealities Sampling switch bandwidth limitations Switch induced distortion Sampling switch conductance dependence on input voltage Clock voltage boosters EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page Called: Current Copier EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page

2 6bit DAC (6+0) - MSB DAC uses current copier technique I/ I/ Current Divider I EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 3 Current Divider Inaccuracy due to Device Mismatch M & M mismatch results in the two output currents not being exactly equal: Id+ Id Id = did Id Id = =Δ I I d d W di d d L = dvth W + I d V GS V th L I/ I/ M M I Ideal Current Divider I/+dI d / M M I I/-dI d / Real Current Divider M& M mismatched Problem: Device mismatch could severely limit DAC accuracy Use of dynamic element matching (next few pages) EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 4

3 EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 5 Dynamic Element Matching Block Diagram Representation CLKB CLK I ` I ` CLK I ` I I ` I I I I/(+Δ ) M M I/(-Δ ) / error Δ I I EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 6

4 Dynamic Element Matching T=/f clk During Φ During Φ () I = I o +Δ () I = I o Δ ( ) ( ) I () = I o Δ () I = I o +Δ ( ) ( ) Average of I : () () I + I CLK I = ( Δ ) + ( +Δ ) Io = I o / I o / I I / error Δ Io Note: DAC frequency of operation << f clk EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 7 I o Note: For optimum current division accuracy clock frequency is divided by two for each finer division Problem: DAC frequency of operation drastically reduced f clk /4 f clk / f clk f clk f clk f clk Note: What if the same clock frequency is used? EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 8

5 Dynamic Element Matching During Φ During Φ I o /4 I o /4 I o / () () I = Io( + Δ) I = Io( Δ) () () I = I ( Δ ) I = I ( + Δ ) o o CLK I 3 I 4 I I () 3 = = I () I 4 o ( + Δ ) ( + Δ )( + Δ ) I () 3 = = I () I 4 o ( Δ ) ( Δ )( Δ ) / error Δ I 3 () I3 + I = Io = 4 Io = 4 () 3 ( + Δ )( + Δ ) + ( Δ )( Δ ) ( + Δ Δ ) CLK I / error Δ E.g. Δ = Δ = % matching error is (%) = 0.0% I o EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 9 Bipolar -bit DAC using dynamic element matching built in 976 Element matching clock frequency 00kHz INL <0.5LSB! EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 0

6 Example: Stateof-the-Art current steering DAC Segmented: 6bit unit-element 8bit binary EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page

7 Learned to build DACs Convert the incoming digital signal to analog DAC output staircase form Some applications require filtering (smoothing) of DAC output reconstruction filter DAC In the Big Picture Analog Input Analog Preprocessing A/D Conversion DSP D/A Conversion Analog Post processing Analog Output Anti-Aliasing Filter Sampling +Quantization "Bits to Staircase" Reconstruction Filter EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 3 DAC Reconstruction Filter Need for and requirements depend on application DAC Input 0.5 B f s / x 0 6 Tasks: Correct for sinc droop Remove aliases (stair-case approximation) sinc DAC Output x Normalized Frequency f/f s EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 4

8 Reconstruction Filter Options Reconstruction Filters Digital Filter DAC SC Filter CT Filter Reconstruction filter options: Continuous-time filter only CT + SC filter SC filter possible only in combination with oversampling (signal bandwidth B << f s /) Digital filter Band limits the input signal prevent aliasing Could also provide high-frequency pre-emphasis to compensate inband sinx/x amplitude droop associated with the inherent DAC S/H function EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 5 DAC Reconstruction Filter Example: Voice-Band CODEC Receive Path Receive Output f s = 8kHz f s = 8kHz f s = 8kHz f s = 8kHz GSR Reconstruction Filter & sinx/x Compensator f s = 8kHz Note: f max sig = 3.4kHz f DAC s = 8kHz sin(π f max sig x T s )/(π f max sig xt s ) = -.75 db droop due to DAC sinx/x shape Ref: D. Senderowicz et. al, A Family of Differential NMOS Analog Circuits for PCM Codec Filter Chip, IEEE Journal of Solid-State Circuits, Vol.-SC-7, No. 6, pp.04-03, Dec. 98. EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 6

9 Summary D/A Converter D/A architecture Unit element complexity proportional to B - excellent DNL Binary weighted- complexity proportional to B- poor DNL Segmented- unit element MSB(B )+ binary weighted LSB(B ) Complexity proportional (( B -) + B ) -DNL compromise between the two Static performance Component matching Dynamic performance Time constants, Glitches DAC improvement techniques Symmetrical switching rather than sequential switching Current source self calibration Dynamic element matching Depending on the application, reconstruction filter may be needed EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 7 What Next? Analog Input ADC Converters: Need to build circuits that "sample Need to build circuits for amplitude quantization Analog Preprocessing A/D Conversion DSP D/A Conversion Analog Post processing Analog Output Anti-Aliasing Filter Sampling +Quantization "Bits to Staircase" Reconstruction Filter EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 8

10 Analog-to-Digital Converters Two categories: Nyquist rate ADCs f sig max ~ 0.5xf sampling Maximum achievable signal bandwidth higher compared to oversampled type Resolution limited to max. -4bits Oversampled ADCs f sig max << 0.5xf sampling Maximum achievable signal bandwidth significantly lower compared to nyquist Maximum achievable resolution high (8 to 0bits!) EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 9 MOS Sampling Circuits EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 0

11 Ideal Sampling In an ideal world, zero resistance sampling switches would close for the briefest instant to sample a continuous voltage v IN onto the capacitor C v IN φ S C v OUT Output Dirac-like pulses with amplitude equal to V IN at the time of sampling φ T=/f S In practice not realizable! EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page Ideal Track & Hold Sampling φ v IN S C v OUT φ T=/f S V out tracks input for ½ clock cycle when switch is closed Ideally acquires exact value of V in at the instant the switch opens "Track and Hold" (T/H) (often called Sample & Hold!) EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page

12 Ideal T/H Sampling Continuous Time time T/H signal (Sampled-Data Signal) Track Hold Clock Discrete-Time Signal EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 3 Practical Sampling Issues φ v IN M C v OUT Switch induced noise due to M finite channel resistance Clock jitter Finite R sw limited bandwidth finite acquisition time R sw = f(v in ) distortion Switch charge injection & clock feedthrough EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 4

13 Sampling Circuit kt/c Noise φ 4kTRΔf v IN M C v OUT v IN R S C v OUT Switch resistance & sampling capacitor form a low-pass filter Noise associated with the switch resistance results in Total noise variance= the output (see noise analysis in Lecture ) In high resolution ADCs kt/c noise at times dominates overall minimum signal handling capability (power dissipation considerations). EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 5 Sampling Network kt/c Noise For ADCs sampling capacitor size is usually chosen based on having thermal noise smaller or equal or at times slightly larger compared to quantization noise: Assumption: Nyquist rate ADC Choose C such that thermal noise level kbt Δ C B C kbt V FS B C kbt VFS Δ is less (or equal) than Q noise For a Nyquist rate ADC :Total quantization noise power EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 6

14 Sampling Network kt/c Noise Required C min as a Function of ADC Resolution B B C kbt V FS C min (V FS = V) pf 0.8 pf 3 pf 06 pf 5,800 pf C min (V FS = 0.5V) 0.0 pf.4 pf 5 pf 84 pf,00 pf The large area required for C limit highest achievable resolution for Nyquist rate ADCs Oversampling results in reduction of required value for C (will be covered in oversampled converter lectures) EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 7 Clock Jitter So far : clock signal controls sampling instants which we assumed to be precisely equi-distant in time (period T) Real clock generator some level of variability Variability in T causes errors "Aperture Uncertainty" or "Aperture Jitter What is the effect of clock jitter on ADC performance? EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 8

15 Clock Jitter Sampling jitter adds an error voltage proportional to the product of (t J -t 0 ) and the derivative of the input signal at the sampling instant x(t) x (t 0 ) actual sampling time t J nominal (ideal) sampling time t 0 EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 9 Clock Jitter The error voltage is e = x (t 0 )(t J t 0 ) x(t) x (t 0 ) actual sampling time t J error Does jitter matter when sampling dc signals (x (t 0 )=0)? nominal sampling time t 0 EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 30

16 Effect of Clock Jitter on Sampling of a Sinusoidal Signal Sinusoidal input Amplitude: Frequency: Jitter: x( t ) = Asin f t max x ( π x ) ( π ) x x max A f x dt x'(t) = π f Acos f t x'(t ) π f A Then: e( t ) x' ( t ) d t e( t ) π f Adt x # of Bits 6 Worst case A= AFS f fs x = Δ AFS e( t ) << B+ dt << B π f s f s MHz 0 MHz 000 MHz dt << 78 ps 0.4 ps 0.07 ps EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 3 Statistical Jitter Analysis The worst case looks pretty stringent what about the average? Let s calculate the mean squared jitter error (variance) If we re sampling a sinusoidal signal x(t) = Asin(πf x t), then x (t) = πf x Acos(πf x t) E{[x (t)] } = π f x A Assume the jitter has variance E{(t J -t 0 ) } = τ EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 3

17 Statistical Jitter Analysis If x (t) and the jitter are independent E{[x (t)(t J -t 0 )] }= E{[x (t)] } E{(t J -t 0 ) } Hence, the jitter error power is E{e } = π f x A τ If the jitter is uncorrelated from sample to sample, this jitter noise is white EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 33 Statistical Jitter Analysis DR jitter A / = π f A τ x = π f τ x = 0log 0 ( πf τ ) x EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 34

18 Example: ADC Spectral Tests SFDR SDR SNR f s Ref: W. Yang et al., "A 3-V 340-mW 4-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input," IEEE J. of Solid-State Circuits, Dec. 00 EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 35 Summary Effect of Clock Jitter on ADC Performance In cases where clock signal is provided from off-chip have to choose a source with low enough jitter On-chip precautions to keep the clock jitter less than single-digit pico-second : Separate supplies as much as possible Separate analog and digital clocks Short inverter chains between clock source and destination Few, if any, other analog-to-digital conversion non-idealities have the same symptoms as sampling jitter: RMS noise proportional to input signal frequency RMS noise proportional to input signal amplitude In cases where clock jitter limits the dynamic range, it s easy to tell, but may be difficult to fix... EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 36

19 Sampling Acquisition Bandwidth The resistance R of switch S turns the sampling network into a lowpass filter with finite time constant: τ = RC v IN R φ S C v OUT Assuming V in is constant or changing slowly during the sampling period and C is initially discharged v out ( t) = v in t /τ ( e ) Need to allow enough time for the output to settle to less than ADC LSB determines minimum duration for φ or maximum clock frequency φ v invout δ v EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 37 Sampling: Effect of Switch On-Resistance tx tx t / τ V V <<Δ since V = V ( e ) in out out in Ts T τ s Ve in <<Δ orτ << V ln in Δ Worst Case: V = V in FS v IN φ R S C v OUT Ts 0.7 Ts τ << ln B B ( ) 0.7 R << fcln Bf C s B ( ) s φ t x Example: B = 4, C = 3pF, f s = 00MHz T s /τ >> 9.4, or 0τ <<T s / R << 40 Ω T=/f S EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 38

20 Switch On-Resistance Switch MOS operating in triode mode: W VDS di IDtriode ( ) = μcox VGS VTH VDS, L R dv Dtriode ( ) ON DS V 0 DS R ON = = W W μc V V C V V V L L ( ) μ ( ) ox GS th ox DD th in Let us call V =0 R then R R ON Ro = Vin V V DD in o o th = W μc V V L ( ) ox DD th VGS = V DD -V in V in φ V DD M C EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 39 Sampling Distortion Simulated 0-Bit ADC & T s / = 5τ V DD V th = V V FS = V Sampling Switch modeled: v out v in = e τ T V in VDD V th Results in HD=-4dBFS & HD3=-5.4dBFS EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 40

21 Doubling sampling time (or ½ time constant) Results in: HD improved from -4dBFS to -70dBFS ~30dB HD3 improved from - 5.4dBFS to -76.3dBFS ~5dB Sampling Distortion Allowing enough time for the sampling network settling Reduces distortion due to switch R non-linear behavior to a tolerable level 0bit ADC T s / = 0 τ V DD V th = V V FS = V EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 4 Sampling Distortion Effect of Supply Voltage 0bit ADC & T s / = 5τ V DD V th = V V FS = V Effect of higher supply voltage on sampling distortion HD3 decreased by (V DD /V DD ) HD decreased by (V DD /V DD ) 0bit ADC & T s / = 5τ V DD V th = 4V V FS = V EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 4

22 Sampling Distortion SFDR sensitive to sampling distortion - improve linearity by: Larger V DD /V FS Higher sampling bandwidth Solutions: Overdesign Larger switches Issue: Increased switch charge injection Increased nonlinear S &D junction cap. Maximize V DD /V FS Decreased dynamic range if V DD const. Complementary switch Constant & max. V GS f(v in ) 0bit ADC T s /τ = 0 V DD V th = V V FS = V EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 43 Practical Sampling Summary So Far! kt/c noise C kbt VFS B Finite R sw limited bandwidth 0.7 R << B fc s v IN φ M v OUT C g sw = f (V in ) distortion Vin W g = g for g μc V V VDD V = th L ( ) ON o o ox DD th EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 44

23 Sampling: Use of Complementary Switches φ g o g n o g o T =g on + g o p φ B g o p φ φ B Complementary n & p switch advantages: Increase in the overall conductance Linearize the switch conductance for the range V thp < Vin < Vdd - V thn EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 45 Complementary Switch Issues Supply Voltage Evolution Supply voltage has scaled down with technology scaling Threshold voltages do not scale accordingly Ref: A. Abo et al, A.5-V, 0-bit, 4.3-MS/s CMOS Pipeline Analog-to-Digital Converter, JSSC May 999, pp EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 46

24 Complementary Switch Effect of Supply Voltage Scaling g effective g o n g o T =go n + g o p φ g o p φ B φ φ B As supply voltage scales down input voltage range for constant g o shrinks Complementary switch not effective when V DD becomes comparable to xv th EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 47 Boosted & Constant V GS Sampling V GS =const. OFF ON Gate voltage V GS =low Device off Beware of signal feedthrough due to parasitic capacitors Increase gate overdrive voltage as much as possible + keep V GS constant Switch overdrive voltage independent of signal level Error due to finite R ON linear (to st order) Lower R on lower time constant EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 48

25 Constant V GS Sampling (= the switch input terminal) EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 49 Constant V GS Sampling Circuit VDD=3V P_N M M M3 M8 M6 VP 00ns P C PB C C3 M P M4 M5 M9 VS.5V MHz Va Vg M Vb Chold This Example: All device sizes:w/l=0μ/0.35μ All capacitor size: pf (except for Chold) Note: Each critical switch requires a separate clock booster Sampling switch & C Ref: A. Abo et al, A.5-V, 0-bit, 4.3-MS/s CMOS Pipeline Analog-to-Digital Converter, JSSC May 999, pp EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 50

26 VDD=0 3V M 0ff C PB 0 3V Clock Voltage Doubler C 0 0 M Saturation mode 0 3V 0 (3V-V th M ) M Triode VDD=3V M off 3V 0 3V (3V-V th M ) (6V-V th M ) Acquire charge C C PB 3V 0 0 3V P P VP =clock 0 3V VP 3V 0 a) Start up b) Next clock phase EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 5 Clock Voltage Doubler M 0ff 3V ~6V VDD=3V C PB 0 3V P VP M 0 3V 3V 0 M Triode (6V-V M th ) (3V-V M th ) ~ 3V Acquires C charge Both C & C charged to VDD after one clock cycle Note that bottom plate of C & C is either 0 or VDD while top plates are at VDD or VDD c) Next clock phase EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 5

27 Clock Voltage Doubler VDD=3V VDD M M P_Boost R R VDD C C PB P 0 VP Clock period: 00ns *R & R=GOhm dummy resistors added for simulation only EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 53 Constant V GS Sampler: Φ Low VDD=3V ~ VDD (boosted clock) M3 Triode OFF VDD C3 M4 Sampling switch M is OFF VDD M Triode Input voltage source OFF M OFF VS.5V MHz Chold pf Device OFF C3 charged to ~VDD EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 54

28 Constant V GS Sampler: Φ High M8 C3 previously charged to VDD VDD C3 pf M9 VS.5V MHz M Chold M8 & M9 are on: C3 across G-S of M M on with constant VGS = VDD EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 55 Constant V GS Sampling Input Switch V Gate Chold Signal Input Signal EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 56

29 Clock Multiplier M7 & M3 for reliability Remaining issues: -V GS constant only for V in <V out Boosted Clock Sampling Complete Circuit -Nonlinearity due to Vth dependence of Mon bodysource voltage Switch Ref: A. Abo et al, A.5-V, 0-bit, 4.3-MS/s CMOS Pipeline Analog-to-Digital Converter, JSSC May 999, pp EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 57 Boosted Clock Sampling Design Consideration Choice of value for C3: C3 too large large charging current large dynamic power dissipation VDD C3 M8 C3 too small Vgate-Vs= VDD.C3/(C3+Cx) Loss of VGS due to low ratio of Cx/C3 Cx includes M CGS and all other parasitics caps. M9 Cx Vin M Chold Ref: A. Abo et al, A.5-V, 0-bit, 4.3-MS/s CMOS Pipeline Analog-to-Digital Converter, JSSC May 999, pp EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 58

30 Advanced Clock Boosting Technique Ref: M. Waltari et al., "A self-calibrated pipeline ADC with 00MHz IFsampling frontend," ISSCC 00, Dig. Tech. Papers, pp. 34 Sampling Switch EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 59 Advanced Clock Boosting Technique clk low Sampling Switch clk low Capacitors Ca & Cb charged to VDD MS off Hold mode EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 60

31 Advanced Clock Boosting Technique clk high Sampling Switch clk high Top plate of Ca & Cb connected to gate of sampling switch Bottom plate of Ca connected to V IN Bottom plate of Cb connected to V OUT VGS & VGD of MS VDD & ac signal on G of MS average of V IN & V OUT EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 6 Advanced Clock Boosting Technique Ref: M. Waltari et al., "A self-calibrated pipeline ADC with 00MHz IFsampling frontend," ISSCC 00, Dig. Tech. Papers, pp. 34 Sampling Switch Gate tracks average of input and output, reduces effect of I R drop at high frequencies Bulk also tracks signal reduced body effect (technology used allows connecting bulk to S) Reported measured SFDR = 76.5dB at f in =00MHz EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 6

32 Constant Conductance Switch Ref: H. Pan et al., "A 3.3-V -b 50-MS/s A/D converter in 0.6um CMOS with over 80-dB SFDR," IEEE J. Solid-State Circuits, pp , Dec. 000 EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 63 Constant Conductance Switch OFF Ref: H. Pan et al., "A 3.3-V -b 50-MS/s A/D converter in 0.6um CMOS with over 80-dB SFDR," IEEE J. Solid-State Circuits, pp , Dec. 000 EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 64

33 Constant Conductance Switch M Constant current constant g ds ON M replica of M & same VGS as M M also constant g ds Note: Authors report requirement of 80MHz GBW for the opamp for bit 50Ms/s ADC Also, opamp common-mode compliance for full input range required Ref: H. Pan et al., "A 3.3-V -b 50-MS/s A/D converter in 0.6um CMOS with over 80-dB SFDR," IEEE J. Solid-State Circuits, pp , Dec. 000 EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 65 Switch Off-Mode Feedthrough Cancellation Ref: M. Waltari et al., "A self-calibrated pipeline ADC with 00MHz IF-sampling frontend," ISSCC 00, Dig. Techn. Papers, pp. 34 EECS 47 Lecture 6: Data Converters- DAC Design & Intro. to ADCs 009 Page 66