EE247 Lecture 11. Example: Switched-capacitor filters in CODEC integrated circuits. Switched-capacitor filter design summary

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1 EE47 Lecture 11 Filters (continued) Example: Switched-capacitor filters in CODEC integrated circuits Switched-capacitor filter design summary Comparison of various filter topologies New Topic: Data Converters EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 1 Summary Last Lecture Switched-capacitor filters Switched-capacitor integrators LDI integrators Effect of parasitic capacitance Bottom-plate integrator topology Resonators Bandpass filters Lowpass filters Termination implementation Transmission zero implementation Switched-capacitor filter design considerations Effect of non-idealities Switched-capacitor filters utilizing double sampling technique EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page

2 Switched-Capacitor Filter Application Example: Voice-Band CODEC (Coder-Decoder) Chip f s = 14kHz f s = 18kHz f s = 8kHz f s = 8kHz f s = 18kHz f s = 8kHz f s = 18kHz f s = 18kHz Ref: D. Senderowicz et. al, A Family of Differential NMOS Analog Circuits for PCM Codec Filter Chip, IEEE Journal of Solid-State Circuits, Vol.-SC-17, No. 6, pp , Dec EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 3 CODEC Transmit Path Lowpass Filter Frequency Response Note: f s =18kHz Magnitude (db) Frequency (Hz) EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 4

3 CODEC Transmit Path Highpass Filter Magnitude (db) Frequency (Hz) Note: f s =8kHz 1 EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 5 CODEC Transmit Path Filter Overall Frequency Response Magnitude (db) Frequency (Hz) 1 Low Q bandpass (Q<1) filter shape Implemented with lowpass followed by highpass EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 6

4 CODEC Transmit Path Clocking & Anti-Aliasing Scheme First filter (1 st order RC type) performs anti-aliasing for the next S.C. biquad The 1 st & nd stage filters form 3 rd order elliptic LPF with corner 3kHz Anti-aliasing for the next lowpass filter The stages prior to the high-pass perform anti-aliasing for highpass Notice gradual lowering of clock frequency Ease of anti-aliasing EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 7 SC Filter Summary Pole and zero frequencies proportional to Sampling frequency f s Capacitor ratios High accuracy and stability in response Long time constants realizable without requiring large value R Compatible with transconductance amplifiers Reduced circuit complexity, power dissipation Amplifier bandwidth requirements less stringent compared to CT filters (low frequencies only) Issue: Sampled-data filters require anti-aliasing prefiltering EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 8

5 Switched-Capacitor Filters versus Continuous- Time Filter Limitations Considering overall effects of: Opamp finite slew rate Opamp finite unitygain-bandwidth Magnitude Error Opamp settling issues Cont. Time Filter Clock feedthru Switch+ sampling cap. finite timeconstant 5-1MHz S.C. Filter Filter bandwidth Limited switched-capacitor filter performance frequency range EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 9 Summary Filter Performance versus Filter Topology Opamp-RC Max. Usable Bandwidth ~1MHz SNDR 6-9dB Freq. tolerance w/o tuning +-3-5% Freq. tolerance + tuning 1-5% Opamp- MOSFET-C ~ 5MHz 4-6dB +-3-5% 1-5% Opamp- MOSFET-RC ~ 5MHz 5-9dB +-3-5% 1-5% Gm-C ~ 1MHz 4-7dB +-4-6% 1-5% Switched Capacitor ~ 1MHz 4-9dB <<1% _ EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 1

6 Material Covered in EE47 Where are We? Filters Continuous-time filters Biquads & ladder type filters Opamp-RC, Opamp-MOSFET-C, gm-c filters Automatic frequency tuning Switched capacitor (SC) filters Data Converters D/A converter architectures A/D converter Nyquist rate ADC- Flash, Pipeline ADCs,. Oversampled converters Self-calibration techniques Systems utilizing analog/digital interfaces EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 11 Data Converters EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 1

7 Suggested Reference Texts R. v. d. Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, nd ed., Kluwer, 3. B. Razavi, Data Conversion System Design, IEEE Press, S. Norsworthy et al (eds), Delta-Sigma Data Converters, IEEE Press, Extensive treatment of oversampled converters including stability, tones, bandpass converters. J. G. Proakis, D. G. Manolakis, Digital Signal Processing, Prentice Hall, EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 13 Converter Applications EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 14

8 Data Converter Basics DSPs benefited from device scaling However, real world signals are still analog: Continuous time Continuous amplitude DSP can only process: Discrete time Discrete amplitude Need for data conversion from analog to digital and digital to analog Analog Input Analog Preprocessing A/D Conversion DSP D/A Conversion Analog Postprocessing Analog Output Filters? ? Filters EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 15 A/D & D/A Conversion A/D Conversion D/A Conversion EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 16

9 Data Converters Stand alone data converters Used in variety of systems Example: Analog Devices AD935 1bit/ 65Ms/s ADC- Applications: Ultrasound equipment IF sampling in wireless receivers Various hand-held measurement equipment Low cost digital oscilloscopes EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 17 Data Converters Embedded data converters Integration of data conversion interfaces along with DSPs and/or RF circuits Cost, reliability, and performance Main issues Feasibility of integrating sensitive analog functions in a technology typically optimized for digital performance Down scaling of supply voltage as a result of downscaling of feature sizes Interference & spurious signal pick-up from on-chip digital circuitry and/or high frequency RF circuits Portable applications dictate low power consumption EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 18

10 Example: Typical Cell Phone Contains in integrated form: 4 Rx filters 4 Tx filters 4 Rx ADCs 4 Tx DACs 3 Auxiliary ADCs 8 Auxiliary DACs Total: Filters 8 ADCs 7 DACs 1 Dual Standard, I/Q Audio, Tx/Rx power control, Battery charge control, display,... EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 19 D/A Converter Transfer Characteristics An ideal digital-toanalog converter: Accepts digital inputs b 1 -b n Produces either an analog output voltage or current Assumption (will be revisited) Uniform, binary digital encoding Unipolar output ranging from to V FS MSB b 1 b b 3 b n.. V FS D/A Nomenclature: N = # of bits = full scale output LSB V o or I o Δ= min. step size 1LSB VFS Δ= N VFS or N = log resolution Δ EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page

11 D/A Converter Transfer Characteristics V N = #of bits FS = full scale output Δ= min. step size 1LSB V Δ= FS N MSB b 1 b b 3 b n.. D/A LSB V V = V N FS i i= 1 N i= 1 bi N i =Δ bi, bi= or 1 ( = 1,alli) Note:D bi max Vo = VFS Δ 1 max Vo = VFS 1 N binary-weighted EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 1 D/A Converter Exampe: D/A with 3-bit Resolution Example:N = 3 Assume VFS =.8V Input code is11 1 ( ) V =Δ b + b + b 1 3 MSB LSB b 1 b b Then: Δ= V / =.1V FS 3 ( 1 ) V.1V 1 1 = + + = V =.5V Note:MSB V / & LSB V / FS FS N D/A V EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page

12 Ideal DAC introduces no error! Ideal 3-Bit D/A Transfer Characteristic V FS Analog Output Ideal Response One-to-one mapping from input to output V FS / Step Height (1LSB =Δ) V FS / Digital Input Code EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 3 A/D Converter Transfer Characteristics An ideal analog-to-digital converter: Accepts analog input in the form of either voltage or current V in MSB b 1 b b 3 b n.. A/D LSB Produces digital output either in serial or parallel form N = # of bits Assumption (will be revisited) Unipolar input ranging from to V FS Uniform, binary digital encoding V FS = full scale output Δ= min. resoluvable input 1LSB VFS Δ= N VFS or N = log resolution Δ EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 4

13 Ideal ADC introduces error with max peak-to-peak: (+-1/ Δ) Δ = V FS / N N= # of bits Ideal A/D Transfer Characteristic Digital Output This error is called ``quantization error`` 1 1 1LSB Δ Δ 3Δ 4Δ 5Δ 6Δ 7Δ Analog input V FS EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 5 Non-Linear Data Converters So far data converter characterisitics studied are with uniform, binary digital encoding For some applications to maximize dynamic range non-linear coding is used e.g. Voiceband telephony, Small signals larger # of codes Large signals smaler # of codes EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 6

14 Example: Non-Linear A/D Converter For Voice-Band Telephony Applications Non-linear ADC and DAC used in voice-band CODECs To maximize dynamic range without need for large # of bits Non-linear Coding scheme called A-law & μ-law is used Also called companding Ref: P. R. Gray, et al. "Companded pulse-code modulation voice codec using monolithic weighted capacitor arrays," IEEE Journal of Solid-State Circuits, vol. 1, pp , December Coder Output (DIGITAL) -V FS -V FS / -V FS /4 Coder Input (ANALOG) EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 7 Data Converter Performance Metrics Data Converters are typically characterized by static, time-domain, & frequency domain performance metrics : Static Monotonicity Offset Full-scale error Differential nonlinearity (DNL) Integral nonlinearity (INL) Dynamic Delay, settling time Aperture uncertainty Distortion- harmonic content Signal-to-noise ratio (SNR), Signal-to-(noise+distortion) ratio (SNDR) Idle channel noise Dynamic range & spurious-free dynamic range (SFDR) EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 8

15 Typical Sampling Process CT SD DT Continuous Time Sampled Data (e.g. T/H signal) time Physical Signals Clock Discrete Time "Memory Content" EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 9 Discrete Time Signals A sequence of numbers (or vector) with discrete index time instants Intermediate signal values not defined (not the same as equal to zero!) Mathematically convenient, non-physical We will use the term "sampled data" for related signals that occur in real, physical interface circuits EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 3

16 Uniform Sampling y(kt)=y(k) t= 1T T 3T 4T 5T 6T... k= Samples spaced T seconds in time Sampling Period T Sampling Frequency f s =1/T Problem: Multiple continuous time signals can yield exactly the same discrete time signal (aliasing) EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 31 Data Converters ADC/DACs need to sample/reconstruct to convert from continuous-time to discrete-time signals and back Purely mathematical discrete-time signals are different from "sampled-data signals" that carry information in actual circuits Question: How do we ensure that sampling/reconstruction fully preserve information? EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 3

17 Aliasing The frequencies f x and nf s ±f x, n integer, are indistinguishable in the discrete time domain Undesired frequency interaction and translation due to sampling is called aliasing If aliasing occurs, no signal processing operation downstream of the sampling process can recover the original continuous time signal! EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 33 Frequency Domain Interpretation Signal scenario before sampling Amplitude Continuous Time Signal scenario after sampling DT f in f s / f s f s.. f nf S ±f max signal fold back into band of interest Aliasing Amplitude.5 Discrete Time f/f s EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 34

18 Brick Wall Anti-Aliasing Filter Amplitude Filter Continuous Time f s f s... f Discrete Time.5 f/f s Sampling at Nyquist rate (f s =f signal ) required brick-wall anti-aliasing filters EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 35 Practical Anti-Aliasing Filter Amplitude Filter Continuous Time f s / f s f s... f Practical filter: Nonzero "transition band" In order to make this work, we need to sample faster than x the signal bandwidth "Oversampling" EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 36

19 Practical Anti-Aliasing Filter Desired Signal Parasitic Tone Continuous Time Attenuation B f s / f s -B f s... f Discrete Time B/f s.5 f/f s EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 37 Data Converter Classification f s > f max Nyquist Sampling "Nyquist Converters" Actually always slightly oversampled (e.g. CODEC f sig max =3.4kHz & ADC sampling 8kHz f s /f max =.35) Requires anti-aliasing filtering prior to A-to-D conversion f s >> f max Oversampling "Oversampled Converters" Anti-alias filtering is often trivial Oversampling is also used to reduce quantization noise, see later in the course... f s < f max Undersampling (sub-sampling) EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 38

20 Continuous Time Sub-Sampling Amplitude BP Filter f s... f Discrete Time.5 f/f s Sub-sampling sampling at a rate less than Nyquist rate aliasing For signals an intermediate frequency Not destructive! Sub-sampling can be exploited to mix a narrowband RF or IF signal down to lower frequencies EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 39 Nyquist Data Converter Topics Basic operation of data converters Uniform sampling and reconstruction Uniform amplitude quantization Characterization and testing Common ADC/DAC architectures Selected topics in converter design Practical implementations Compensation & calibration for analog circuit non-idealities Figures of merit and performance trends EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 4

21 Where Are We Now? Analog Input We now know how to preserve signal information in CT DT transition Analog Preprocessing A/D Conversion DSP Anti-Aliasing Filter Sampling (+Quantization) How do we go back from DT CT? D/A Conversion Analog Postprocessing? Analog Output EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 41 Ideal Reconstruction x(k) x(t) The DSP books tell us: k = x ( t) = x( k) g( t kt ) sin(πbt) g( t) = πbt Unfortunately not all that practical... EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 4

22 Zero-Order Hold Reconstruction Amplitude sampled data -1 after ZOH 1 3 Time [μs] How about just creating a staircase, i.e. hold each discrete time value until new information becomes available? What does this do to the frequency content of the signal? Let's analyze this in two steps... EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 43 DT CT: Infinite Zero Padding Time Domain Frequency Domain DT sequence f /f s Infinite Zero padded Interpolation: CT Signal f s 1.5f s.5f s f /f s Next step: pass the samples through a sample & hold block (ZOH) EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 44

23 Hold Pulse T p =T s Transfer Function 1 abs(h(f)) sin( Tπ f T p sin(π s ) H( f ) = ftp ) H ( f ) = π f T T s πft s p f /f s EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 45 ZOH Spectral Shaping 1 Continuous Time Pulse Train Spectrum ZOH Transfer Function ("Sinc Shaping") ZOH output, Spectrum of Staircase Approximation X(k) ZOH f / f s EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 46

24 Smoothing Filter Filter out the high frequency content associated with staircase shape of the signal Order of the filter required is a function of oversampling ratio High oversampling helps reduce filter order requirement f / f s EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 47 Summary Sampling theorem f s > f max, usually dictates anti-aliasing filter If theorem is met, CT signal can be recovered from DT without loss of information ZOH and smoothing filter reconstruct CT signal from DT vector Oversampling helps reduce order & complexity of anti-aliasing & smoothing filters EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 48

25 Next Topic Analog Input Done with "Quantization in time" Next: Quantization in amplitude Analog Preprocessing A/D Conversion DSP D/A Conversion Analog Postprocessing Anti-Aliasing Filter Sampling (+Quantization) D/A+ZOH Smoothing Filter Analog Output EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 49 Ideal ADC ("Quantizer") Accepts & analog input & generates it s digital representation Quantization step: Δ (= 1 LSB) Full-scale input range: -.5Δ ( N -.5)Δ E.g. N = 3 Bits V FS = -.5Δ to 7.5Δ Digital Output Code Ideal converter with infinite # of bits ADC characteristics V FS ADC Input Voltage [ Δ] EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 5

26 Quantization Error Quantization error Difference between analog input and output of the ADC converted to analog via an ideal DAC Called: Quantization error Residue Quantization noise V in ADC. Ideal DAC Residue - Σ ε q (V in ) + EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 51 Quantization Error For an ideal ADC: Quantization error is bounded by Δ/ +Δ/ for inputs within full-scale range V in ADC Model D + out ε q (V in ) Digital Output Code Quantization error [LSB] ideal converter with infinite bits ADC characteristics ADC Input Voltage [Δ] EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 5

27 ADC Dynamic Range Assuming quantization noise is much larger compared to circuit generated noise: D.R. Maximum Full Scale Signal Power = 1log Quantization Noise Power Crude assumption: Same peak/rms ratio for signal and quantization noise! D.R. Maximum Peak Full Scale = log Peak Quantization Noise VFS N = log = log = 6. N [ db ] Δ Question: What is the quantization noise power? EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 53 Quantization Error Let us assume V in is a ramp signal with amplitude equal to ADC full-scale V in _Ramp V FS Quantization error [LSB] Δ/ Δ/ Time Time Note: Quantization error waveform periodic and also ramp EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 54

28 Quantization Error Need to find the rms value for quantization error waveform: + T/ + Δ /k Quantization 1 Δ εeq = ( k t) dt ( k t) = dt error T k Δ k = k T/ Δ/k + Δ /k t dt Δ /k Δ/ Δ ε Δ/k eq = Independent of k 1 Δ Δ/ εeq = 1 In general above equation applies if: Input signal much larger than 1LSB Input signal busy No signal clipping ε q =k.t Δ/k Time EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 55 Quantization Error PDF Probability density function (PDF) Uniformly distributed from Δ/ +Δ/ provided that: Busy input Amplitude is many LSBs No overload Not Gaussian! Zero mean Variance +Δ / Δ / e Δ e = de= Δ 1 PDF 1/Δ Ref: W. R. Bennett, Spectra of quantized signals, Bell Syst. Tech. J., vol. 7, pp , July Δ/ +Δ/ error B. Widrow, A study of rough amplitude quantization by means of Nyquist sampling theory, IRE Trans. Circuit Theory, vol. CT-3, pp , EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 56

29 Signal-to-Quantization Noise Ratio If certain conditions the quantization error can be viewed as being "random", and is often referred to as noise In this case, we can define a peak signal-to-quantization noise ratio, SQNR, for sinusoidal inputs: N 1 Δ e.g. N SQNR 8 5 db N SQNR= = db Δ db 1 1 db = 6.N db Accurate for N>3 Real converters do not quite achieve this performance due to other sources of error: Electronic noise Deviations from the ideal quantization levels EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 57 SQNR Measurement log(sqnr) 6dB/octave SQNRpeak = 6.N db Ideal Realistic db Dynamic Range Vin [db] EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 58

30 Static Ideal Macro Models DAC D in V out V in ADC + ε q D out EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 59 Cascade of Data Converters q ADC DAC V in + ε V out D in DAC ADC + εq D out EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 6

31 Static Converter Errors Deviation of converter characteristics from ideal: Offset Full-scale error Differential nonlinearity DNL Integral nonlinearity INL EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 61 ADC Offset Error DAC Ref: Understanding Data Converters, Texas Instruments Application Report SLAA13, Mixed-Signal Products, EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 6

32 ADC Actual full-scale point Full-Scale Error Ideal full-scale point DAC Ideal full-scale point Full-scale error Full-scale error Actual full-scale point EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 63 Offset and Full-Scale Error Note: For further measurements (DNL, INL) connecting the endpoints & deriving ideal codes based on the non-ideal endpoints elliminates offset and full-scale error Digital Output Code ADC characteristics ideal converter Offset error Full-scale error ADC Input Voltage [LSB] EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 64

33 Offset and Full-Scale Errors Alternative specification in % Full-Scale = 1% * (# of LSB value)/ N Gain error can be extracted from offset & full-scale error Non-trivial to build a converter with extremely good full-scale/offset specs Typically full-scale/offset is most easily compensated by the digital pre/post-processor More critical: Linearity measures DNL, INL EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 65 ADC Differential Nonlinearity DNL = deviation of code width from Δ (1LSB) 1. Endpoints connected. Ideal characteristics derived elliminating offset & full-scale error 3. DNL measured Digital Output Code ADC Transfer Curve Real Ideal -.4 LSB DNL error LSB DNL error +.4 LSB DNL error ADC Input Voltage [Δ] EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 66

34 ADC Differential Nonlinearity Ideal ADC transitions point equally spaced by 1LSB For DNL measurement, offset and full-scale error is eliminated DNL [k] (a vector) measures the deviation of each code from its ideal width Typically, the vector for the entire code is reported If only one DNL # is reported that would be the worst case EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 67 Example Compute Offset, Full-Scale Error, & DNL A 3bit ADC is designed to have an ideal: LSB=.1V The measured transitions levels for the end product is shown in the table below, compute offset, full-scale, gain error, & DNL Transition # 1 Ideal transition point [V].5 Real transition point [V]. 1- Offset: (real transition-ideal)= -.3V, in LSB -.3/.1=-.3LSB - Full-scale error (real last transition-ideal) = =.3V in LSB.3/.1=+.3LSB LSB after correcting for offset & full-scale error: LSB=(Last transition-first transition)/( N -) LSB=(.68-.)/6=.11V EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 68

35 ADC Differential Nonlinearity Example V FS = N..11V=.88V 4-Gain relative to ideal Gain=.8/.88=.9 Code # Code Width [V] - Width [LSB] - DNL [LSB] Find all code widths Width[k]=Transition[k+1]- Transition[k] -Divide code width by LSB W[k] Find DNL: DNL[k]=W[k]-LSB EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 69 ADC Differential Nonlinearity Example DNL [LSB] 1.5 Max. DNL 1 3 Code # DNL [LSB] Code # 7 - EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 7

36 ADC Differential Nonlinearity Examples 8 ADC characteristics ideal converter 8 ADC characteristics ideal converter 7 7 Digital Output Code Missing code (+.5/-1 LSB DNL) Digital Output Code Non-monotonic (> 1 LSB DNL) ADC Input Voltage [Δ] ADC Input Voltage [Δ] EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 71 ADC DNL DNL=-1 implies missing code For an ADC DNL < -1 not possible undefined Can show: all i DNL[i] = For a DAC DNL < -1 possible EECS 47 Lecture 11: S.C. Filter Example/ Introduction to Data Converters 7 H. K. Page 7

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