Data Converter Topics. Suggested Reference Texts

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1 Data Converter Topics Basic Operation of Data Converters Uniform sampling and reconstruction Uniform amplitude quantization Characterization and Testing Common ADC/DAC Architectures Selected Topics in Converter Design Practical Implementations Desensitization to Analog Circuit Non-Idealities Figures of Merit and Performance Trends EECS 247 Lecture 2: Data Converters 25 H. K. Page 7 Suggested Reference Texts R. v. d. Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 2nd ed., Kluwer, 23. B. Razavi, Data Conversion System Design, IEEE Press, 995. S. Norsworthy et al (eds), Delta-Sigma Data Converters, IEEE Press, 997. Extensive treatment of oversampled converters including stability, tones, bandpass converters. J. G. Proakis, D. G. Manolakis, Digital Signal Processing, Prentice Hall, 995. EECS 247 Lecture 2: Data Converters 25 H. K. Page 8

2 Data Converter Basics Analog Input DSP is wonderful, but... Real world signals are analog: Continuous time Continuous amplitude DSP can only process: Discrete time Discrete amplitude Need for data conversion from analog to digital and digital to analog Analog Preprocessing A/D Conversion DSP D/A Conversion Analog Postprocessing Analog Output Filters?...? Filters EECS 247 Lecture 2: Data Converters 25 H. K. Page A/D & D/A Conversion A/D Conversion D/A Conversion EECS 247 Lecture 2: Data Converters 25 H. K. Page 2

3 Data Converter Performance Metrics Data Converters are typically characterized by static, time-domain, & frequency domain performance metrics : Static Monotonicity Offset Full-scale error Differential nonlinearity (DNL) Integral nonlinearity (INL) Dynamic Delay, settling time Aperture uncertainty Distortion- harmonic content Signal-to-noise ratio (SNR), Signal-to-(noise+distortion) ratio (SNDR) Idle channel noise Dynamic range & spurious-free dynamic range (SFDR) EECS 247 Lecture 2: Data Converters 25 H. K. Page 9 What is a discrete time signal? A signal that changes only at discrete time instances? A continous time signal multiplied with a train of infinitely narrow unit pulses? A vector whose element indices correspond to discrete instances in time? All of the above? [ ] time EECS 247 Lecture 2: Data Converters 25 H. K. Page 2

4 Discrete Time Signals A sequence of numbers (or vector) with discrete index time instants Intermediate signal values not defined (not the same as equal to zero!) Mathematically convenient, non-physical We will use the term "sampled data" for related signals that occur in real, physical interface circuits EECS 247 Lecture 2: Data Converters 25 H. K. Page 2 Typical Sampling Process CT SD DT Continuous Time Sampled Data (e.g. T/H signal) time Physical Signals Clock Discrete Time "Memory Content" EECS 247 Lecture 2: Data Converters 25 H. K. Page 22

5 Aliasing The frequencies f x and Nf s ± f x, N integer, are indistinguishable in the discrete time domain Undesired frequency interaction and translation due to sampling is called aliasing If aliasing occurs, no signal processing operation downstream of the sampling process can recover the original continuous time signal! Let's look at this in the frequency domain... EECS 247 Lecture 2: Data Converters 25 H. K. Page 25 Sampling Sine Waves Voltage Time domain f s = /T y(nt) time Frequency domain Amplitude f in f s - f in f s f s + f in 2f f s EECS 247 Lecture 2: Data Converters 25 H. K. Page 26

6 Frequency Domain Interpretation Signal scenario before sampling Amplitude Continuous Time Signal scenario after sampling DT f in f s /2 f s 2f s.. f nf S ± f max signal fold back into band of interest Aliasing Amplitude.5 Discrete Time f/f s EECS 247 Lecture 2: Data Converters 25 H. K. Page 27 Brick Wall Anti-Aliasing Filter Amplitude Filter Continuous Time f s 2f s... f Discrete Time.5 f/f s Sampling at Nyquist rate (f s =2f signal ) required brick-wall anti-aliasing filters EECS 247 Lecture 2: Data Converters 25 H. K. Page 28

7 How to Avoid Aliasing Must obey sampling theorem: f max_signal < f s /2 Two possibilities:. Sample fast enough to cover all spectral components, including "parasitic" ones outside band of interest 2. Limit f max_signal through filtering EECS 247 Lecture 2: Data Converters 25 H. K. Page 29 How to Avoid Aliasing - Push sampling frequency to x2 of the highest freq. Oversampled converters almost! Amplitude f in 2f s_old Frequency domain f s_new f s_old.. f 2- Pre-filter signal to eliminate signals above /2 sampling frequency- then sample Amplitude f in f s /2 f s Frequency domain 2f s f EECS 247 Lecture 2: Data Converters 25 H. K. Page 3

8 Practical Anti-Aliasing Filter Amplitude Filter Continuous Time f s /2 f s 2f s... f Practical filter: Nonzero "transition band" In order to make this work, we need to sample faster than 2x the signal bandwidth "Oversampling" EECS 247 Lecture 2: Data Converters 25 H. K. Page 3 Practical Anti-Aliasing Filter Desired Signal Parasitic Tone Continuous Time Attenuation B f s /2 f s -B f s... f Discrete Time B/f s.5 f/f s EECS 247 Lecture 2: Data Converters 25 H. K. Page 32

9 Data Converter Classification f s > 2f max Nyquist Sampling "Nyquist Converters" Actually always slightly oversampled f s >> 2f max Oversampling "Oversampled Converters" Anti alias filtering is often trivial Oversampling is also used to reduce quantization noise, see later in the course... f s < 2f max Undersampling (sub-sampling) EECS 247 Lecture 2: Data Converters 25 H. K. Page 33 Continuous Time Sub-Sampling Amplitude BP Filter f s... f Discrete Time.5 f/f s Sub-sampling sampling at a rate less than Nyquist rate aliasing For signals an intermediate frequency Not destructive! Sub-sampling can be exploited to mix a narrowband RF or IF signal down to lower frequencies EECS 247 Lecture 2: Data Converters 25 H. K. Page 34

10 Where Are We Now? Analog Input We now know how to preserve signal information in CT DT transition How do we go back from DT CT? Analog Preprocessing A/D Conversion DSP D/A Conversion Analog Postprocessing Analog Output Anti-Aliasing Filter Sampling (+Quantization)...? EECS 247 Lecture 2: Data Converters 25 H. K. Page 35 Ideal Reconstruction x(k) x(t) The DSP books tell us: k= x ( t) = x( k) g( t kt ) sin(2πbt) g( t) = 2πBt Unfortunately not all that practical... EECS 247 Lecture 2: Data Converters 25 H. K. Page 36

11 Amplitude Zero-Order Hold Reconstruction sampled data after ZOH Time x -5 How about just creating a staircase, i.e. hold each discrete time value until new information becomes available What does this do the frequency content of the signal? Let's analyze this in two steps... EECS 247 Lecture 2: Data Converters 25 H. K. Page 37 ) DT CT: Infinite Zero Padding Time Domain Frequency Domain DT sequence f/f s Zero padded DT sequence /i.5/i 2.5/i f/f s Infinite Interpolation: CT Signal! f s.5f s 2.5f s f EECS 247 Lecture 2: Data Converters 25 H. K. Page 38

12 2) Effect of Hold Pulse T p Ts Using the Fourier transform of a rectangular impulse we get: T H ( f ) = T p s sin(π ft ) πft p p EECS 247 Lecture 2: Data Converters 25 H. K. Page 39 Hold Pulse T p =T s T H ( f ) = T p s sin(π ft ) πft p p abs(h(f)) f/fs EECS 247 Lecture 2: Data Converters 25 H. K. Page 4

13 Hold Pulse T p =.5T s T H ( f ) = T p s sin(π ft ) πft p p abs(h(f)) f/fs EECS 247 Lecture 2: Data Converters 25 H. K. Page 4 ZOH Spectral Distortion Continuous Time Pulse Train Spectrum ZOH Transfer Function ("Sinc Distortion") ZOH output, Spectrum of Staircase Approximation X(k) ZOH f/f s EECS 247 Lecture 2: Data Converters 25 H. K. Page 42

14 Smoothing Filter f/f s Again: A brick wall filter would be nice Oversampling helps to reduce filter order EECS 247 Lecture 2: Data Converters 25 H. K. Page 43 Summary Sampling theorem f s > 2f max, usually dictates anti-aliasing filter If theorem is met, CT signal can be recovered from DT without loss of information ZOH and smoothing filter reconstruct CT from DT signal Oversampling helps reduce order & complexity of anti-aliasing & smoothing filters EECS 247 Lecture 2: Data Converters 25 H. K. Page 44

15 Next Topic Analog Input Done with "Quantization in time" Next: Quantization in amplitude Analog Preprocessing A/D Conversion DSP D/A Conversion Analog Postprocessing Anti-Aliasing Filter Sampling (+Quantization)... D/A+ZOH Smoothing Filter Analog Output EECS 247 Lecture 2: Data Converters 25 H. K. Page 45 Amplitude Quantization Amplitude quantization quantization noise Static ADC/DAC performance measures Offset Gain INL DNL EECS 247 Lecture 2: Data Converters 25 H. K. Page 46

16 Ideal ADC ("Quantizer") Quantization step (= LSB) E.g. N = 3 Bits Full-scale input range: -.5 (2 N -.5) Digital Output Code ADC characteristics ideal converter A/D Characteristics [] Quantization error: bounded by /2 + /2 for inputs within full-scale range V in ADC Model D + out ε q (V in ) Quantization error [LSB] ADC Input Voltage [/ ] EECS 247 Lecture 2: Data Converters 25 H. K. Page 47 Quantization Error PDF Uniformly distributed from /2 + /2 provided that Busy input Amplitude is many LSBs No overload Not Gaussian! Pdf /D Zero mean Variance + /2 / e e = de= 2 Spectral density white if the joint pdf of the input at different sample times is smooth Ref: W. R. Bennett, Spectra of quantized signals, Bell Syst. Tech. J., vol. 27, pp , July D/2 +D/2 error B. Widrow, A study of rough amplitude quantization by means of Nyquist sampling theory, IRE Trans. Circuit Theory, vol. CT-3, pp , 956. EECS 247 Lecture 2: Data Converters 25 H. K. Page 48

17 Signal-to-Quantization Noise Ratio If certain conditions are met (!) the quantization error can be viewed as being "random", and is often referred to as noise In this case, we can define a peak signal-to-quantization noise ratio, SQNR, for sinusoidal inputs: N N SQNR= = = 6.2N +.76 db Accurate for N>3 e.g. N SQNR 8 5 db 2 74 db 6 98 db 2 22 db Actual converters do not quite achieve this performance due to other errors, including Electronic noise Deviations from the ideal quantization levels EECS 247 Lecture 2: Data Converters 25 H. K. Page 49 Static, Ideal Macro Models ADC V in + ε q D out D in DAC V out EECS 247 Lecture 2: Data Converters 25 H. K. Page 5

18 Cascade of Data Converters q ADC DAC V in + ε V out D in DAC ADC + εq D out EECS 247 Lecture 2: Data Converters 25 H. K. Page 5 Static Converter Errors Deviations of characteristic from ideal Offset Full scale error Differential nonlinearity, DNL Integral nonlinearity, INL EECS 247 Lecture 2: Data Converters 25 H. K. Page 52

19 Offset Error ADC DAC Ref: Understanding Data Converters, Texas Instruments Application Report SLAA3, Mixed-Signal Products, 995. EECS 247 Lecture 2: Data Converters 25 H. K. Page 53 ADC Actual full scale point Full Scale Error Ideal full scale point DAC Ideal full scale point Full scale error Full scale error Actual full scale point EECS 247 Lecture 2: Data Converters 25 H. K. Page 54

20 Offset and Full Scale Errors Alternative specification in % Full Scale = % * (LSB value)/ 2 N Gain error can be extracted from offset & full scale error Non-trivial to build a converter with extremely good gain/offset specs Typically gain/offset is most easily compensated by the digital pre/post-processor More interesting: Linearity DNL, INL EECS 247 Lecture 2: Data Converters 25 H. K. Page 55 Offset and Full-Scale Error Note: For further measurements (DNL, INL) connecting the endpoints & deriving ideal codes based on the non-ideal endpoints elliminates offset and fullscale error Digital Output Code ADC characteristics ideal converter Offset error ADC Input Voltage [LSB] Full-scale error EECS 247 Lecture 2: Data Converters 25 H. K. Page 56

21 ADC Differential Nonlinearity DNL = deviation of code width from (LSB) ADC characteristics ideal converter -.4 LSB DNL error Endpoints connected Ideal characterisctics derived DNL measured Digital Output Code LSB DNL error +.4 LSB DNL error ADC Input Voltage [D] EECS 247 Lecture 2: Data Converters 25 H. K. Page 57 ADC Differential Nonlinearity Examples 8 ADC characteristics ideal converter 8 ADC characteristics ideal converter 7 7 Digital Output Code Missing code (+.5/- LSB DNL) Digital Output Code Non-monotonic (> LSB DNL) ADC Input Voltage [D] ADC Input Voltage [D] EECS 247 Lecture 2: Data Converters 25 H. K. Page 58

22 DAC Differential Nonlinearity EECS 247 Lecture 2: Data Converters 25 H. K. Page 59 Impact of DNL on Performance Same as a somewhat larger quantization error, consequently degrades SQNR How much later in the course... People sometimes speak of "DNL noise", i.e. "additional quantization noise due to DNL" EECS 247 Lecture 2: Data Converters 25 H. K. Page 6

23 ADC Integral Nonlinearity INL = deviation of code transition from its ideal location A straight line through the endpoints is usually used as reference, i.e. offset and full scale errors are ignored in INL calculation Ideal converter steps is found for the endpoint line, then INL is measured Digital Output Code LSB INL Note that INL errors can be much larger than DNL errors and vice-versa ADC Input Voltage [D] EECS 247 Lecture 2: Data Converters 25 H. K. Page 6 DAC Integral Nonlinearity EECS 247 Lecture 2: Data Converters 25 H. K. Page 62

24 DAC DNL and INL * Ref: Understanding Data Converters, Texas Instruments Application Report SLAA3, Mixed-Signal Products, 995. EECS 247 Lecture 2: Data Converters 25 H. K. Page 63 Example: INL & DNL Large INL & Small DNL Large DNL & Small INL EECS 247 Lecture 2: Data Converters 25 H. K. Page 64

25 Monotonicity Monotonicity guaranteed if INL =.5 LSB The best fit straight line is taken as the reference for determining the INL. This implies DNL = LSB Note: these conditions are sufficient but not necessary for monotonicity EECS 247 Lecture 2: Data Converters 25 H. K. Page 65

26 How to measure DNL/INL? DAC: Apply codes and use a good voltmeter to measure output ADC Not as simple as DAC need to find "decision levels", i.e. input voltages at all code boundaries One way: Adjust voltage source to find exact code trip points "code boundary servo" More versatile: Histogram testing Apply a signal with known distibution and analyze digital code distribution at ADC output EECS 247 Lecture 3: Data Converters 25 H.K. Page Code Boundary Servo Input Digital Code A Digital Comp. B A<B A B i C R 2 ADC Input V REF f S ADC Under Test C 2 i 2 ADC Output EECS 247 Lecture 3: Data Converters 25 H.K. Page 2

27 Code Boundary Servo i and i2 are small, and C is large, so the ADC analog input moves a small fraction of an LSB each sampling period For a code input of, the ADC analog input settles to the code boundary shown ADC Digital Output D 2D 3D 4D 5D 6D 7D ADC Analog Input EECS 247 Lecture 3: Data Converters 25 H.K. Page 3 Code Boundary Servo Input Digital Code A A<B i C Good DVM V REF f S Digital Comp. B A B i 2 R 2 C 2 ADC ADC Output EECS 247 Lecture 3: Data Converters 25 H.K. Page 4

28 Code Boundary Servo A very good digital voltmeter (DVM) measures the analog input voltage corresponding to the desired code boundary DVMs have some interesting properties They can have very high resolutions (8½ decimal digit meters are inexpensive) To achieve stable readings, DVMs average voltage measurements over multiple 6Hz ac line cycles to filter out pickup in the measurement loop EECS 247 Lecture 3: Data Converters 25 H.K. Page 5 Code Boundary Servo ADCs of all kinds are notorious for kicking back high-frequency, signal-dependent glitches to their analog inputs R 2 Good DVM V REF f S ADC A magnified view of an analog input glitch follows C 2 EECS 247 Lecture 3: Data Converters 25 H.K. Page 6

29 Code Boundary Servo A large C 2 fixes this Good DVM At the expense of longer measurement time V REF f S R 2 ADC C 2 EECS 247 Lecture 3: Data Converters 25 H.K. Page 9 Histogram Testing Code boundary measurements are slow Long testing time May miss dynamic errors Histogram testing Quantize input with known pdf (e.g. ramp or sinusoid) Measure output pdf Derive INL and DNL from deviation of measured pdf from expected result EECS 247 Lecture 3: Data Converters 25 H.K. Page 2

30 Histogram Test Setup V REF Ramp V REF ADC PC Time Slow (wrt conversion time) linear ramp applied to ADC DNL derived directly from total number of occurrences of each the output of the ADC EECS 247 Lecture 3: Data Converters 25 H.K. Page 2 A/D Histogram Test Using Ramp Signal Example: Ramp slope: µv/µsec LSB =mv Each ADC code msec f s =khz T s =µsec n = samples/code Digital Output ADC Input/Output Analog input n/f s Ramp Time EECS 247 Lecture 3: Data Converters 25 H.K. Page 22

31 Ramp Histogram Example: Ideal 3-Bit ADC Digital Output Code ADC characteristics ideal converter Code Count ADC Input Voltage [D] ADC output code EECS 247 Lecture 3: Data Converters 25 H.K. Page 25 Ramp Histogram Example: 3-Bit ADC with Error 7 ADC characteristics ideal converter 2 8 Digital Output Code LSB DNL +.4 LSB INL Code Count LSB DNL ADC Input Voltage [D] ADC output code EECS 247 Lecture 3: Data Converters 25 H.K. Page 26

32 Example: 3 Bit ADC DNL Extracted from Histogram - Over-range bins removed ( and full-scale) 2- Compute average count/bin ( in this case) Code Count, End bins removed ADC output code EECS 247 Lecture 3: Data Converters 25 H.K. Page 27 Example: 3 Bit ADC DNL Extracted from Histogram.4 Normalize: 3- Divide by average count/bin (ideal bins have exactly the average count, which, after normalization, is ) Normalized Code Count ADC output code EECS 247 Lecture 3: Data Converters 25 H.K. Page 28

33 A/D Histogram Test Using Sinusoidal Signals At sinusoid midpoint crossings: dv/dt max. least # of samples At sinusoid amplitude peaks: dv/dt min. highest # of samples Digital Output Time ADC Input/Output Analog input Sinusoid # of Samples Per code EECS 247 Lecture 3: Data Converters 25 H.K. Page 33 Resulting DNL and INL DNL = +.3 / - LSB, missing code if (DNL<-.9) DNL [LSB] code 2 INL = +.7 / -.69 LSB INL [LSB] code EECS 247 Lecture 3: Data Converters 25 H.K. Page 34

34 Direct ADC-DAC Test Device Under Test (DUT) Signal Generator V in V out Spectrum ADC DAC Analyzer Clock Generator Need DAC with much better performance compared to ADC under test Actually a good way to "get started"... EECS 247 Lecture 3: Data Converters 25 H.K. Page 4 DFT Test Device Under Test (DUT) Signal Generator V in ADC Data Acquisition System PC Clock Generator EECS 247 Lecture 3: Data Converters 25 H.K. Page 42

35 ADC Output Spectrum Signal amplitude: Bin: N * fx/fs + (Matlab arrays start at ) A = dbfs Ampliutde [dbfs] N=248 SNR? f/fs EECS 247 Lecture 3: Data Converters 25 H.K. Page 6 ADC Output Spectrum Noise bins: all except signal bin bx = N*fx/fs + ; As = 2*log(s(bx)) s(bx) = ; An = *log(sum(s.^2)) SNR = As - An Ampliutde [dbfs] N=248 SNR = 62dB ( bits) Computed SQNR = 6.2xN+.76dB f/fs EECS 247 Lecture 3: Data Converters 25 H.K. Page 62

36 Spectral Performance Metrics Signal S DC Distortion D Noise N Signal-to-noise ratio SNR = S / N Signal-to-distortion ratio SDR = S / D Signal-to-noise+distortion ratio SNDR = S / (N+D) Spurious-free dynamic range SFDR EECS 247 Lecture 3: Data Converters 25 H.K. Page 65 Harmonic Components At multiples of f x Aliasing: f signal = f x =.8 f s f 2 = 2 f =.36 f s f 3 = 3 f =.54 f s.46 f s f 4 = 4 f =.72 f s.28 f s f 5 = 5 f =.9 f s. f s f 6 = 6 f =.8 f s.8 f s EECS 247 Lecture 3: Data Converters 25 H.K. Page 66

37 Spectrum versus INL, DNL DNL [in LSB] DNL and INL of Bit converter (from converter decision thresholds) avg=.53, std.dev=.48, range=.9 Good DNL and poor INL bin suggests distortion problem avg=.2, std.dev=.75, range=2. INL [in LSB] bin EECS 247 Lecture 3: Data Converters 25 H.K. Page 67 Relationship INL-SFDR/SNDR Depends on "shape" of INL Rule of Thumb: SFDR 2log(2 B /INL) E.g. LSB INL, b SFDR 6dB Beware, this is of course only true under the same conditions at which the INL was taken, i.e. typically low input frequency EECS 247 Lecture 3: Data Converters 25 H.K. Page 68

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