UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences

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1 UNIVERSITY OF AIFORNIA ollege of Engineering Department of Electrical Engineering and omputer Sciences Homework 6 Solution EES 47 H. Khorramabadi Due Tues. November 3, 00 FA 00. A basic NMOS track and hold circuit is shown below. The clock applied to the gate of the transistor swings from V SS =0V to V DD =.5V. Assume an ideal square law model for the transistor with V TH =0.V and µ ox =50µA/V. Ignore body effect. a) Suppose this circuit precedes a 4bit AD. How large should we choose so that the input referred rms noise from the sampler is equal to 0.5SB of the AD at T = 7? ompared to the case where only quantization noise is present, how much is the overall SNR degraded by the inputreferred kt/ noise. b) If the clock has a 50% duty cycle, calculate the maximum clock frequency at which inputs between 0.0put can be sampled to within /8 SB accuracy at 4 bit resolution. Assume =5pF. You can use the average resistance for M. c) In practice, what are the other factors affecting the accuracy of this sampling frontend? Rs=50 W/=40/0. M V 0 Solution: a) For KT/ noise to be /4SB & VFS=V and considering B=4bit: B x4 VFS KT KT B 0. 5 xv 0 5 FS KT / pf. x oss of SNR can be computed as: SNR SQNR 0log. 43dB 0. 5 b) During the track mode, is charged with the time constant R, thus: V (t ) V e out in t R To compute the error associated with the not fully settled output at the end of track ½ clock cycle: V V V e in / in Ts R

2 In this case, the total resistance consists of the source Rs and equivalent switch resistance. In the lectures, switch resistance was found as: R 5.3 W ox VDD Vth V V 0 Rsw with R0 Vin Then: Rsw 367MHz fs DD th Rsw Rsw Rsw Ve average Vin0 VinV in fs Rs Rsw ) 367MHz fs Rs Rsw ) fs xe e Since it is required that / 8SB: e 4 8x 367MHz f s 3. MHz 7 ln ) In practice other factors affecting the accuracy of the sampling process includes switch charge injection and clock feedthrough.. onsider a 6bit flash AD with an ideal reference resistor string and =V. Assume that the comparators have an offset voltage with standard deviation OS =3mV. What are the standard deviations of the converter s worst case DN and IN? Assuming that the DA generates ideal level values, the uncertainty for each decision threshold is only due to comparator offset. In particular, each decision level is affected by the offset associated with only the comparator connected to the corresponding tap and is independent of the offset due to the rest of the comparators. Since IN is the deviation of the transition from its ideal position measured in terms of SB: V IN Then : IN actual V ideal OS OS 3mV 0. 9SB VFS V B 6 DN is defined as the deviation of the width of each code from SB: V V DN actual actual i i

3 Assuming the offset associated with two consecutive comparator is uncorrelated then: OS OS 3 x mv DN 0. 7SB VFS V 6 6 Note that DN is worse than IN in this case. 3. Shown below is the block diagram of a pipelined AD. Note that the input voltage is centered around ground level. Beff B bits B bits... Beff The first stage has the following block diagram: x 0 D0 A T H MUX V res D0 MUX output 0 Vref Vref The rest of the stages have the block diagram shown bellow: 3

4 x V res, 3, / / D D0 A T H MUX 0 D, D0 MUX output a) What is the effective number of bits for stage and the following stages? What is the raw number of bits for each stage? b) How many stages are needed to implement a bit AD? c) If each stage takes one clock cycle per conversion, what is the minimum signal latency from the analog input to the digital output? d) Derive the residue plot for the first and the following stages. e) What is the maximum tolerable comparator offset in the st stage (assume all other stages are ideal)? Show your derivation on the residue plot/s. f) What is the maximum tolerable comparator offset in the nd stage (assume all other stages are ideal)? Show your derivation on the residue plot/s. a Bonus extra credit section: g) Simulate a 3stage version of this AD first assuming no comparator offset. Derive the transfer curve and DN/IN. Second, apply ½ offset you found in part f) and prove no missing codes. Third, apply enough comparator offset to have missing codes. Solution: a) Effective # of bits is log ()=bit and the raw is log ()=bit for stage. For the other stages effective log ()=bit and raw is log ()=.58bit. b) No of stages needed are. c) atency is clock cycles. Depending on the architecture the minimum would be ½ clock cycle per stage or 6 clock cycles. d) 4

5 V res V res Stage Stage,3,. e&f) as shown in the figure: The nd stage can correct for Vref/4 offset associated with the st stage. The 3 rd stage can correct for the same amount of offset in the nd stage comparator. Note that if the criteria are for no missing code in the overall transfer curve then peak to peak residue of SB can be considered which translates to maximum allowable offset of Vref/ for single errors. /4 V Res /4 V i n Stage V Res Stage V Res3 3 Stage 3 5