CHAPTER 5 DESIGN OF TRACK-AND-HOLD AMPLIFIER AND MULITIPLYING DIGITAL TO ANALOG CONVERTER

Transcription

1 67 HAPTER 5 DESIGN OF TRAKANDHOLD AMPLIFIER AND MULITIPLYING DIGITAL TO ANALOG ONVERTER 5. INTRODUTION This chapter presents the design of the trackandhold and multiplying digitaltoanalog converter functional blocks. They are realized by Switched apacitors (S) circuits. Typical S circuit stage consists of sampling capacitors and Metal Oxide Semiconductor (MOS) switches which turn on and off at the clock rate to store the input signal (charge) on the sampling capacitors and subsequently transfer that charge to the next stage. As the MOS switches are turned on and off, charge is injected from the gate to the drain and the source of these switches. The turnon resistance of a MOS switch is input signal dependent and creates nonlinear distortion. The charge injection and signal dependent onresistance of the MOS switches introduce nonlinearity errors in the switched capacitor circuits. apacitor mismatch is another error source that significantly affects AD performance. A detailed investigation on circuit nonidealities degrading the performance of the switched capacitor AD is carried out. Exploration of the circuit techniques for reducing the nonlinearities is addressed in this chapter. 5. TRAKANDHOLD AMPLIFIER IRUIT Sampleandhold circuit grabs the signal in certain instances and hold the value at the next set of time period for doing conversion process. Actually ideal Dirac sampling is impractical since, it requires a switch, to switch on and off in infinitely small in time (in the order of pico second (ps)),

2 68 analog circuit to process the information in that period and a clock to switch ON ( =HIGH) and OFF ( = LOW) for such a high speed is practically impossible (Kok hin hang 99). The practical solution is TrackandHold (T/H) circuit. Instead of grabbing the signal in the instances, the circuit operates in two modes. In one of the two modes, it tracks the signal and in the other mode, it holds the signal (Waltari and Halonen 00). Normally, in literature, trackandhold circuit is known as sampleandhold circuit. The process of analogtodigital conversion is shown in Figure 5.. The continuous time signal is shown in Figure 5.(a). At certain time instant, it tracks the continuous time signal of the input and then during other time slots, it holds at the constant value that ideally corresponds to the last value of the track instant is as shown in Figure 5.(b). Hence the output of the T/H circuit is called as sampled data signal. During the hold phase, the ADS quantizes the sampled data signal and gives the binary numbers equivalent to the sampled data signal as shown in Figure 5.(d). (a) (b) (c) (d) (a) ontinuous time signal (b) Signal is tracked by trackandhold circuit (c) lock signal (d) Binary equivalent of sampled data signal Figure 5. Process of analogtodigital conversion

3 69 In practice, a T/H circuit can be realized by a switch in the form of transistor and capacitor as shown in Figure 5.. During the track phase, the switch is closed and the capacitor tracks the input signal with certain R time constant. In the next clock phase, the switch is opened and the capacitor holds the latest value. t V OUT Track Hold t Ideal V OUT t H t Practical V OUT Ideal Practical t H t Figure 5. Practical trackandhold circuit Normally the hold signal contains signal with distortion due to circuit nonidealities. The nonidealities are classified by their associates, they are The error associated with R time constant Finite acquisition time and thermal noise The error associated with clock signal Sampling time uncertainty

4 70 The error associated with sampling mode Voltage dependent of switch, track mode nonlinearity and signal dependent sampling instant The error associated with transition from sampling mode to hold mode Pedestal error and charge injection error The error associated with hold mode Hold mode feedthrough and droop The above nonidealities of the circuit can be compensated by the combination of the following methods: (i) (ii) (iii) MOS switches are replaced for NMOS switches Bootstrap (lock boosting) switches are used in the signal path Fully differential bottom plate sampling 5.. Finite Acquisition Time In an ideal sampler, the signal is tracked instantaneously, but in a practical trackandhold circuit, the signal is tracked with finite speed due to R time constant. The finite acquisition time (t acq ) is the time required for the THA output to experience the full scale transition and settle within the specified error band around its final value (Razavi 995). lock frequency is shown in Figure 5.3(a) and simple T/H circuit is shown in Figure 5.3(b).

5 7 mts Ts= f S Figure 5.3(a) lock frequency R V OUT Figure 5.3(b) Simple trackandhold circuit The maximum signal transition occurs when the signal tracking instant is from zero signal value to V FS. alculate τ such that V OUT settles within mts period and LSB quantization error. Normally m = 0.5 (assume track and hold phase for equal time intervals). Assuming the step voltage applied as input, the step value is equal to the full scale conversion range. The voltage stored across the capacitor is OUT FS t/τ V (t) = V (e ) (5.) V (t) = V V e OUT FS FS t/τ t/τ VFS e = VFS V OUT (t) (Quantization error) where t is the time period to settle (t = mts) and τ is the R time constant.

6 7 Quantization error must be less than LSB Minimum signal can be resolved by AD is From this Equation, V FS can be expressed as Hence the quantization error is V Δ = (5.) BAD Δ FS BAD mts BAD τ Δ e < Δ (5.3) Taking natural logarithm on both sides of Equation (5.3) gives the number of settling time constant M. M = mts B AD > ln τ 0.5 (5.4) Table 5. shows the relation between AD resolution and the settling time constant based on the Equation (5.4). Table 5. Relation between AD resolution and the settling time constant Resolution of the AD (B AD ) Minimum required time constant (M)

7 Thermal Noise Any sampling circuit can be considered as consisting of at least a switch and a capacitor. The switch always has some finite onresistance which generates thermal noise as shown in Figure 5.4. The power spectral density of this noise is the wellknown 4kTR (V /Hz), where k is the Boltzmann s constant ( ), T is the absolute temperature in Kelvin and R is the resistance. The noise in the voltage sample is the resistor noise filtered by the lowpass circuit formed by the sampling capacitor and the switch onresistance. Integrating the resistor noise spectral density weighted by the lowpass transfer function yields the mean square noise voltage on the capacitor (Johns and Martin 004, Schreier et al 005). Vn = 4kTR Δf Figure 5.4 Simple thermal noise generator circuit 0 Vo total = 4KTR df (5.5) jπr 4kTR kt Vo total = πr arctan(πf R) = 0 πr (5.6) AD. Normally, thermal noise is equated to the quantization noise of the

8 74 kt = and hence = kt V B AD FS (5.7) The minimum value of sampling capacitance MIN and maximum value of switch onresistance R MAX for various B AD can be found from Equations (5.4) and (5.7). For V FS = V, m = 0.5 and f S = 00MHz; MIN and R MAX for various B AD are listed in Table 5.. Table 5. Relationship between B AD, MIN and R MAX Resolution of the AD (B AD ) MIN R MAX fF 9,84,640 Ω ff 50,38 Ω 08.5fF 66 Ω pF 44 Ω pF 8 Ω pF 0.45 Ω 5..3 Sampling Time Uncertainty lock jitter may cause variations in the sampling instances which limit the dynamic performance of the T/H circuit (Razavi 997). The effect of the sampling time uncertainty is illustrated in Figure 5.5, where t is the desired sampling instant but due to clock jitter tδt is the actual sampling instant.

9 75 Signal Δ hange in during t =Sampling time uncertainty Ideal sampling instant tδt Actual sampling instant (Worst ase) Figure 5.5 Sampling time uncertainty The error Δ caused by this jitter delay. The error increases with high signal frequencies but is independent of sampling frequency. Much of the error causing sampling time uncertainty can be reduced by using the bottom plate sampling technique. The performance is however fundamentally limited by clock jitter in the clock generator. If the clock jitter is assumed to be random noise with variance (Laker and Sansen 994). σ t the error power can be approximated as where dvin Δ τ (5.8) dt E{ΔV } E τ E E τ dt dt dvin dvin IN E{Δ} is the noise power due to sampling time uncertainty. (5.9) d E A cos πfint σ dt t (5.0) (π A f in ) σ t (5.) where A is the magnitude of the input signal.

10 76 SNDR aperture 0 log (π f in σ t ) ENOB = SNDR aperture (5.) (5.3) The SNDR is independent of the signal frequency. To reduce the sampling time uncertainty, the clock is designed to give maximum rms jitter of one ps (Gustavsson et al 004). The obtainable ENOB as a function of the clock jitter, σ t, is plotted for different input frequencies in Figure 5.6. Effective Number Of Bits (ENOB) Effective Number of Bits (ENOB) MHz MHz 0MHz 50MHz 00MHz Sampling time uncertainty (ps) (ps) Figure 5.6 ENOB as a function of sampling time uncertainty

11 77 The following errors are associated with the sampling transistors Voltage Dependence of Switch An MOS transistor can be used as an analog switch shown in Figure 5.7. The gate voltage of the MOS controls the onresistance R ON of the drain and source (Razavi 995). V OUT Figure 5.7 MOS act as switch The switch always operates in the linear region and its onresistance is given by W V I D(triode) = µ V V V L DS OX GS t DS D R ON = dvds V DS0 di (triode) W µ OX (VGS V t ) L R ON = W µ OX ( VIN V t ) L (5.4) (5.5) In Equation (5.4), I D(triode) is the drain current during the transistor operating in the linear region, V GS is the gate source voltage, V DS is the drain source voltage and V t is the threshold voltage of the MOS transistor. In Equation (5.5), µ is the mobility, OX is the capacitance per unit area, W is the width and L is the length of the MOS transistor.

12 78 following problems From Equation (5.5), it is observed that the MOS switch has (i) (ii) Transistor turns off is signal dependent, occurs when = V t. R ON is modulated by ( = V DD = onstant). bootstrap switch. The above problems can be overcome by using MOS switch or 5..5 Track Mode Nonlinearity A frequency dependent nonlinearity error is introduced in MOS sampling circuits due to variation of the switch onresistance (the variation in the input signal). For high frequency inputs, this variation introduces input dependent phase shift and hence harmonic distortion (Razavi 995). The distortion caused by switchon resistance during the track mode is shown in Figure 5.8. The magnitude of the third harmonic due to the track mode nonlinearity is given by HD 3 in 4 VGS Vt A π f R (5.6) V R ON HIGH V OUT R ON LOW t Figure 5.8 Distortion caused by switchon resistance during track mode

13 79 To reduce the third harmonic distortion in high speed sampling circuit, either input signal swing is reduced (but this is not feasible for low noise contribution of T/H circuit) or R is selected greater than the Πf in (bigger switch). Otherwise MOS or bootstrap switch is employed in the T/H circuit to reduce the track mode nonlinearity error Signal Dependent Sampling Instant Normally ideal sampling instant is the mid of the clock phase. Due to rise time and fall time delay of the clock signal, if the signal is sampled other than VDD, it causes signal dependent error (Moscovici 000). This error is shown in Figure 5.9. This error is more dominant when the rate of change of input signal is faster than the falling rate of the clock signal. The THD of the THA is VLK THD = 0 log A f t in F (5.7) V LK and t F are the amplitude and fall time of the clock signal respectively. V LK LK Ideal sampling Instant V t V LK Actual sampling Instant t F t Figure 5.9 Signal dependent sampling instant error

14 80 Normally this is not a big issue for highspeed and mediumresolution pipelined AD. For example, 00MS/s sampling circuit, the clock frequency is 00MHz, the fall and rise time of the clock is few tens of ps. During Nyquist rate, input frequency (50MHz) the peaktopeak signal occurs during the time interval of 0ns and hence clock fall rate is steeper than rate of change of input signal Pedestal Error Pedestal error voltage is the offset voltage error introduced at the THA output during the transition from track mode to hold mode. This error caused due to finite overlap capacitance OV between gate and source or drain terminals as depicted in Figure 5.0. LK OV OV OFF H VOUT Figure 5.0 Transition of the switch state from track mode to hold mode When the gate control voltage changes the state to turns off the switch, OV conducts the transition and changes the voltage stored on the hold capacitor H by an amount equal to ΔV = OV OV H V LK (5.8)

15 8 OV ΔV = ( Vt L) (5.9) OUT OV IN H V = V ΔV (5.0) V = V (V V ) OV OUT IN IN t L OV H V OUT = (ε) V OS (5.) ε = V & V = (V ) OV OV IN OS t L OV H OV H In Equation (5.9), Φ L stands for V LK = 0V. In Equation (5.), ε stands for nonlinearity error and V OS stands for offset voltage. Pedestal voltage error can be reduced to minimum by selecting a larger value of the hold capacitor harge Injection Error In addition to finite onresistance, the MOS switch exhibits channel charge injection. When the MOS switch is on, it carries a strong channel charge under strong inversion region which can be expressed as Qh W L OX (VGS V t ) (5.) When the device is turned off, this charge leaves the channel through the drain and source terminals, introducing the error voltage in the sampling capacitors as depicted in Figure 5.. If the charge is not distributed uniformly over the drain and source terminals, it causes a nonlinearity error in the T/H circuit (Wegmann et al 987, Ding and Harjani 000). This error can be eliminated by using the bottom plate sampling technique.

16 8 Q h H V OUT Figure 5. harge injection error 5..9 Hold Mode Feedthrough The percentage of input signal appearing at the output during the hold mode is called the hold mode feedthrough (Plassche 007). This effect appears because the switch has parasitic capacitance path between the source and drain via gate overlap capacitance even in off state. This is shown in Figure 5.. This causes an additional noise in the T/H circuit. The hold mode feedthrough can be expressed as V π f R ; H OV (5.3) V 4π f R OUT OV in OUT OV (hold) IN H in OUT OV R OUT is the output resistance of the clock circuit. R OUT is selected such that, for the maximum input frequency, the hold mode feedthrough should be minimum. LK R OUT OV OV OFF H V OUT Figure 5. Hold mode feedthrough

17 Droop Rate When the T/H circuit is in the hold mode, the output signal is stored on the hold capacitor. The voltage across the hold capacitor is sensed with an amplifier with a small input bias current. This input bias current, together with possible leakage currents, discharge the hold capacitor, resulting in a droop of the voltage across this capacitor (Plassche 007). where leakage Ileakage V droop = T H ONV LK I is the leakage current, T ONV =, where LK= Larger value of hold capacitor is selected so as to reduce the droop rate. (5.4) f S 5.. ompensation methods for ircuit Nonidealities The nonidealities of the switched capacitor circuit cause nonlinearity errors in the AD. These nonlinearity errors can be reduced by combining the following compensation methods MOS Switch The signal swing is limited by the dynamic range of the MOS switches. In NMOS switches, the dynamic range is V DD V tn, where V tn includes the body effect also. Hence in the simple NMOS switch, the dynamic range of the signal swing is limited by (V DD V tn )/. The substantial increase in switch onresistance results in frequency dependent harmonic distortion component. omplementary switches are used to extend the signal swing as railtorail signal swing. A MOS switch is depicted in Figure 5.3.

18 84 Φ V OUT Figure 5.3 MOS switch The NMOS switch conducts the signal 0 < < V DD V tn and PMOS switch conducts the signal V tp < V DD, thereby providing railtorail as input and output signal swing. The onresistance of the MOS switch is independent of as shown in Figure 5.4. It minimizes the harmonic distortion caused by variation in onresistance (Razavi 995, Brown et al 006). R ON PMOS NMOS MOS 0 V tp V DD V tn Figure 5.4 Variation in onresistance of NMOS, PMOS and MOS switches

19 85 The onresistance of the MOS switch can be expressed as RON MOS W W µ (V V ) µ (V V ) n OX GSn tn p OX GSp tp L n L p (5.5) W W µ (V V V ) µ (V V ) n OX DD IN tn p OX IN tp L n L p W W W W µ n OX (VDD V tn ) µ nox µ pox VIN µ p OX V tp L n L n L p L p W W if µ n = µ p L L n p then R ON (MOS) W µ (V V V ) n OX DD tn tp L n (5.6) The channel charge Q h accumulated on the NMOS cancels the PMOS charge accumulation once their dimensions are equal. But the Q h depends on V GS V t, which is not same in NMOS and PMOS switches. In high speed applications, the switches must be turned on and off at the same instant, otherwise input dependent phase shift is introduced. Hence to overcome the charge injection error, bottom plate sampling technique is used in switched capacitor circuits Bootstrap Switch To reduce the signal dependant error associated with the transistor switches and to increase the linearity of the THA, the Bootstrapping technique is employed (Abo and Gray 999). The ideal bootstrapped MOS switch is

20 86 shown in Figure 5.5. During the OFF state ( = HIGH), the gate is grounded and the device is cutoff. Simultaneously, the capacitor, which acts as the battery, is charged to supply voltage. During the ON state ( = HIGH), the capacitor is then switched across the gate and source terminals of the switching device. A constant voltage of V DD is applied across the gatetosource terminals and a low onresistance is established from draintosource independent of the input signal. V DD boot G S Switch D Figure 5.5 Ideal bootstrap switch The logic can be implemented using an actual bootstrapped switch as shown in Figure 5.6. During the phase, the transistor M is to be switched off and during phase, the transistor M is to be switched on. During the phase, M 8 and M 9 discharge the gate voltage of M to ground. At the same time capacitor boot charges V DD via M 3 and M. This capacitor will act as a battery across the gate and source of M during phase. M 7 and M 0 isolate the switch from boot while it is charging up. During the phase, M 5 pulls down the gate of M 7 and makes a conducting path between the capacitor and M. M 0 enables gate G to track the input voltage at source S shifted by V DD and set the gatesource voltage constant regardless of the input signal. M 6 ensures that the M 7 gate voltage does not go beyond V DD. And M 8 reduces the V GS and V GD experienced by the device M 9 during

21 87 phase. To reduce the latch up problem M 7 substrate is tied up with its source terminal. boot must be sufficiently large to supply charge to the gate of the switching device in addition to all parasitic capacitances in the charging path. Otherwise, charge sharing will significantly reduce the boosted voltage according to Equation (5.7). V = V boot G VS DD boot P (5.7) where V S is the source voltage of the switch and P is the parasitic load at the gate of the switch transistor when is high (Abo and Gray 999, Jian Li et al 008). The V G (gate voltage) and V D (drain voltage) of bootstrap switch for V input signal and 00MHz sampling frequency are shown in Figure 5.7. The figure depicts that the gate signal is the superimposed component of and V DD. V DD M M M 3 M 7 M 8 M 9 V DD M 4 boot G M 5 M 6 M S M 0 M D G S D M V SWITH IN Figure 5.6 Actual bootstrap switch

22 88 Transient Response of Bootstrap switch V G V D Figure 5.7, V G and V D of the Bootstrap switch Bottom Plate Sampling Technique Bottom plate sampling technique is used to eliminate the charge injection error in switched capacitor circuit (Allstot and Black 983, Lee and Meyer 985). The circuitlevel implementation of the bottom plate sampling technique and the nonoverlapping clock phases are shown in Figures 5.8(a) and 5.8(b) respectively. Φ Φ M 3 Φ M 5 Φ M s F M 4 P Φ e M X V OUT Figure 5.8(a) ircuitlevel implementation of the bottom plate sampling technique

23 89 Φ Φ e Φ Figure 5.8(b) Nonoverlapping clock phases In this circuit S and F are the sampling and feedback capacitors respectively. P is the input capacitance (parasitic) of the OTA. When the clock phases and e are high, the capacitor s tracks the voltage across it. The total charge accumulated on node X in Figure 5.8(a) is Q(X(0)) = s (5.8) e falls earlier than, the transistor M is switched off. The total charge accumulated on node X is Q(X()) = s ΔQ (5.9) ΔQ is charge injection due to M turning off. When turns low, ΔQ leads to a change in voltage across all capacitors, but the total charge on node X remains unchanged. During the redistributed to the feedback capacitor. clock phase, the charge is Q(X())= F V OUT (5.30) By charge conversion principle Q(X()) = Q (X()) (5.3) s ΔQ = F V OUT

24 90 S ΔQ V OUT = F F (5.3) ΔQ. F The output signal contains the signal independent offset error This error can be easily cancelled by using fully differential switched capacitor circuit. 5.3 THA ARHITETURES The frontend THA circuit is an important part of the pipelined AD. The T/H circuit tracks the analog signal during the track period and holds the signal during the hold period. This often greatly relaxes the bandwidth requirements of consecutive MDA sections which now can work with a D voltage. Because the THA is often the first block in the signal processing chain, the accuracy and speed of entire application cannot exceed that of the T/H circuit. Hence the design of T/H circuit is more stringent than the overall design requirements of an AD (hanghyuk ho 005). Since, THA has been designed as a highgain and highbandwidth module, the power consumption is almost fifty percent of overall power consumption of the pipelined AD. Hence exploration of the circuit techniques for reducing the power consumption of the THA ultimately reduces the overall power consumption of the AD. Two different trackandhold amplifiers are investigated hargetransferring THA The first architecture is referred to as chargetransferring T/H circuit as shown in Figure 5.9 (Yen and Gray 98, Lewis and Gray 987). Four capacitors with the same value are used in this structure. During the

25 9 track phase ( = HIGH), the differential input signal is tracked by the two input sampling capacitors S. Next, during the hold phase ( = HIGH), the bottom plates of the two sampling capacitors are connected together. Thus only the differential charge is transferred to the feedback capacitors. As a result, this T/H can handle very large input commonmode variation. e is the early clock phase which performs the bottom plate sampling to avoid the charge injection errors during chargetransfer in THA (Allstot and Black 983, Lee and Meyer 985). F Φ Φ Φ V MI Bootstrap switch Φ e Φ e S S V MI X Φ e X Φ e Φ Φ Φ Φ V OUT V MO V OUT MOS switch F Φ TRAK PHASE Φ HOLD PHASE Φ Figure 5.9 hargetransferring trackandhold amplifier In this circuit, are differential input signals, V OUT and V OUT are differential output signals, V MI is the commonmode voltage. The nonoverlapping clock phases are as already shown in Figure 5.8(b). During the clock phase, the capacitor S acquires the charge. The charge stored in the capacitor on node X is S ( V MI ). During the clock phase, the

26 9 acquired charge is transferred to the F. The charge on the node X is conserved. Q(Φ ) = Q(Φ ) (5.33) S ( V MI ) = F (V OUT V MI ) (5.34) S S V MI = F V OUT F V MI S S V MI F V MI = F V OUT S Hence V OUT = V F V IN F S MI F (5.35) Since S = F ; V OUT = (5.36) 5.3. Fliparound THA The second architecture is the capacitor fliparound THA as shown in Figure 5.0. No chargetransfer occurs in this scheme and only two capacitors are used. During the track phase, the differential input signal is sampled by the input capacitors in the same way as the first THA. However, during the hold phase, the input capacitors are flipped over by connecting their bottom plates to the output of the amplifier. By doing this, both the commonmode and differentialmode charges are transferred (Yang et al 00, YunShiang Shu and BangSup Song 008). Though the commonmode feedback circuit of the amplifier will force the output commonmode to the nominal value, its input commonmode level will change according to the difference between the input signal s commonmode level and the commonmode level of the amplifier output. It means that the amplifier must be capable of handling a large input commonmode variation.

27 93 Φ Φ Φ V MI Bootstrap switch Φ e Φ e S S V MI X Φ e Φ e X Φ Φ Φ V MO V OUT V OUT Φ TRAK PHASE MOS switch Φ HOLD PHASE Figure 5.0 Fliparound trackandhold amplifier During the clock phase, the capacitor acquires the charge. The charge stored in the capacitor on node X = S ( V MI ). During the clock phase, the capacitor is fliparound. The charge stored in the capacitor on node X = S (V OUT V MI ). Q(Φ ) = Q(Φ ) (5.37) S ( V MI ) = S (V OUT V MI ) (5.38) Hence V OUT = (5.39) When parasitic capacitance is ignored, the feedback factor β of a fliparound THA is, whereas the feedback factor of a chargetransferring THA is 0.5. As the feedback factor of the fliparound THA is twice as large compared to the chargetransferring THA, it requires only half of OTA gain bandwidth to produce the same closedloop bandwidth. Thus, the same performance can be achieved with much less power by using the fliparound architecture. THA circuit contributes more than fifty percent of noise in AD. Reducing the THA noise, overall noise of the AD is significantly reduced.

28 94 The second advantage of fliparound architecture is that it contributes less noise. The noise contributed by the trackandhold amplifier circuit is the summation of noise contribution in the track phase and that in the hold phase. The hold phase noise depends on the topology of the OTA. In the fliparound architecture, the inputreferred noise in track phase is kt S, whereas in chargetransferring THA the inputreferred noise in the track phase is kt F S F. When S = F, the noise contribution is twice as that of fliparound architecture. The drawback of the fliparound THA is that, an OTA for a fliparound THA should have a large input commonmode range when the input commonmode level is different from the output commonmode level. In this design both the input and the output commonmode levels are set to the middle of a supply voltage. Hence there is no concern about the input commonmode range of an OTA. Therefore, the fliparound architecture is chosen for the advantages related to power and noise. Transient response of the fliparound THA for V pp differential input signal (V id ) and 00MHz sampling frequency is shown in Figure 5.. The figure depicts that the THA circuit perfectly tracks and holds the input signal at the rate of 00MS/s. V id Transient Response of FlipAround THA Differential output signal (V od) Figure 5. Transient response of the fliparound THA

29 MDA DESIGN The MDA combines the functions of a trackandhold, a DAS, a subtracter and a gain amplifier. Each MDA section is implemented using the switched capacitor circuit with the resolution of.5bitperstage and an interstage gain of as shown in Figure 5. (line 995, Iizuka et al 006, Picolli et al 008). F Φ V DAS Φ Φ V MI S Φ Φ V MI Φ e Φ Φ e Φ V OUT Φ V MO Φ S V OUT MOS SWITH Φ V DAS Φ Φ TRAK PHASE F Φ Φ HOLD PHASE.5bit ADS Bbit Reference Selector V DAS =DV REF V DAS V DAS V REF 4 V REF 4 Bbit VREF VREF Figure 5. Implementation of MDA in switched capacitor circuit

30 96 During the track phase ( =HIGH), the input signal is applied to the set of capacitors S and F and simultaneously quantized perstage resolution of B eff bit through the ADS function which has the threshold value of VREF VREF and 4 4. At the end of the track phase, is tracked across S and F and output of the ADS is latched. During the hold phase ( =HIGH), F closes negative feedback path around the OTA, the top plate of S is switched to the DAS output. The output of ADS is used to select the DAS output voltage according to the ADS input. Since the nonlinearity errors present in the MDA section is the same as THA section nonlinearity errors, the same circuit techniques are employed to reduce the nonlinearity errors in the MDA section. S F S V OUT = D V F F REF ; S = F V resi = V OUT = DV REF (5.40) 5.4. Selection of the Sampling apacitors based on The minimum size of the capacitor for a MDA section is selected (i) (ii) DNL error due to the capacitor mismatch and Thermal Noise consideration

31 apacitor Mismatch A precision interstage gain is required to achieve the desired overall AD linearity. Since the capacitor ratio S F determines this interstage gain, capacitor matching is critical. If the capacitors S and F are not equal, then an error proportional to the mismatch is generated in the residue output (Abo 999, Yun hiu et al 004a). Thus, accurate capacitor matching is required to design a high resolution pipelined AD. The integrated circuit capacitor value is given by ε = A = A OX OX tox (5.4) where A is the area of a capacitor, ε OX is the dielectric constant of silicon dioxide and t OX is the thickness of oxide. apacitance value depends on the area and oxide thickness of a capacitor. The main causes of capacitor mismatch are due to overetching and the oxidethickness gradient. The relative capacitance error can be expressed by Δ Δ ΔA = A OX OX (5.4) where Δ OX is an error in OX due to oxide thickness gradient and ΔA is an error in area A due to over etching. Since OX is fixed by a process technology, the accuracy of capacitance can be improved by simply increasing the area. However, in S circuits the accuracy of a capacitor ratio is of more concern rather than the accuracy of capacitance, because the gain of a MDA is decided by the capacitor ratio. Δ is the difference between S and F.

32 98 Δ (5.43) S F S = S F F ; S Δ Δ = and F= Δ Δ = (5.44) Δ The approximation holds if Δ. Therefore residue transfer function in Equation (5.40) is changed as V resi(new) = Δ Δ VIN D VREF (5.45) Therefore, the accuracy of a capacitor ratio can be improved if the difference of the mismatch errors of both capacitors is as small as possible. A mismatch error in the accuracy of a capacitor ratio due to over etching can be minimized by implementing capacitors with an array of small equal sized unit capacitors (Johns and Martin 004). A mismatch error in the ratio accuracy of capacitors is due to the variation of oxide thickness. This mismatch can be minimized by laying out capacitors in commoncentroid geometry. The inputreferred DNL error of the AD should be less than LSB. In a 0bit pipelined AD, considering the inputreferred DNL error, the capacitor mismatch should be Δ Δ < ; i.e. < 0.% BAD (5.46) It is possible to achieve less than 0.% capacitor mismatch error in modern digital MOS technology.

33 Thermal Noise consideration In analogtodigital converters, quantization noise is equal to the thermal noise. Quantization noise of the 0bit AD = VFS Δ= BAD ; in this design V FS = V pp., where Variance of the total quantization noise = V 0 = (564µV) (5.47) Hence total inputreferred noise is 564µV. The rms value of the total thermal noise referred to the input can be expressed as (Goes et al 998). Vni THA Vni stage Vni stage Vni stagem i m G G G G j j= Vn =... (5.48) In Equation (5.48), Vn itha stands for inputreferred thermal noise of THA section and Vnistage i stands for inputreferred thermal noise of i th stage. Normally in pipelined AD G =G =G i =G=. Except the track and hold stage other stage s total inputreferred noise is divided by the gain of the preceded stages as in Equation (5.48). Hence the maximum noise budget allowed for THA is normally 50% of overall noise budget and rest of the noise budget is shared by the MDAs. Maximum inputreferred noise allowed for trackandhold amplifier in both the cycles is 8µV. Rest of the noise budget is shared by the other stages. Transient response of the MDA section for the differential input signal of 800mV is shown in Figure 5.3. The maximum time period allowed for MDA to settle is 5ns. But the output

34 00 waveform (V od ) depicts that the MDA settles within half the hold time period (less than.5ns). Transient response of MDA section Track period Hold period Figure 5.3 Transient response of the MDA section 5.5 SUMMARY In this chapter, the design of highspeed, lowpower and lownoise THA and MDA functional blocks are presented. THA and MDA circuits are realized by using actual transistor switches and capacitors. Hence nonidealities are introduced in these analog blocks. A more detailed investigation on the nonidealities that affect the performance of the switched capacitor AD is discussed and certain circuit techniques are incorporated to reduce the nonlinearity errors. OTA is the key part of the THA and MDA sections. The main requirements of OTA design are: highgain, largebandwidth, largesignal swing, lownoise and lowpower consumption under

35 0 low supply voltage. Besides these, high power supply noise rejection ratio, high commonmode noise rejection ratio and high dynamic range are also desirable. Unfortunately, these factors cannot be improved simultaneously and many tradeoffs exist among them. So a good OTA design is the optimization of these factors according to the design specification. The following chapter presents the systematic design approach for operational transconductance amplifier to meet the design specifications.