Sampling and Quantization

Transcription

1 University of Saskatchewan EE Electrical Engineering Laboratory Sampling and Quantization Safety The voltages used in this experiment are less than V and normally do not present a risk of shock. However, you should always follow safe procedures when working on any electronic circuit. Assemble or modify a circuit with the power off or disconnected. Don t touch different nodes of a live circuit simultaneously, and don t touch the circuit if any part of you is grounded. Don t touch a circuit if you have a cut or sore that might come in contact with a live wire. Check the orientation of polarized capacitors before powering a circuit, and remember that capacitors can store charge after the power is turned off. Never remove a wire from an inductor while current is flowing through it. Components can become hot if a fault develops or even during normal operation so use appropriate caution when touching components. Objectives: To investigate PAM sampling and to observe the effects of sampling and quantization and to measure output quality in terms of signal to noise ratio (SNR) for PCM systems. Equipment: You will require a PAM module for the first part and a PCM module for the second part. You will also require a filter module The modules are available from the technicians in C. Reference: Virtual experiment found at Procedure: Sampling Pulse Amplitude Modulation. Obtain a PAM sampling module (Figure ) from the technicians and set up the sampling Fig. Sampling Module

2 University of Saskatchewan EE Electrical Engineering Laboratory gnd W (t) 0 ohm n v Sampling Module TTL clock Out khz LPF 0 v Fig. Sampling Circuit circuit of Figure. Use a pulse generator to generate a gating signal for the sampling module. Set the pulse voltage to TTL levels (0 V low to V high). Attach a khz filter module to the output of the sampling module. You will use a signal generator for the input signal for most of the steps below. Limit the input signal to ± V; larger signals may damage the sampling gate chip. The sampling module (Fig. ) uses a 0 CMOS switch, controlled by the gating pulse, to apply the input signal to either a 0K resistor or a 0 nf capacitor to ground, selected by switch S. With the 0K resistor selected, the output voltage will follow the input voltage so long as the 0 switch is closed but will be pulled to ground through the 0K resistor when the 0 switch is open. The result is natural sampling. With the 0 nf capacitor Fig. PAM Sampling Module

3 University of Saskatchewan EE Electrical Engineering Laboratory selected, the input voltage charges the capacitor while the 0 switch is closed and the voltage is maintained by the capacitor when the 0 switch is open. The result is flattop sampling provided the gate signal has a small duty cycle. A second 0 switch allows the capacitor to be discharged before the next sample resulting in less than 00% width flattop sampling. The timing is controlled by a PC microcontroller; the % width of flattop sampling is set by the dip switch. The TL0 voltage follower prevents loading of the sampling circuit by the device connected to the output.. Set the sampling pulse to 00 µs period (0 khz) and % duty cycle. Apply V DC to the input and confirm that the sampling gate is operating correctly. Use the 0K load resistor to produce natural sampling, and check the result with both an oscilloscope and a spectrum analyzer. Measure the spectrum and confirm that it agrees with theory.. Apply a V pp sinusoid at khz to the sampling circuit input. Display the input signal, the sampled signal and the filter output signal on the oscilloscope and spectrum analyzer. Measure the spectrum and confirm that it agrees with theory.. nvestigate how the sampled signal s spectrum and the filtered output wave form changes as a) the input signal frequency f m is increased b) the pulse duty cycle is increased c) the sampling frequency f s is altered d) f m is increased up to twice f s. Generate an approximation to flattop sampling by using the 0 nf capacitor in place of the 0K load resistor and by reducing the duty cycle of the gating pulses as much as possible; be sure the sampling frequency is 0 khz. Start with 00% width flattop sampling. Observe the sampled waveform on the oscilloscope and use the spectrum analyzer to observe baseband alias frequency components as the input signal frequency is increased up to and beyond f s. Confirm that the relative gain follows the theoretical sin x / x function part of which is shown in Figure. Switch to 0% and then % width flattop sampling and measure the relative gain as a function of signal frequency..0 % % 0. 0% Relative Gain 0. Sampling Frequency Fs = 0 khz 00% Frequency in khz Fig. Signal Gain in Flat Top Sampling

4 University of Saskatchewan EE Electrical Engineering Laboratory Procedure: Quantization Pulse Code Modulation. Obtain the PCM test module shown in Figure. The circuit uses a AD bit A/D converter to digitize the input signal. Provide a 00 khz TTL sampling clock to operate the converter. Apply a khz sine wave and adjust the amplitude to match the maximum input range of the A/D converter (about V pp ). The capacitive coupling and the resistor network is used to shift the input voltage so that the voltage applied to the A/D converter is positive. f the input range of the A/D converter is exceeded your signal will be clipped, but if your signal is much less than the input range then the effective number of bits will be reduced. The module also includes two bit DACs and switches that allow the bits to go to either the first or the second DAC. f n higher order bits are sent to the first DAC then its output will be the nbit PCM signal. The second DAC receives the n lower order bits, and its output approximates the error signal.. Using the setup of Figure without the speaker or voltmeter, observe and sketch the quantized signal and the error signal. Observe the effect of using different numbers of bits of quantization. Reduce the sampling frequency to 0 khz and measure the signaltonoise ratio (SNR) in the sampled signal after the khz lowpass filter for different n bits of quantization (the expected change is db per bit).. Plot the bit SNR as the signal level is reduced up to 0 db relative to the maximum NPUT.K AD SAMPLE CLOCK µf V MHZ CONVERSON CLOCK µf V µf CA0 ONE SHOT CLK AGND V VDD (LSB) D0 D AD AN VREF V 0 D D D D D (MSB) D TP RD C BUSY S DAC REF 0K pf DGND 0 V 0 0 (LSB) (MSB) V V (LSB) (MSB) V V DAC # DAC0 o Vref () Vref ( ) o VLC COMP V V DAC # DAC0 V V Vref () Vref ( ) o o VLC COMP. TL0. TL0 DAC REF DAC REF OUTPUT # TL0 OUTPUT # TL0 Fig. PCM A/D and D/A Circuit

5 University of Saskatchewan EE Electrical Engineering Laboratory Fig. PCM Measurement Setup signal. (Note that quantizing noise power should be constant except when overload occurs).. ncreasing the sampling rate improves the SNR of a bandlimited PCM system (i.e. a system with a lowpass filter on the output). Verify this experimentally by changing the sampling rate from 0 khz to 0 khz and measuring the SNR.