Lecture 21. Analog-to-Digital Converters (continued) Residue Type ADCs

Transcription

1 Lecture 21 Analogtoigital Converters (continued) Residue Type s Twotep flash Pipelined s Concept and basics of the architecture Effect of building block nonidealities on overall performance ub ubac ain stage Error correction by adding redundancy igital calibration Correction for interstage gain nonlinearity EEC 247 Lecture 21: ata Converters: Nyquist Rate s 21 Page 1 Architectures lope type converters uccessive approximation Flash Interpolating & Folding Residue type s Twostep Flash Pipelined s Timeinterleaved / parallel converter Oversampled s EEC 247 Lecture 21: ata Converters Nyquist Rate s 21 Page 2

2 [LB] Twotep Example: (22)Bits 2bit 2bit??? e q1 out out = e q1 Using only one : output contains large quantization error "Missing voltage" or "residue" ( e q1 ) Idea: Use second to quantize and add e q Input [LB] EEC 247 Lecture 21 Residue Type s 21 Page 3 Two tage Example ref1 Coarse 2bit 2bit AC e q1 e q2 out = e q1 e q1 Fine 2bit e q1 e q2 2 Use AC to compute missing voltage Add quantized representation of missing voltage Why does this help? How about e q2? ince maximum voltage at input of the 2 nd is 1 /4 then for 2 nd 2 =1 /4 and thus e q2 = e q1 /4 =1 /16 4bit overall resolution EEC 247 Lecture 21 Residue Type s 21 Page 4

3 Two tep (22) Flash 4bit traight Flash Ideal 2step Flash oltage quantized by 2 nd EEC 247 Lecture 21 Residue Type s 21 Page 5 Two tage Example e q / econd Fine First Coarse Fine is reused 2 2 times Fine 's full scale range needs to span only 1 LB of coarse quantizer ref 2 ref 1 eq EEC 247 Lecture 21 Residue Type s 21 Page 6

4 Bit Combiner (B1B2)Bit Twotage (22) Transfer Function out Coarse Bits (MB) Fine Bits (LB) 1 EEC 247 Lecture 21 Residue Type s 21 Page 7 Residue or Multitep Type Issues in Coarse (B1Bit) AC (B1Bit) Residue Fine (optional) (B2Bit) Operation: Coarse determines MBs AC converts the coarse output to analog Residue is found by subtracting ( AC ) Fine converts the residue and determines the LBs Bits are combined in digital domain Issue: 1. Fine has to have F=F coarse /2 B1 & precision in the order of overall 1/2LB 2. peed penalty Need at least 1 clock cycle per extra series stage to resolve one sample EEC 247 Lecture 21 Residue Type s 21 Page 8

5 olution to Issue (1) Reducing Precision Required for Fine 2bit Coarse 2bit AC e q1 =2 B1 2bit Fine e q1 e q2 out = e q1 e q1 e q2 Accuracy needed for fine relaxed by introducing interstage gain Example: By adding gain of x(=2 B1 =4) prior to fine in (22)bit case, precision required for fine is reduced to 2bit only! Additional advantage coarse and fine can be identical stages EEC 247 Lecture 21 Residue Type s 21 Page 9 olution to Issue (2) Increasing Throughput 2bit Coarse 2bit AC T/H(=2 B1 ) e q1 Fine T/H 2bit out = e q1 e q1 e q2 Conversion time significantly decreased by employing T/H between stages All stages busy at all times operation concurrent uring one clock cycle coarse & fine s operate concurrently: First stage samples/converts/generates residue of input signal sample # n While 2 nd stage samples/converts residue associated with sample # n1 EEC 247 Lecture 21 Residue Type s 21 Page 1

6 Residue Type s Twotep flash Pipelined s Basic operation Effect of sub, subac, gain stage nonidealities on overall performance Error correction by adding redundancy igital calibration Correction for interstage gain nonlinearity Implementation Practical circuits tage scaling Combining the bits tage implementation Circuits Noise budgeting How many bits per stage? EEC 247 Lecture 21 Pipelined s 21 Page 11 Pipeline Block iagram tage 1 B 1 Bits tage 2 B 2 Bits res2 tage k B k Bits MB......LB Align and Combine ata igital output (B 1 B 2... B k ) Bits Idea: Cascade several low resolution stages to obtain high overall resolution (e.g. 1bit can be built with series of 1 s each 1bit only!) Each stage performs coarse A/ conversion and computes its quantization error, or "residue All stages operate concurrently EEC 247 Lecture 21 Pipelined s 21 Page 12

7 Pipeline Concurrent tage Operation f 1 f 2 acquire convert tage 1 B 1 Bits convert acquire tage 2 B 2 Bits tage k B k Bits CLK f 1 f 2 Align and Combine ata igital output (B 1 B 2... B k ) Bits tages operate on the input signal like a shift register New output data every clock cycle, but each stage introduces at least ½ clock cycle latency EEC 247 Lecture 21 Pipelined s 21 Page 13 Pipeline Latency Note: One conversion per clock cycle & 8 clock cycle latency [Analog evices, A bit ata heet] EEC 247 Lecture 21 Pipelined s 21 Page 14

8 Pipelined Characteristics Number of components (stages) grows linearly with resolution Pipelining Trading latency for overall component count Latency may be an issue in e.g. control systems Throughput limited by speed of one stage Fast ersatile: bits, 1...4M/s One important feature of pipelined s: many analog circuit nonidealities can be corrected digitally EEC 247 Lecture 21 Pipelined s 21 Page 15 Pipeline igital ata Alignment f 1 f 2 acquire convert convert acquire tage 1 B 1 Bits tage 2 B 2 Bits tage k B k Bits CLK f 1 f 2 out CLK CLK CLK igital shift register aligns subconversion results in time EEC 247 Lecture 21 Pipelined s 21 Page 16

9 Cascading More tages ref /2 B1 /2 (B1B2) /2 (B1B2B3) B 1 bits B 2 bits B 3 bits AC LB of last stage becomes very small All stages need to have full precision Impractical to generate several EEC 247 Lecture 21 Pipelined s 21 Page 17 Pipeline Intertage ain Elements T/H&2 B1 T/H&2 B2 T/H&2 B3 B 1 bits B 2 bits B 3 bits AC Practical pipelines by adding interstage gain use single Precision requirements decrease down the pipe Advantageous for noise, matching (later), power dissipation All stages can operate concurrently Throughput 1sample/clock cycle EEC 247 Lecture 21 Pipelined s 21 Page 18

10 Complete Pipeline tage e q1 res Bbit Residue Plot E.g.: B=2 =2 2 =4 Bbit AC res Note: None of the blocks have ideal performance Question: What is the effect of the nonidealities? ref EEC 247 Lecture 21 Pipelined s 21 Page 19 Pipeline Errors Nonidealities associated with subs, subacs and gain stages error in overall pipeline performance Need to find means to tolerate/correct errors Important sources of error ub errors comparator offset ain stage offset ain stage gain error ubac error EEC 247 Lecture 21 Pipelined s 21 Page 2

11 Pipeline ingle tage Model e q res e q out res = xe q EEC 247 Lecture 21 Pipelined s 21 Page 21 Pipeline Multitage Model, e q1 1 res2 res(n1) e q2 2 e q(n1) n1 1 2 (n1) n e qn out 1/ d1 1/ d2 1/ d(n1) e q2 2 out in, eq1 d1 d1 d 2 e... 1 e q( n1) ( n1) qn n2 n1 dj d( n1) j1 j1 dj EEC 247 Lecture 21 Pipelined s 21 Page 22

12 Pipeline Model If the "Analog" and "igital" gain/loss is precisely matched: e qn ref out in, where e & Bn # of n 1 2 qn Bn j j1 ref rms F ignal. R. 2log 2log 2 2 2log rms Quant. Noise B Bn log 2 2 n1 j1 j 12 2 ref n1 Bn j1 j bits in final stage 3 Bn 2 2 n1 j1 j B B log n n1 2 j1 j EEC 247 Lecture 21 Pipelined s 21 Page 23 Pipeline Observations The aggregate resolution is independent of sub resolution! Effective stage resolution B j =log 2 ( j ) Overall conversion error does not (directly) depend on sub errors! Only error term in out contains quantization error associated with the last stage o why do we care about sub errors? o back to two stage example EEC 247 Lecture 21 Pipelined s 21 Page 24

13 Pipeline ub Errors, B1 =2bits 2bits ref e q2 e qn out in, n 1 j j1 out in, out=1 e q2 1 EEC 247 Lecture 21 Pipelined s 21 Page 25 Pipeline ub Errors, B1 =2bits 2bits offset ref e q2 e qn out in, n 1 j j1 out in, e q2 rows outside ½ LB bounds 1 EEC 247 Lecture 21 Pipelined s 21 Page 26

14 Pipeline 1 st tage Comparator Offset Problem: exceeds 2 nd pipeline stage overload range res2 Overall Transfer Curve First stage Levels: (Levels normalized to LB) Ideal comparator threshold: 1,, 1 Comparator threshold including offset: 1,.3, 1 Missing Code! EEC 247 Lecture 21 Pipelined s 21 Page 27 Pipeline Three Ways to eal with ub Errors All involve sub redundancy Redundancy in stage that produces errors Choose gain for residue to be processed by the 2 nd stage < 2 B1 Higher resolution sub & subac Redundancy in succeeding stage(s) EEC 247 Lecture 21 Pipelined s 21 Page 28

15 (1) Intertage ain Following 1 st tage <2 B1 B 1 bits Choose 1 less than 2 B1 Effective stage resolution could become noninteger B 1eff =log 2 1 E.g. if 1 =3.8 B 1eff =1.8bit e q2 Ref: A. Karanicolas et. al., JC 12/1993 EEC 247 Lecture 21 Pipelined s 21 Page 29 Correction Through Redundancy enlarged residuum still within input range of next stage res2 Overall Transfer Curve If 1=2 instead of 4 Only 1bit resolution from first stage (3bit total) In spite of comparator offset: No overall error! EEC 247 Lecture 21 Pipelined s 21 Page 3

16 (2) Higher Resolution ub B 1 bits Keep 1 precise power of two (e.g. 1 =4) Add extra decision levels in sub (e.g. add 1 extra bit to 1 st stage) E.g. B 1 =B 1eff 1 e q2 Ref: inger et. al., LI 1996 EEC 247 Lecture 21 Pipelined s 21 Page 31 (3) OverRange Accommodation Through Increase in Following tage Resolution, B 1 bits No redundancy in stage with errors Add extra decision levels in succeeding stage e q2 Ref: Opris et. al., JC 12/1998 EEC 247 Lecture 21 Pipelined s 21 Page 32

17 Redundancy The preceding analysis applies to any stage in an nstage pipeline Can always perceive a multistage pipelined as a single stage backend B 1 bits B 2 bits B 3 bits B 4 bits B 1 bits res1 B 2 B 3 B 4 bits EEC 247 Lecture 21 Pipelined s 21 Page 33 Redundancy In literature, sub redundancy schemes are often called "digital correction" a misnomer! No error correction takes place We can tolerate sub errors as long as: The residues stay "within the box", or Another stage downstream "returns the residue to within the box" before it reaches last quantizer Let's calculate tolerable errors for popular "1.5 bits/stage" topology EEC 247 Lecture 21 Pipelined s 21 Page 34

18 1.5Bit/tage Pipelined 1.5bit 1.5bit AC res1 e q1 =2 =2 Effective bit/stage B eff =log 2 =log 2 2=1 Actual bit/stage B=log 2 (21)= bit/stage.5bit redundancy Ref: Lewis et. al., JC 3/1992 EEC 247 Lecture 21 Pipelined s 21 Page Bits/tage Example Comparators threshold levels placed strategically =2 B eff =log 2 =log 2 2=1 B=log 2 (21)= os = /8.5bit redundancy Ref: Lewis et. al., JC 3/1992 EEC 247 Lecture 21 Pipelined s 21 Page 36

19 3tage 1.5bitpertage Pipelined res2 res3 Overall Transfer Curve All three stages Comparator with offset Overall transfer curve No missing codes ome NL error Ref:. Lewis et al, A 1b 2M/s Analogtoigital Converter, J. olidtate Circ., pp. 3518, March 1992 EEC 247 Lecture 21 Pipelined s 21 Page 37 ummary o Far Pipelined A/ Converters B 1 bits 2 B1eff B 2B2 2 2 bits 2 B2eff B 3 bits 2 B3eff AC Cascade of low resolution stages tages operate concurrently trades latency for overall component count Throughput limited by speed of one stage Fast Errors and correction Builtin redundancy compensate for sub inaccuracies (interstage gain: =2 Bneff, B neff < B n ) EEC 247 Lecture 21 Pipelined s 21 Page 38

20 Pipeline Errors Nonidealities associated with subs, subacs and gain stages error in overall pipeline performance Need to find means to tolerate/correct errors Important sources of error ub errors comparator offset ain stage offset ain stage error ubac error EEC 247 Lecture 21 Pipelined s 21 Page 39 Intertage Amplifier Offset os AC os res os Input referred converter offset usually no problem Equivalent sub offset accommodated through adequate redundancy EEC 247 Lecture 21 Pipelined s 21 Page 4

21 Pipeline Errors Nonidealities associated with subs, subacs and gain stages error in overall pipeline performance Need to find means to tolerate/correct errors Important sources of error ub errors comparator offset ain stage offset ain stage gain error ubac error EEC 247 Lecture 21 Pipelined s 21 Page 41 ain tage ain Error, e q1 res1 res2 res(n1) 2 n1 e e q2 q(n1) 1 2 (n1) n e qn out 1/( d1 ) 1/ d2 1 out in, eq11 d1 e e q2 2 q( n1) ( n1) qn n2 n1 d1 d 2 d ( n1) dj dj j1 j1 e 1/ d(n1) Resolution is function of log 2 therefore error in affects resolution mall amount of gain error can be tolerated EEC 247 Lecture 21 Pipelined s 21 Page 42

22 out(ideal) out res out Interstage ain Error First tage Residue (ain Error) 1 Converter Transfer Function (ain Error) in in Transfer Function Error(ain Error) in EEC 247 Lecture 21 Pipelined s 21 Page 43 ain tage ain Inaccuracy ain error can be compensated in digital domain "igital Calibration" Problem: Need to measure/calibrate digital correction coefficient Example: Calibrate 1bit first stage Objective: Measure in digital domain EEC 247 Lecture 21 Pipelined s 21 Page 44

23 Model Backend back 1bit = =1 1bit AC in 2 res1 in AC in AC AC ( ) ( 1) ref / 2 EEC 247 Lecture 21 Pipelined s 21 Page 45 ain tage Inacurracy Calibration tep 1 = const. (1) Backend back (1) 1bit 1 M U X 1bit AC (1) res1 (1) back in in ref ref ref / 2 / 2 store EEC 247 Lecture 21 Pipelined s 21 Page 46

24 ain tage Inacurracy Calibration tep 2 = const. (2) Backend back (2) 1bit M U X 1bit AC (2) res1 (2) back in in ref store EEC 247 Lecture 21 Pipelined s 21 Page 47 ain tage Inacurracy Calibration Evaluate (1) back (2) back (1) back (2) back in in ref ref ref 1 2 / 2 To minimize the effect of backend noise perform measurement several times and take the average EEC 247 Lecture 21 Pipelined s 21 Page 48

25 Accuracy Bootstrapping, e q1 res1 res2 res(n1) 1 2 n1 e e q2 q(n1) 1 2 (n1) n e qn out 1/ d1 1/ d2 1/ d(n1) e 1 q2 2 q( n 1) ( n 1) qn out in, e q n2 n1 d1 d1 d 2 d ( n 1) dj dj j1 j1 Highest sensitivity to gain errors in frontend stages e e EEC 247 Lecture 21 Pipelined s 21 Page 49 "Accuracy Bootstrapping" irection of Calibration ufficiently Accurate tage 1 tage 2 tage 3 tage k B n bits Ref: A. N. Karanicolas et al. "A 15b 1Msample/s digitally selfcalibrated pipeline," IEEE J. Of olidtate Circuits, pp , ec E.. oenen et al., "An architecture and an algorithm for fully digital correction of monolithic pipelined s," TCA II, pp , March 1995 L. inger et al., "A 12 b 65 Mample/s CMO with 82 db FR at 12 MHz," ICC 2, igest of Tech. Papers., pp. 389 (calibration in opposite direction!) EEC 247 Lecture 21 Pipelined s 21 Page 5

26 Pipeline Errors Nonidealities associated with subs, subacs and gain stages error in overall pipeline performance Need to find means to tolerate/correct errors Important sources of error ub errors comparator offset ain stage offset ain stage error ubac error EEC 247 Lecture 21 Pipelined s 21 Page 51 AC Errors Backend B 1 bit B 1 bit AC e AC out 1/ back Can be corrected digitally as well ame calibration concept as gain errors ary AC codes & measure errors via backend EEC 247 Lecture 21 Pipelined s 21 Page 52

27 AC Calibration tep 1 = const. Backend B 1 bit M U X B 1 bit AC e AC () out 1/ back e AC () equivalent to offset ignore EEC 247 Lecture 21 Pipelined s 21 Page 53 AC Calibration tep B1 = const. Backend B 1 bit M U X B 1 bit AC e AC (1...2 B11 ) B Cal. Register out 1/ back tepping through AC codes B1 1 yields all incremental correction values Measurements repeated and averages to account for variance associated with noise EEC 247 Lecture 21 Pipelined s 21 Page 54

28 Pipeline Example: Calibration Hardware Above block diagram may seem extensive however, in current fineline CMO technologies digital portion of a pipeline s consume insignificant power and area compared to the analog sections Ref: E.. oenen et al., "An architecture and an algorithm for fully digital correction of monolithic pipelined s," TCA II, pp , March 1995 EEC 247 Lecture 21 Pipelined s 21 Page 55 ummary o Far Pipelined A/ Converters T/Hain B 1 bits 2 B1eff B 2B2 2 2 bits 2 B2eff B 3 bits 2 B3eff Cascade of low resolution stages By adding interstage gain= 2 Beff No need to scale down ref for stages down the pipe Reduced accuracy requirement for stages coming after stage 1 Addition of Track & Hold function to interstagegain tages can operate concurrently Throughput increased to as high as one sample per clock cycle Latency function of number of stages & conversionperstage Correction for circuit nonidealities Builtin redundancy compensate for sub inaccuracies such as comparator offset (interstage gain: =2 Bneff, B neff < B n ) Error associated with gain stage and subac calibrated out EEC 247 Lecture 21 Pipelined s 21 Page 56