EE290C - Spring 2004 Advanced Topics in Circuit Design High-Speed Electrical Interfaces. Agenda

Transcription

1 EE290C - Spring 2004 Advanced Topics in Circuit Design High-Speed Electrical Interfaces Lecture 6 Equalizers Borivoje Nikolic February 5, Agenda Equalization Background Implementation of Equalizers Digital Receive Equalizers Mixed-Signal Receive Equalizers Transmit Equalizers Some practical implementations Summary 2 1

2 Link as a Communication System Communication through a band-limited channel Tx Rx Channel H(f) channel frequency 3 Inter-Symbol Interference Effects of frequency-selective attenuation in the time domain No ISI x[nt] x[mt] = 0 m? n No ISI x[nt] x[mt]? 0 m? n 4 2

3 Channel General channel should be ISI-free Tx Rcvr Front-End Slicer/ Detector Channel ISI-free channel 5 Equalizer Most channels are low-pass Channel Eq H(f) Channel G(f) Equalizer G(f)H(f) Channel + equalizer f Band-limited channel (w/isi)? f no ISI f 6 3

4 Equalizer: Amplitude + Phase 1 H(f) channel 10 G(f) Equalizer H(f) channel f 90 o G(f) Equalizer f -90 o 0 f Band-limited channel (w/isi)? f no ISI 7 Implementing Equalizers Digital receive equalizers Analog receive equalizers Transmit equalizers 8 4

5 Receive Equalizers Digital equalizer Mixed-signal equalizer 9 Receive Equalizers ADC resolution H(f) channel QN Analog equalizers can reduce the resolution requirement for the ADC f 10 5

6 Implementing Equalizers Digital receive equalizers Analog receive equalizers Transmit equalizers 11 y Transversal Filter FIR filter, direct form [ n] = a x[ n] + a x n 1] + a x[ n 2] a x[ n N 1] 0 1 [ 2 N

7 Critical Path Digital FIR T = T mult + (N-1)T add 13 Pipelining Pipelining can be used in both digital and analog (mixed-signal) implementations to increase throughput Pipelining: Adding same number of delay elements in each forward cutset (in the data-flow graph) from the input to the output Cutset: set of edges in a graph that if removed, graph becomes disjoint Forward cutset: cutset from input to output over all edges Increases latency Register overhead (power, area) 14 7

8 Pipelining 3-tap FIR 15 Pipelined Direct FIR Critical path T = T mult + T add 16 8

9 Multi-Operand Addition Adders form a tree T = T mult + (log 2 N)T add 17 Multi-Operand Addition Using 3:2 or 4:2 compression Optional pipelining, 1-2 stages 18 9

10 Transposing FIR Transposition: Reversing the direction of all the edges in a signal-flow graph, Interchanging the input and output ports Functionality unchanged 19 Transposed FIR Represent as a signal-flow graph 20 10

11 Transposed FIR T = T mult + T add Critical path shortened Input loading increased 21 Parallel FIR Feed-forward algorithms are easy to parallelize Processing element representation of a transversal filter a 1 x[n] x[n-1] x[n-2] 0 a 0 a 1 a 2 y[n] Processing element Transversal filter 22 11

12 Parallel FIR Two parallel paths Two cycles to complete operation Can be extended to more Two parallel path FIR Processing element 23 Practical Digital Equalizers Mita, ISSCC 96, two parallel paths 150Mb/s 0.7µm BiCMOS 24 12

13 Practical Digital Equalizers Moloney, JSSC 7/98, 2 parallel paths, 3:2 Wallace 150Mb/s 0.7µm BiCMOS 25 Practical Digital Equalizers Wong, Rudell, Uehara, Gray JSSC 3/95, 4 parallel paths 50Mb/s, 1.2µm CMOS 26 13

14 Practical Digital Equalizers Thon, ISSCC 95 Transposed filter, 240Mb/s 0.8µm 3.7V CMOS, 150mW 27 Practical Digital Equalizers Staszewski, JSSC 8/00 2 parallel transposed paths 550Mb/s 0.21µm CMOS, 36mW 28 14

15 Practical Digital Equalizers Rylov, ISSCC Gb/s, 1.2W, 0.18µm domino CMOS 29 Practical Digital Equalizers Tierno, ISSCC Gb/s, 450mW, 0.18µm 2.1V domino CMOS 30 15

16 Implementing Equalizers Digital receive equalizers Analog receive equalizers Transmit equalizers 31 Analog Receive Equalizers Delay-line-based FIR Straightforward, direct or transpose Needs two S/H per tap S/H offset, noise, error accumulate Shuffling architectures Digital shuffling of tap coefficients Shuffling of analog inputs in the current domain 32 16

17 Practical Analog Equalizers Coefficient shuffling Lee, Razavi, CICC Practical Analog Equalizers Xu, ISSCC MHz, 9-tap, 0.6µm CMOS, 500mW 34 17

18 Practical Analog Equalizers Lee, CICC 01, 125MHz, 1000Base-T 35 Receive Equalizers ADC resolution H(f) channel 1 After pre-equalization QN Before pre-equalization Analog pre-equalizers can reduce the resolution requirement for the ADC f 36 18

19 Boost in CTF E.g. 7-p 2-z CTF See calculation in A. Hadji-Abdolhamid, D. Johns, ESSCIRC Implementing Equalizers Digital receive equalizers Analog receive equalizers Transmit equalizers 38 19

20 Transmit Equalizers TP TN TP TN A[2] W/L A[0] W/L A[1] W/L 1/z B[0] 1/z W/L A[0] W/L... 1/z W/L E[0] Simple 2P/4P Tx Equalizing 5-Tap 2P/4P Tx 39 Transmit Equalizers : / : $ >@ : ( >@ $OORFDWLRQ /RJLF : / $>@ (>@ %>@ : / : % >@ $>@ (>@ $>@ : / : / (>@ : / : ( >@ : $ >@ (>@ : / : ( >@ Original 5-Tap 2-PAM/4-PAM equalizing transmitter 7RWDOJDWH : / Shared equalizing transmitter 40 20

21 Summary Digital receive equalizers are a solution with <2Gb/s and low ADC (~6-b) resolutions Power is an issue Mixed signal receive equalizers are hard to build Lower power Reduce ADC resolution requirements High signaling rates transmit equalization 41 References R. Jain, P.T. Yang, T. Yoshino, "FIRGEN: a computer-aided design system for high performance FIR filter integrated circuits," IEEE Transactions on Signal Processing, vol.39, no.7, pp , July R.A. Hawley, B.C. Wong, T.-J. Lin, J. Laskowski, H. Samueli, "Design techniques for silicon compiler implementations of high-speed FIR digital filters," IEEE Journal of Solid-State Circuits, vol.31, no.5, pp , May W.L. Abbott, et al, A digital chip with adaptive equalizer for PRML detection in hard-disk drives IEEE International Solid -State Circuits Conference, Digest of Technical Papers, ISSCC 94, San Francisco, CA, Feb , 1994, pp D.J. Pearson, et al, Digital FIR filters for high speed PRML disk read channels, IEEE Journal of Solid-State Circuits, vol.30, no.12, pp , May S. Mita, et al, A 150 Mb/s PRML chip for magnetic disk drives, IEEE International Solid-State Circuits Conference, Digest of Technical Papers, ISSCC 96, San Francisco, CA, Feb. 8-10, 1996, pp , 418. D. Moloney, J. O'Brien, E. O'Rourke, F. Brianti, "Low-power 200-Msps, area-efficient, five-tap programmable FIR filter," IEEE Journal of Solid-State Circuits, vol.33, no.7, pp , July C.S.H. Wong, J.C. Rudell, G.T. Uehara, P.R. Gray, "A 50 MHz eight-tap adaptive equalizer for partial-response channels," IEEE Journal of Solid-State Circuits, vol.30, no.3, pp , March L.E. Thon, P. Sutardja, F.-S. Lai, G. Coleman, "A 240 MHz 8-tap programmable FIR filter for disk-drive read channes," 1995 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, ISSCC '95, pp.82-3, 343, San Francisco, CA, Feb R. B. Staszewski, K. Muhammad, P. Balsara, "A 550-MSample/s 8-Tap FIR Digital Filter for Magnetic Recording Read Channels," IEEE Journal of Solid-State Circuits, vol. 35, no. 8, pp , August S. Rylov, et al, A 2.3 GSample/s 10-tap digital FIR filter for magnetic recording read channels, IEEE International Solid -State Circuits Conference, Digest of Technical Papers, ISSCC 01, San Francisco, CA, Feb. 5-7, 2001, pp J. Tierno, et at, A 1.3 GSample/s 10-tap full-rate variable-latency self-timed FIR filter with clocked interfaces, IEEE International Solid -State Circuits Conference, Digest of Technical Papers, ISSCC 02, San Francisco, CA, Feb. 3-7, 2002, pp ,