Studies on FIR Filter Pre-Emphasis for High-Speed Backplane Data Transmission
|
|
- Ashlynn Sims
- 6 years ago
- Views:
Transcription
1 Studies on FIR Filter Pre-Emphasis for High-Speed Backplane Data Transmission Miao Li Department of Electronics Carleton University Ottawa, ON. K1S5B6, Canada Tel: Yuming Tao Ottawa IC Development ALTERA Corp. Ottawa, ON. K2K3C9 Canada Tel: Shoujun Wang Ottawa IC Development ALTERA Corp. Ottawa, ON. K2K3C9 Canada Tel: Tad Kwasniewski Department of Electronics Carleton University Ottawa, ON. K1S5B6, Canada Tel: Abstract -- FIR filter-based transmitter pre-emphasis has been used to counteract inter-symbol interference (ISI) in high-speed backplane data transmission. In this paper, backplane channel characteristics are analyzed in both time and frequency domains. The analysis performed demonstrates that group delay distortion is a major ISI contributor in addition to amplitude attenuation. A Matlab program is then used to optimize FIR filter coefficients. Both symbol-spaced FIR (SSF) and fractionally-spaced FIR (FSF) techniques are compared at , 6.5-, and 1-Gbps data rates. Finally, the results obtained from Matlab and ADS are compared. Keywords: FIR filter, ISI, Pre-emphasis, backplane, LMS I. INTRODUCTION Inter-symbol-interference (ISI) is a major factor limiting the maximum distance and data rate of high-speed serial backplane data transmissions. ISI is caused by channel bandwidth limitations due to impairments of physical backplanes, such as skin-effect loss, dielectric losses, reflection, cross talk, etc. The overall effect of this distortion is that the receive eye at the far-end of a backplane can become too small to be recovered by the clock-data-recovery (CDR) block and bit errors start to appear. There are numerous techniques to increase the eye opening. Of these, pre-emphasis at the transmitter side has been proven to be one of the most effective techniques [1,2]. The FIR filter-based pre-emphasis function is used to boost the high-frequency content of the transmitted signal, thereby extending the bandwidth of the combined pre-emphasis and channel transfer functions. There are two types of FIR filters considered here: symbol-spaced and fractionally spaced. Due to the parametric variation of a physical backplane, an optimized FIR is required to obtain the best performance at the receive side. A Matlab coefficient estimator/simulator program, therefore, has been developed to study the FIR filter pre-emphasis applied in backplane data transmission. This paper starts with the channel characteristics analyzed in Section II. The Matlab program and flow-chart are described in Section III. Simulation results are presented and analyzed in Section IV. The results obtained with behavioral the Matlab and transistor-level ADS simulators are also compared in that section. Final conclusions are provided in Section V. II. CHANNEL CHARACTERISTICS Figure 1 shows the configuration of a backplane transceiver link with FIR pre-emphasis. The entire backplane channel typically consists of a transmitter daughter card, connector, backplane, another connector, and another receiver daughter card. Figure 1. FIR pre-emphasis for backplane channel In this paper, a Tyco XAUI 34-inch FR4 backplane (referred to as 34-inch backplane) with two daughter cards is used as the channel model for FIR filter studies. The actual channel characteristics can be fully described by the measured differential S-parameters [3]. Figure 2 shows the amplitude attenuation and group delay of the backplane. The bandwidth limitation effects on ISI and the group delay variation of a linear low-pass element are well understood. It should be noted, however, that additional group delay distortion, as observed in Figure 2, is also a major ISI contributor. This group delay distortion of a physical
2 backplane can be attributed to the skin effect and undesired high-order modes existing within connectors and the transmission line. Figure 2 shows the channel impulse response with and without any group delay distortion (for clarity of the argument). For the no-group-delay case, the channel impulse response is attenuated, but dispersed symmetrically. The impulse response becomes asymmetrical when the channel impairments, in particular the group delay distortion, are fully included. Interestingly, the group delay is likely to speed up the leading edge of the impulse response, causing a long tail, as shown in Figure 2. For this 34-inch backplane, the pre-cursor ISI value seems to be negligible. As a consequence, the group delay distortion visibly degrades the eye opening as shown in Figure 3. The group delay distortion, therefore, should be taken into account for channel modeling and FIR filter design. Amplitude attenuation (db) Group delay (sec) Impulse response of channel (volt) Frequency (Hz) x 1-9 x Frequency (Hz) with group delay without group delay x1-9 Figure 2. Backplane channel characteristics: Measured frequency response and Impulse response with and without group delay distortion Eye diagram without group delay x Eye diagram with group delay x 1-1 Figure 3. Far-end eye diagrams at data rate of Gbps: without group delay distortion and with group delay distortion x n III. MATLAB PROGRAM D D D C C 1 C 2 C N-2 C N-1 - Figure 4. FIR filter structure The structure of the FIR filter is shown in Figure 4. For symbol-spaced FIR (SSF), the delay D is equal to one symbol period T. The transfer function of SSF in z- domain is given by: H N 1 = n () z C n z n= where C n is the tap coefficient, z = exp( j2πf / f s ), and the sampling frequency f s = 1/ T. For a fractionally spaced FIR (FSF), the delay D is a fraction of T (e.g., D=T/2). A Matlab program is developed to aid FIR-filter-based preemphasis design in backplane data communications applications. It consists of two parts: a tap-coefficients y n (1)
3 calculator and a backplane link simulator, as shown in Figure 5Error! Reference source not found.error! Reference source not found. and, respectively. the Matlab program at data rates of Gbps, 6.25 Gbps and 1 Gbps. The tap number of SSF is varied to determine the optimum number. The performance of SSF and FSF is compared. A. Symbol-spaced FIR Filter Figure 6 shows the pulse response of the channel at different data rates. The optimum tap coefficients of SSF are obtained at the above data rates for the post-tap number, varied from 1 to 1 (the total tap number is from 2 to 11). The far-end eye diagrams are drawn after applying the obtained SSF preemphasis to the link. Pulse response of channel (volt) Gbps 6.25Gbps 1Gbps 3.125Gbps 6.25Gbps 1Gbps Figure 5. Error! Reference source not found.matlab program flow chart: Tap-coefficients calculator and backplane link simulator As shown Figure 5, the channel impulse response is first obtained by applying the inverse fast Fourier transform (IFFT) to the measured channel differential, S-parameter transfer function SDD21. Next, training data (from a pseudorandom source) is convolved with the impulse response to obtain the distorted data at the far end of the channel. The distorted data and the error signal, which is the difference between the delayed training data and FIR filter output, go into the least-mean-square (LMS) convergence engine. The LMS algorithm coefficient updating process follows the equation: C( n + 1 ) = C( n) + μ u e (2) where C is the tap coefficient, is the step size, u is the distorted signal, and e is the error signal. As the algorithm convergences, the tap coefficients reach their optimum values. The obtained optimum tap coefficients are then applied to the transmitter FIR filter in the Matlab link simulator. The spectrum of data bit sequence, channel, and transfer functions of the FIR filter are first multiplied in the frequency domain, and then converted to the time domain using IFFT. Finally, the time domain response is used to obtain the far-end eye diagram. IV. CASE STUDIES AND CORRELATION The 34-inch FR4 backplane discussed above is used as the transmission channel. SSF and FSF are optimized through Tim e (sec) x 1-9 Figure 6. Channel pulse responses at different data rates Tim e (sec) x x x x x x 1-1 (c) Figure 5. Comparison of far-end eye diagrams without and with SSF pre-emphasis: Gbps; 6.25 Gbps; and (c) 1 Gbps.
4 The selection of the optimum tap number is discussed separately [4]. In general, the optimum tap number is close to the least number of symbol-spaced points that cover the greatest part of the tail of the pulse response. For the 34-inch FR4 backplane used here, four post-taps were used for Gbps and 6.25 Gbps, and five post-taps were used for 1 Gbps. SSF pre-emphasis, with the obtained optimum tap number and coefficients, is applied to the link at different data rates. Far-end eye diagrams, with and without SSF preemphasis, are compared in Figure 5. The effectiveness of SSF pre-emphasis can be clearly observed. A CML transmitter with 2-tap FIR pre-emphasis has been designed in.18-µm CMOS technology. This transmitter is then used to drive the 34-inch backplane with the optimized tap-coefficients obtained from the developed Matlab program. ADS is used as the transistor-level simulator due to its capability of simulating S-parameters in transient. The far-end eye-diagrams simulated using the Matlab program and ADS simulator are plotted in Figure 6 and, respectively. Comparing the horizontal and vertical eyeopenings, a reasonably good correlation can be observed between these two link simulations. B. Fractionally-spaced FIR Filter The performance of SSF is limited by aliasing, as a result of sampling at 1/T. SSF cannot reliably compensate for channel impairments beyond the Nyquist frequency 1/2T. FSF samples at a fraction of T, and the pre-emphasis is defined beyond the 1/2T frequency point. It is expected that FSF preemphasis can perform better than SSF. Three cases are studied in the following example: 3-tap T-spaced FIR (2T span), 3-tap T/2-spaced FIR (1T span), and 5-tap T/2-spaced FIR (2T span). The performance comparison at different data rates is shown in Table 1. The eye opening of the 3-tap FSF is worse than that of the 3- tap SSF because the 3-tap FSF only covers half the time span of the 3-tap SSF. FSF, however, always performs better than SSF if the same time span is covered. The 5-tap FSF shows larger horizontal eye openings than the 3-tap SSF for all three data rates. For the backplane channel studied here, the performance gain of T/2 FSF over SSF is not significant. Further improvement can be achieved with FSF preemphasis by reducing the delay D to a smaller fraction of T. The selection of FSF vs. SSF is channel-dependent and requires a trade-off between performance and implementation complexity. Table 1. Horizontal (in unit intervals) and vertical (in volts) eye openings for SSF vs. FSF pre-emphasis Data rate 3-tap SSF 3-tap FSF 5-tap FSF [UI] [V] [UI] [V] [UI] [V] Gbps Gbps Gbps Figure Gbps data eye-diagrams at the far-end of 34- inch backplane without and with FIR pre-emphasis: Matlab simulation and ADS transistor-level simulation V. CONCLUSION One backplane channel has been thoroughly analyzed in the frequency and time domains. It was found that the group delay distortion is a major ISI contributor in addition to amplitude attenuation. Using the Matlab program, we studied the FIR filter pre-emphasis for backplane channel equalization and, as expected, FSF performs better than SSF, if the same time span is covered. Results from Matlab simulation are close to these obtained from the ADS simulation that included transistor-level FIR pre-emphasis. The Matlab program can be used to optimize FIR preemphasis and provide design guidelines for given backplane channels. C. Simulation Correlation
5 REFERENCES [1] J. Zerbe, et al. Equalization and clock recovery for a 2.5-1Gbs 2-PAM/4-PAM backplane transceiver cell, ISSCC Digest of Technical Papers, paper 4.6, 23. [2] J.T. Stonick, Gu-Yeon Wei, J.L. Sonntag, D.K. Weinlader, An adaptive PAM-4 5-Gb/s backplane transceiver in.25-um CMOS, IEEE J. Solid-State Circuits, vol.38, pp , March 23. [3] OIF , Common Electrical Interface (CEI) electrical and jitter interoperability agreements for 6+ and 11+ Gbps I/O, October 23. [4] M. Li, S. Wang, Y. Tao, and T. Kwasniewski, FIR filter optimization as pre-emphasis of high-speed backplane data transmission, International Conference of Communications, Circuits and Systems (ICCCAS), Chengdu, China, June 2729, 24.
A 10Gbps Analog Adaptive Equalizer and Pulse Shaping Circuit for Backplane Interface
Proceedings of the 5th WSEAS Int. Conf. on CIRCUITS, SYSTEMS, ELECTRONICS, CONTROL & SIGNAL PROCESSING, Dallas, USA, November 1-3, 2006 225 A 10Gbps Analog Adaptive Equalizer and Pulse Shaping Circuit
More information56+ Gb/s Serial Transmission using Duobinary Signaling
56+ Gb/s Serial Transmission using Duobinary Signaling Jan De Geest Senior Staff R&D Signal Integrity Engineer, FCI Timothy De Keulenaer Doctoral Researcher, Ghent University, INTEC-IMEC Introduction Motivation
More informationTo learn fundamentals of high speed I/O link equalization techniques.
1 ECEN 720 High-Speed Links: Circuits and Systems Lab5 Equalization Circuits Objective To learn fundamentals of high speed I/O link equalization techniques. Introduction An ideal cable could propagate
More informationTo learn S-parameters, eye diagram, ISI, modulation techniques and their simulations in MATLAB and Cadence.
1 ECEN 720 High-Speed Links: Circuits and Systems Lab2- Channel Models Objective To learn S-parameters, eye diagram, ISI, modulation techniques and their simulations in MATLAB and Cadence. Introduction
More informationA Two-Tone Test Method for Continuous-Time Adaptive Equalizers
Two-Tone Test Method for Continuous-Time daptive Equalizers Dongwoo Hong*, Shadi Saberi**, Kwang-Ting (Tim) Cheng*, C. Patrick Yue* University of California, Santa Barbara, C, US* Carnegie Mellon University,
More informationA PROGRAMMABLE PRE-CURSOR ISI EQUALIZATION CIRCUIT FOR HIGH-SPEED SERIAL LINK OVER HIGHLY LOSSY BACKPLANE CHANNEL
A PROGRAMMABLE PRE-CUROR II EQUALIZATION CIRCUIT FOR HIGH-PEED ERIAL LINK OVER HIGHLY LOY BACKPLANE CHANNEL Bo Wang, Dianyong Chen, Bangli Liang, Jinguang Jiang 2 and Tad Kwasniewski DOE, Carleton University,
More informationA 5-Gb/s 156-mW Transceiver with FFE/Analog Equalizer in 90-nm CMOS Technology Wang Xinghua a, Wang Zhengchen b, Gui Xiaoyan c,
4th International Conference on Computer, Mechatronics, Control and Electronic Engineering (ICCMCEE 2015) A 5-Gb/s 156-mW Transceiver with FFE/Analog Equalizer in 90-nm CMOS Technology Wang Xinghua a,
More information06-011r0 Towards a SAS-2 Physical Layer Specification. Kevin Witt 11/30/2005
06-011r0 Towards a SAS-2 Physical Layer Specification Kevin Witt 11/30/2005 Physical Layer Working Group Goal Draft a Specification which will: 1. Meet the System Designers application requirements, 2.
More informationTo learn S-parameter, eye diagram, ISI, modulation techniques and to simulate in Matlab and Cadence.
1 ECEN 689 High-Speed Links Circuits and Systems Lab2- Channel Models Objective To learn S-parameter, eye diagram, ISI, modulation techniques and to simulate in Matlab and Cadence. Introduction S-parameters
More informationHigh-Speed Circuits and Systems Laboratory B.M.Yu. High-Speed Circuits and Systems Lab.
High-Speed Circuits and Systems Laboratory B.M.Yu 1 Content 1. Introduction 2. Pre-emphasis 1. Amplitude pre-emphasis 2. Phase pre-emphasis 3. Circuit implantation 4. Result 5. Conclusion 2 Introduction
More informationH19- Reliable Serial Backplane Data Transmission at 10 Gb/s. January 30, 2002 Slide 1 of 24
H19- Reliable Serial Backplane Data Transmission at 10 Gb/s Slide 1 of 24 Evolution of the Interconnect F r e q u e n c y A c t i v e Channel Architecture Connectors Transmission Media Loss Properties
More informationSHF Communication Technologies AG. Wilhelm-von-Siemens-Str. 23D Berlin Germany. Phone Fax
SHF Communication Technologies AG -- Wilhelm-von-Siemens-Str. 23D 12277 Berlin Germany Phone +49 30 772051-0 Fax ++49 30 7531078 E-Mail: sales@shf.de Web: http://www.shf.de Datasheet SHF 12125 B Compact
More informationPWM pre-emphasis. Chapter Introduction
Chapter 4 PWM pre-emphasis 4.1. Introduction To compensate for channel losses, transmitter pre-emphasis or receiver equalization can be applied [Farjad-Rad], [Lee], [Kudoh], [Gai], [Dally-1]. Receiver
More informationECEN720: High-Speed Links Circuits and Systems Spring 2017
ECEN72: High-Speed Links Circuits and Systems Spring 217 Lecture 4: Channel Pulse Model & Modulation Schemes Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements & Agenda Lab 1 Report
More information100 Gb/s: The High Speed Connectivity Race is On
100 Gb/s: The High Speed Connectivity Race is On Cathy Liu SerDes Architect, LSI Corporation Harold Gomard SerDes Product Manager, LSI Corporation October 6, 2010 Agenda 100 Gb/s Ethernet evolution SoC
More information5Gbps Serial Link Transmitter with Pre-emphasis
Gbps Serial Link Transmitter with Pre-emphasis Chih-Hsien Lin, Chung-Hong Wang and Shyh-Jye Jou Department of Electrical Engineering,National Central University,Chung-Li, Taiwan R.O.C. Abstract- High-speed
More informationECEN720: High-Speed Links Circuits and Systems Spring 2017
ECEN720: High-Speed Links Circuits and Systems Spring 207 Lecture 8: RX FIR, CTLE, DFE, & Adaptive Eq. Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Lab 4 Report and Prelab
More informationDesignCon IBIS-AMI Modeling and Simulation of 56G PAM4 Link Systems. Hongtao Zhang, Xilinx Inc.
DesignCon 2015 IBIS-AMI Modeling and Simulation of 56G PAM4 Link Systems Hongtao Zhang, Xilinx Inc. hongtao@xilinx.com Fangyi Rao, Keysight Technologies fangyi_rao@keysight.com Xiaoqing Dong, Huawei Technologies
More informationStatistical Link Modeling
April 26, 2018 Wendem Beyene UIUC ECE 546 Statistical Link Modeling Review of Basic Techniques What is a High-Speed Link? 1011...001 TX Channel RX 1011...001 Clock Clock Three basic building blocks: Transmitter,
More informationSerial Data Transmission
Serial Data Transmission Dr. José Ernesto Rayas Sánchez 1 Outline Baseband serial transmission Line Codes Bandwidth of serial data streams Block codes Serialization Intersymbol Interference (ISI) Jitter
More informationHigh-Speed Link Tuning Using Signal Conditioning Circuitry in Stratix V Transceivers
High-Speed Link Tuning Using Signal Conditioning Circuitry in Stratix V Transceivers AN678 Subscribe This application note provides a set of guidelines to run error free across backplanes at high-speed
More informationECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012
ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 0 Lecture 8: RX FIR, CTLE, & DFE Equalization Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Exam is
More informationEqualize 10Gbase-CX4 and Copper InfiniBand Links with the MAX3983
Design Note: HFDN-27.0 Rev.1; 04/08 Equalize 10Gbase-CX4 and Copper InfiniBand Links with the MAX3983 AAILABLE Equalize 10Gbase-CX4 and Copper InfiniBand Links with the MAX3983 1 Introduction This discussion
More informationADAPTIVE DECISION FEEDBACK EQUALIZATION FOR MULTI-Gbps DATA LINKS
ADAPTIVE DECISION FEEDBACK EQUALIZATION FOR MULTI-Gbps DATA LINKS by Alaa R. Abdullah Bacelor of Science, University of Technology, Baghdad, Iraq, 1989 Master of Science, Ryerson University, Toronto, Canada,
More informationBackplane Applications with 28 nm FPGAs
Backplane Applications with 28 nm FPGAs WP-01185-1.1 White Paper This white paper covers the challenges of backplane applications and how to use the features of Altera Stratix V GX and GS FPGAs to address
More informationBlind Adaptation of a Decision Feedback Equalizer for use in a logbps Serial Link
Blind Adaptation of a Decision Feedback Equalizer for use in a logbps Serial Link By Charles E. Berndt B.Eng., Carleton University A Thesis Submitted to the Faculty of Graduate Studies and Research in
More informationISSCC 2003 / SESSION 4 / CLOCK RECOVERY AND BACKPLANE TRANSCEIVERS / PAPER 4.3
ISSCC 2003 / SESSION 4 / CLOCK RECOVERY AND BACKPLANE TRANSCEIVERS / PAPER 4.3 4.3 A Second-Order Semi-Digital Clock Recovery Circuit Based on Injection Locking M.-J. Edward Lee 1, William J. Dally 1,2,
More informationA 0.18µm CMOS Gb/s Digitally Controlled Adaptive Line Equalizer with Feed-Forward Swing Control for Backplane Serial Link
1 A 0.18µm CMOS 3.125-Gb/s Digitally Controlled Adaptive Line Equalizer with Feed-Forward Swing Control for Backplane Serial Link Ki-Hyuk Lee, Jae-Wook Lee nonmembers and Woo-Young Choi regular member
More informationCOMPARISON OF CHANNEL ESTIMATION AND EQUALIZATION TECHNIQUES FOR OFDM SYSTEMS
COMPARISON OF CHANNEL ESTIMATION AND EQUALIZATION TECHNIQUES FOR OFDM SYSTEMS Sanjana T and Suma M N Department of Electronics and communication, BMS College of Engineering, Bangalore, India ABSTRACT In
More informationVLSI Broadband Communication Circuits
Miscellaneous topics Department of Electrical Engineering Indian Institute of Technology, Madras Chennai, 600036, India 16 Nov. 2007 Outline Optimal equalizers LMS adaptation Validity of PLL linear model
More informationECE 546 Introduction
ECE 546 Introduction Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine 1 Future System Needs and Functions Auto Digital
More informationSpecifying a Channel Through Impulse Response. Charles Moore July 9, 2004
Specifying a Channel Through Impulse Response Charles Moore July 9, 2004 Current Practice Current practice specifies channels in terms of S parameters. This is useful since S parameters are relatively
More informationAs presented at Euro DesignCon 2004 Channel Compliance Testing Utilizing Novel Statistical Eye Methodology
T10/05-198r0 As presented at Euro DesignCon 2004 Channel Compliance Testing Utilizing Novel Statistical Eye Methodology Anthony Sanders Infineon Technologies Mike Resso John D Ambrosia Technologies Agilent
More informationAdaptive Analog Transversal Equalizers for High-Speed Serial Links
University of Pavia Department of Electronic Engineering Ph.D. Thesis in Microelectronics XXVIII Cycle Adaptive Analog Transversal Equalizers for High-Speed Serial Links Supervisor: Prof. Andrea Mazzanti
More informationComparison of Time Domain and Statistical IBIS-AMI Analyses Mike LaBonte SiSoft
Comparison of Time Domain and Statistical IBIS-AMI Analyses Mike LaBonte SiSoft Asian IBIS Summit 2017 Taipei, ROC November 15, 2017 9 Combinations of TX and RX Model Types AMI file has: GetWave_Exists
More informationComparison of Time Domain and Statistical IBIS-AMI Analyses
Comparison of Time Domain and Statistical IBIS-AMI Analyses Mike LaBonte SiSoft Asian IBIS Summit 2017 Shanghai, PRC November 13, 2017 9 Combinations of TX and RX Model Types AMI file has: GetWave_Exists
More informationUltra-high-speed Interconnect Technology for Processor Communication
Ultra-high-speed Interconnect Technology for Processor Communication Yoshiyasu Doi Samir Parikh Yuki Ogata Yoichi Koyanagi In order to improve the performance of storage systems and servers that make up
More informationSource Coding and Pre-emphasis for Double-Edged Pulse width Modulation Serial Communication
Source Coding and Pre-emphasis for Double-Edged Pulse width Modulation Serial Communication Abstract: Double-edged pulse width modulation (DPWM) is less sensitive to frequency-dependent losses in electrical
More informationBackchannel Modeling and Simulation Using Recent Enhancements to the IBIS Standard
Backchannel Modeling and Simulation Using Recent Enhancements to the IBIS Standard By Ken Willis, Product Engineering Architect; Ambrish Varma, Senior Principal Software Engineer; Dr. Kumar Keshavan, Senior
More information3Gb/s CMOS Adaptive Equalizer for Backplane Serial Links
3Gb/s CMOS Adaptive Equalizer for Backplane Serial Links JaeWook Lee and WooYoung Choi Department of Electrical and Electronic Engineering, Yonsei University patima@tera.yonsei.ac.kr Abstract A new line
More informationDelft University of Technology Faculty of Electrical Engineering, Mathematics and Computer Science
Delft University of Technology Faculty of Electrical Engineering, Mathematics and Computer Science Analysis and Design of Decision Feedback Equalizers for bitrates of 10Gbps and Beyond in Submicron CMOS
More informationDifferential Signal and Common Mode Signal in Time Domain
Differential Signal and Common Mode Signal in Time Domain Most of multi-gbps IO technologies use differential signaling, and their typical signal path impedance is ohm differential. Two 5ohm cables, however,
More informationELT Receiver Architectures and Signal Processing Fall Mandatory homework exercises
ELT-44006 Receiver Architectures and Signal Processing Fall 2014 1 Mandatory homework exercises - Individual solutions to be returned to Markku Renfors by email or in paper format. - Solutions are expected
More informationEE290C Spring Lecture 5: Equalization Techniques. Elad Alon Dept. of EECS 9" FR4 26" FR4. 9" FR4, via stub.
EE29C Spring 211 Lecture 5: Equalization Techniques Elad Alon Dept. of EECS Link Channels Attenuation [db] -1-2 -3-4 -5 9" FR4, via stub 9" FR4 26" FR4-6 26" FR4, via stub 2 4 6 8 1 frequency [GHz] EE29C
More informationElectronic Dispersion Compensation of 40-Gb/s Multimode Fiber Links Using IIR Equalization
Electronic Dispersion Compensation of 4-Gb/s Multimode Fiber Links Using IIR Equalization George Ng & Anthony Chan Carusone Dept. of Electrical & Computer Engineering University of Toronto Canada Transmitting
More informationTime-Domain Pre-Distortion Technique Using Raised Cosine Shaping for High-Speed Serial Signaling B. Ševčík, L. Brančík 1
Ročník 20 Číslo IV Time-Domain Pre-Distortion Technique Using Raised Cosine Shaping for High-Speed Serial Signaling B. Ševčík, L. Brančík Department of Radio Electronics, Faculty of Electrical Engineering,
More informationA10-Gb/slow-power adaptive continuous-time linear equalizer using asynchronous under-sampling histogram
LETTER IEICE Electronics Express, Vol.10, No.4, 1 8 A10-Gb/slow-power adaptive continuous-time linear equalizer using asynchronous under-sampling histogram Wang-Soo Kim and Woo-Young Choi a) Department
More informationMicram DAC10001 and DAC GS/s Digital to Analog Converter System. Data Sheet
Micram DAC10001 and DAC10002 100 GS/s Digital to Analog Converter Data Sheet 100 GS/s Sample rate per channel Single and Dual Channel s 35 GHz Analog Bandwidth (typical) Very fast (
More informationEQUALIZATION of high-speed serial links has evolved
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 6, JUNE 2006 1391 Phase and Amplitude Pre-Emphasis Techniques for Low-Power Serial Links James F. Buckwalter, Member, IEEE, Mounir Meghelli, Daniel J.
More informationLSI and Circuit Technologies for the SX-8 Supercomputer
LSI and Circuit Technologies for the SX-8 Supercomputer By Jun INASAKA,* Toshio TANAHASHI,* Hideaki KOBAYASHI,* Toshihiro KATOH,* Mikihiro KAJITA* and Naoya NAKAYAMA This paper describes the LSI and circuit
More informationECEN 720 High-Speed Links: Circuits and Systems
1 ECEN 720 High-Speed Links: Circuits and Systems Lab4 Receiver Circuits Objective To learn fundamentals of receiver circuits. Introduction Receivers are used to recover the data stream transmitted by
More informationSIGNALS AND SYSTEMS LABORATORY 13: Digital Communication
SIGNALS AND SYSTEMS LABORATORY 13: Digital Communication INTRODUCTION Digital Communication refers to the transmission of binary, or digital, information over analog channels. In this laboratory you will
More informationOIF CEI 6G LR OVERVIEW
OIF CEI 6G LR OVERVIEW Graeme Boyd, Yuriy Greshishchev T10 SAS-2 WG meeting, Houston, 25-26 May 2005 www.pmc-sierra.com 1 Outline! Why CEI-6G LR is of Interest to SAS-2?! CEI-6G- LR Specification Methodology!
More informationECEN 720 High-Speed Links Circuits and Systems
1 ECEN 720 High-Speed Links Circuits and Systems Lab4 Receiver Circuits Objective To learn fundamentals of receiver circuits. Introduction Receivers are used to recover the data stream transmitted by transmitters.
More informationValidation & Analysis of Complex Serial Bus Link Models
Validation & Analysis of Complex Serial Bus Link Models Version 1.0 John Pickerd, Tektronix, Inc John.J.Pickerd@Tek.com 503-627-5122 Kan Tan, Tektronix, Inc Kan.Tan@Tektronix.com 503-627-2049 Abstract
More informationPerformance of Wideband Mobile Channel with Perfect Synchronism BPSK vs QPSK DS-CDMA
Performance of Wideband Mobile Channel with Perfect Synchronism BPSK vs QPSK DS-CDMA By Hamed D. AlSharari College of Engineering, Aljouf University, Sakaka, Aljouf 2014, Kingdom of Saudi Arabia, hamed_100@hotmail.com
More information06-496r3 SAS-2 Electrical Specification Proposal. Kevin Witt SAS-2 Phy Working Group 1/16/07
06-496r3 SAS-2 Electrical Specification Proposal Kevin Witt SAS-2 Phy Working Group 1/16/07 Overview Motivation Multiple SAS-2 Test Chips Have Been Built and Tested, SAS-2 Product Designs have Started
More informationT10/05-428r0. From: Yuriy M. Greshishchev, PMC-Sierra Inc. Date: 06 November 2005
T10/05-428r0 SAS-2 channels analyses and suggestion for physical link requirements To: T10 Technical Committee From: Yuriy M. Greshishchev, PMC-Sierra Inc. (yuriy_greshishchev@pmc-sierra.com) Date: 06
More informationKeysight Technologies Using Equalization Techniques on Your Ininiium 90000A Series Oscilloscope. Application Note
Keysight Technologies Using Equalization Techniques on Your Ininiium 90000A Series Oscilloscope Application Note Introduction This application note provides an overview of feed-forward and decision feedback
More informationDepartment of Electronics and Communication Engineering 1
UNIT I SAMPLING AND QUANTIZATION Pulse Modulation 1. Explain in detail the generation of PWM and PPM signals (16) (M/J 2011) 2. Explain in detail the concept of PWM and PAM (16) (N/D 2012) 3. What is the
More informationExperiment 2 Effects of Filtering
Experiment 2 Effects of Filtering INTRODUCTION This experiment demonstrates the relationship between the time and frequency domains. A basic rule of thumb is that the wider the bandwidth allowed for the
More informationBaseline Proposal for 100G Backplane Specification Using PAM2. Mike Dudek QLogic Mike Li Altera Feb 25, 2012
Baseline Proposal for 100G Backplane Specification Using PAM2 Mike Dudek QLogic Mike Li Altera Feb 25, 2012 1 2 Baseline Proposal for 100G PAM2 Backplane Specification : dudek_01_0312 Supporters Stephen
More informationBeta and Epsilon Point Update. Adam Healey Mark Marlett August 8, 2007
Beta and Epsilon Point Update Adam Healey Mark Marlett August 8, 2007 Contributors and Supporters Dean Wallace, QLogic Pravin Patel, IBM Eric Kvamme, LSI Tae-Kwang Jeon, LSI Bill Fulmer, LSI Max Olsen,
More informationHigh-speed Integrated Circuits for Silicon Photonics
High-speed Integrated Circuits for Silicon Photonics Institute of Semiconductor, CAS 2017.7 Outline Introduction High-Speed Signaling Fundamentals TX Design Techniques RX Design Techniques Design Examples
More informationCircuit Techniques for High-Speed Serial and Backplane Signaling Marcus Henricus van Ierssel
Circuit Techniques for High-Speed Serial and Backplane Signaling Marcus Henricus van Ierssel A thesis submitted in conformity with the requirements for the degree of Doctor of Philosophy, Department of
More informationSignal Processing Techniques for Software Radio
Signal Processing Techniques for Software Radio Behrouz Farhang-Boroujeny Department of Electrical and Computer Engineering University of Utah c 2007, Behrouz Farhang-Boroujeny, ECE Department, University
More informationModule 12 : System Degradation and Power Penalty
Module 12 : System Degradation and Power Penalty Lecture : System Degradation and Power Penalty Objectives In this lecture you will learn the following Degradation during Propagation Modal Noise Dispersion
More informationBlind Equalization Using Constant Modulus Algorithm and Multi-Modulus Algorithm in Wireless Communication Systems
Blind Equalization Using Constant Modulus Algorithm and Multi-Modulus Algorithm in Wireless Communication Systems Ram Babu. T Electronics and Communication Department Rao and Naidu Engineering College
More information6.976 High Speed Communication Circuits and Systems Lecture 21 MSK Modulation and Clock and Data Recovery Circuits
6.976 High Speed Communication Circuits and Systems Lecture 21 MSK Modulation and Clock and Data Recovery Circuits Michael Perrott Massachusetts Institute of Technology Copyright 2003 by Michael H. Perrott
More informationConsiderations in High-Speed High Performance Die-Package-Board Co-Design. Jenny Jiang Altera Packaging Department October 2014
Considerations in High-Speed High Performance Die-Package-Board Co-Design Jenny Jiang Altera Packaging Department October 2014 Why Co-Design? Complex Multi-Layer BGA Package Horizontal and vertical design
More informationBasic Concepts in Data Transmission
Basic Concepts in Data Transmission EE450: Introduction to Computer Networks Professor A. Zahid A.Zahid-EE450 1 Data and Signals Data is an entity that convey information Analog Continuous values within
More informationData and Computer Communications Chapter 3 Data Transmission
Data and Computer Communications Chapter 3 Data Transmission Eighth Edition by William Stallings Transmission Terminology data transmission occurs between a transmitter & receiver via some medium guided
More informationA 5-8 Gb/s Low-Power Transmitter with 2-Tap Pre-Emphasis Based on Toggling Serialization
A 5-8 Gb/s Low-Power Transmitter with 2-Tap Pre-Emphasis Based on Toggling Serialization Sung-Geun Kim, Tongsung Kim, Dae-Hyun Kwon, and Woo-Young Choi Department of Electrical and Electronic Engineering,
More informationESE531 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Signal Processing
University of Pennsylvania Department of Electrical and System Engineering Digital Signal Processing ESE531, Spring 2017 Final Project: Audio Equalization Wednesday, Apr. 5 Due: Tuesday, April 25th, 11:59pm
More informationPlastic straw: future of high-speed signaling
Supplementary Information for Plastic straw: future of high-speed signaling Ha Il Song, Huxian Jin, and Hyeon-Min Bae * Korea Advanced Institute of Science and Technology (KAIST), Department of Electrical
More informationTerminology (1) Chapter 3. Terminology (3) Terminology (2) Transmitter Receiver Medium. Data Transmission. Direct link. Point-to-point.
Terminology (1) Chapter 3 Data Transmission Transmitter Receiver Medium Guided medium e.g. twisted pair, optical fiber Unguided medium e.g. air, water, vacuum Spring 2012 03-1 Spring 2012 03-2 Terminology
More informationHigh Speed I/O 2-PAM Receiver Design. EE215E Project. Signaling and Synchronization. Submitted By
High Speed I/O 2-PAM Receiver Design EE215E Project Signaling and Synchronization Submitted By Amrutha Iyer Kalpana Manickavasagam Pritika Dandriyal Joseph P Mathew Problem Statement To Design a high speed
More informationTerminology (1) Chapter 3. Terminology (3) Terminology (2) Transmitter Receiver Medium. Data Transmission. Simplex. Direct link.
Chapter 3 Data Transmission Terminology (1) Transmitter Receiver Medium Guided medium e.g. twisted pair, optical fiber Unguided medium e.g. air, water, vacuum Corneliu Zaharia 2 Corneliu Zaharia Terminology
More informationEE3723 : Digital Communications
EE3723 : Digital Communications Week 11, 12: Inter Symbol Interference (ISI) Nyquist Criteria for ISI Pulse Shaping and Raised-Cosine Filter Eye Pattern Equalization (On Board) 01-Jun-15 Muhammad Ali Jinnah
More informationLSI and Circuit Technologies of the SX-9
TANAHASHI Toshio, TSUCHIDA Junichi, MATSUZAWA Hajime NIWA Kenji, SATOH Tatsuo, KATAGIRI Masaru Abstract This paper outlines the LSI and circuit technologies of the SX-9 as well as their inspection technologies.
More informationTo learn statistical bit-error-rate (BER) simulation, BER link noise budgeting and using ADS to model high speed I/O link circuits
1 ECEN 720 High-Speed Links: Circuits and Systems Lab6 Link Modeling with ADS Objective To learn statistical bit-error-rate (BER) simulation, BER link noise budgeting and using ADS to model high speed
More informationFundamentals of Digital Communication
Fundamentals of Digital Communication Network Infrastructures A.A. 2017/18 Digital communication system Analog Digital Input Signal Analog/ Digital Low Pass Filter Sampler Quantizer Source Encoder Channel
More informationReconfigurable Equalization for 10-Gb/sec Serial Data Links
Reconfigurable Equalization for 10-Gb/sec Serial Data Links in a 0.18-µm CMOS Technology A Dissertation Presented to The Academic Faculty by Franklin Bien In Partial Fulfillment of the Requirements for
More informationPhase Modulator for Higher Order Dispersion Compensation in Optical OFDM System
Phase Modulator for Higher Order Dispersion Compensation in Optical OFDM System Manpreet Singh 1, Karamjit Kaur 2 Student, University College of Engineering, Punjabi University, Patiala, India 1. Assistant
More informationPerformance Analysis Of Hybrid Optical OFDM System With High Order Dispersion Compensation
Performance Analysis Of Hybrid Optical OFDM System With High Order Dispersion Compensation Manpreet Singh Student, University College of Engineering, Punjabi University, Patiala, India. Abstract Orthogonal
More informationThe Practical Limitations of S Parameter Measurements and the Impact on Time- Domain Simulations of High Speed Interconnects
The Practical Limitations of S Parameter Measurements and the Impact on Time- Domain Simulations of High Speed Interconnects Dennis Poulin Anritsu Company Slide 1 Outline PSU Signal Integrity Symposium
More informationEC 554 Data Communications
EC 554 Data Communications Mohamed Khedr http://webmail. webmail.aast.edu/~khedraast.edu/~khedr Syllabus Tentatively Week 1 Week 2 Week 3 Week 4 Week 5 Week 6 Week 7 Week 8 Week 9 Week 10 Week 11 Week
More informationCrosstalk-Aware Transmitter Pulse-Shaping for Parallel Chip-to-Chip Links. Mike Bichan
Crosstalk-Aware Transmitter Pulse-Shaping for Parallel Chip-to-Chip Links by Mike Bichan A thesis submitted in conformity with the requirements for the degree of Master of Applied Science Graduate Department
More informationIN HIGH-SPEED wireline transceivers, a (DFE) is often
326 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 59, NO. 6, JUNE 2012 Decision Feedback Equalizer Architectures With Multiple Continuous-Time Infinite Impulse Response Filters Shayan
More information/$ IEEE
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 53, NO. 11, NOVEMBER 2006 1205 A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for
More informationChapter 3. Data Transmission
Chapter 3 Data Transmission Reading Materials Data and Computer Communications, William Stallings Terminology (1) Transmitter Receiver Medium Guided medium (e.g. twisted pair, optical fiber) Unguided medium
More informationText Book: Simon Haykin & Michael Moher,
Qassim University College of Engineering Electrical Engineering Department Electronics and Communications Course: EE322 Digital Communications Prerequisite: EE320 Text Book: Simon Haykin & Michael Moher,
More informationSC - Single carrier systems One carrier carries data stream
Digital modulation SC - Single carrier systems One carrier carries data stream MC - Multi-carrier systems Many carriers are used for data transmission. Data stream is divided into sub-streams and each
More informationDecision Feedback Equalizer A Nobel Approch and a Comparitive Study with Decision Directed Equalizer
International Journal of Innovative Research in Electronics and Communications (IJIREC) Volume, Issue 2, May 24, PP 4-46 ISSN 2349-442 (Print) & ISSN 2349-45 (Online) www.arcjournals.org Decision Feedback
More informationPrinciples of Baseband Digital Data Transmission
Principles of Baseband Digital Data Transmission Prof. Wangrok Oh Dept. of Information Communications Eng. Chungnam National University Prof. Wangrok Oh(CNU) / 3 Overview Baseband Digital Data Transmission
More informationA New Adaptive Channel Estimation for Frequency Selective Time Varying Fading OFDM Channels
A New Adaptive Channel Estimation for Frequency Selective Time Varying Fading OFDM Channels Wessam M. Afifi, Hassan M. Elkamchouchi Abstract In this paper a new algorithm for adaptive dynamic channel estimation
More informationEE5713 : Advanced Digital Communications
EE573 : Advanced Digital Communications Week 4, 5: Inter Symbol Interference (ISI) Nyquist Criteria for ISI Pulse Shaping and Raised-Cosine Filter Eye Pattern Error Performance Degradation (On Board) Demodulation
More informationMulti-gigabit signaling with CMOS
Multi-gigabit signaling with CMOS William J. Dally - Massachusetts Institute of Technology John Poulton - University of North Carolina @ Chapel Hill Steve Tell - University of North Carolina @ Chapel Hill
More informationA 24Gb/s Software Programmable Multi-Channel Transmitter
A 24Gb/s Software Programmable Multi-Channel Transmitter A. Amirkhany 1, A. Abbasfar 2, J. Savoj 2, M. Jeeradit 2, B. Garlepp 2, V. Stojanovic 2,3, M. Horowitz 1,2 1 Stanford University 2 Rambus Inc 3
More informationQAM-Based 1000BASE-T Transceiver
QAM-Based 1000BASE-T Transceiver Oscar Agazzi, Mehdi Hatamian, Henry Samueli Broadcom Corp. 16251 Laguna Canyon Rd. Irvine, CA 92618 714-450-8700 802.3, Irvine, CA, March 1997 Overview The FEXT problem
More information