AS DATA RATES increase, the variation in channel

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1 80 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 1, JANUARY Gb/s Source-Synchronous I/O Link With Adaptive Receiver Equalization, Offset Cancellation, and Clock De-Skew James E. Jaussi, Member, IEEE, Ganesh Balamurugan, Student Member, IEEE, David R. Johnson, Member, IEEE, Bryan Casper, Member, IEEE, Aaron Martin, Member, IEEE, Joseph Kennedy, Member, IEEE, Naresh Shanbhag, Senior Member, IEEE, and Randy Mooney, Member, IEEE Abstract A source-synchronous I/O link with adaptive receiver-side equalization has been implemented in m bulk CMOS technology. The transceiver is optimized for small area (360 m 360 m) and low power (280 mw). The analog equalizer is implemented as an 8-way interleaved, 4-tap discrete-time linear filter. The equalization improved the data rate of a 102 cm backplane interconnect by 110%. On-die adaptive logic determines optimal receiver settings through comparator offset cancellation, data alignment of the transmitter and receiver, clock de-skew and setting filter coefficients for equalization. The noise-margin degradation due to statistical variation in converged coefficient values was less than 3%. Index Terms Adaptive equalizers, analog equalization, high-speed I/O, offset cancellation, transceivers, waveform capture. I. INTRODUCTION AS DATA RATES increase, the variation in channel responses becomes more pronounced and adaptive solutions are desirable to maximize link performance. PC desktop configurations have channel lengths that range from 5 to 17 cm with one socket, while server configurations range from 25 to 100 cm of channel length with sockets and connectors. Channel loss is a function of frequency, interconnect length and discontinuities which results in intersymbol interference (ISI). To accommodate many different interconnects, PC desktop and backplane topologies and configurations, we implemented an adaptive equalizer to remove the ISI and extend the maximum I/O data rate. In general, the equalizer can be implemented at the transmitter or receiver. Adaptive receiver equalization has advantages over adaptive transmit equalization. First, transmit equalization constrains the magnitude sum of the equalizer taps which reduces the cursor amplitude. Second, adaptive transmit equalization requires the receiver information be conveyed back to the transmitter [1]. The linear equalizer is implemented as an analog 4-tap discrete-time finite impulse response (DT-FIR) filter [2] [4]. The filter coefficients are determined by the on-die adaptive Manuscript received April 15, 2004; revised July 30, J. E. Jaussi, G. Balamurugan, D. R. Johnson, B. Casper, A. Martin, J. Kennedy, and R. Mooney are with Circuits Research, Intel Labs, Hillsboro, OR USA ( james.e.jaussi@intel.com). N. Shanbhag is with the University of Illinois at Urbana-Champaign, Urbana, IL USA. Digital Object Identifier /JSSC control unit (ACU) that updates the coefficients based on a modified partial zero-forcing (PZF) algorithm or a modified sign-sign least mean squares (SS-LMS) algorithm [2]. The ACU also controls transmitter and receiver data alignment, per bit clock de-skew and comparator offset cancellation. At lower data rates and higher noise-margins, the bit error ratios (BER) become very low and are therefore an ineffective metric for comparing link margin and performance. More efficient relative voltage margin comparisons between multiple links are made possible by a figure of merit called normalized estimated noise-margin (NENM). With equalization enabled, the data rate improved by a factor of 1.3 to 2.1 depending on the channel characteristics. The cost of the equalization is relatively low in terms of I/O power (280 mw at 8 Gb/s with 1.7-V supply) and area (360 m 360 m) in a m bulk CMOS technology. II. LINK ARCHITECTURE A diagram of the link architecture is shown in Fig. 1. Unidirectional unencoded non-return-to-zero (NRZ) data is transmitted in parallel with a unidirectional clock. The forwarded clock is used to eliminate the need for data coding and its associated circuit complexity, port latency and bandwidth overhead [5]. The clock is transmitted with a differential cascode current-mode driver with terminating resistances to ground [6]. The clock and data transmitter are identical circuits. The clock receiver is a delay-locked loop (DLL) used to lock the 0 clock phase to the 180 phase and produce four global phases and their complements separated by 45 [6]. These global phases are buffered and driven to each I/O cell. Local to the I/O cell, an interpolator receives the differential low swing clock phases as shown in Fig. 2. The clock phases pass through the digital coarse select that is implemented as analog pass gates. The two selected adjacent phases are applied to the differential stages with common linearized load elements [7]. The digital fine select adjusts the transconductance of each differential input stage through digitally controlled current sources to achieve a 6.4 resolution. The output of the interpolator feeds the clock to the phase generator. A phase generator produces eight phases that clock the samplers at the front-end of the filter and the current latches (I-latch). Fig. 3 shows state elements that accept low swing differential clocks, where the inputs and outputs are complementary signals. During the reset state, a state is set for both the upper and /$ IEEE

2 JAUSSI et al.: 8-Gb/s SOURCE-SYNCHRONOUS I/O LINK 81 Fig. 1. Link architecture. Fig. 2. Interpolator design. Fig. 3. Clock phase generator. lower state machines. During port operation, this state cycles continuously through the flip-flops. The timing diagram shown in Fig. 4 contains the clock and phase relationship information. The even and odd phases are generated with respect to the rising and falling clock edge, respectively. These clock phases are then applied to the FIR filter. The authors of [3] proposed an FIR filter architecture that holds the samples stationary while rotating the filter coefficients. By holding the analog samples stationary, a high signal-to-noise ratio (SNR) can be maintained [3]. This work proposes maintaining both the samples and filter coefficients stationary, thereby drastically reducing the dynamic power requirements. In order to keep both terms stationary, the filter must be interleaved by one more than the number of filter taps. The 4-tap FIR filter is interleaved by eight to allow sufficient time for samples to be acquired and transient currents to settle before the evaluation of the I-latch. Based on simulations, the proposed 8-way interleaved FIR filter with stationary samples and filter coefficients consumes less power compared with a two way-interleaved FIR filter with rotating weights. The total simulated power for the transceiver is 280 mw with a power supply of 1.7 V. The power breakdown is 46% for the transmitter and 54% for the receiver. The analog filter and clock phase generator constitutes 66% of the receiver power. Each filter tap consists of a voltage-to-current converter (VIC) and a current steering DAC (I-DAC) shown in Fig. 5. The VIC is a differential input stage where the resistance shown as R1 and R2 can be bypassed by closing switches S1 and S2. Therefore, the source degeneration can be enabled or Fig. 4. Sampling phase and latch evaluation phase timing diagram. disabled through digital control. The I-DAC is implemented with binary-weighted parallel NMOS devices. The sources of the I-DAC devices are connected to the drains of the current mirror. The drains of the I-DAC devices are connected to either the input of the I-latch or the VCC power supply. During port operation, the VIC s output current is entirely passed to the I-latch input or the VIC s output current is divided by the filter coefficient value. The I-DAC outputs from the four taps are then summed together at the input of the I-latch. Another component that sums into the I-latch is the offset current DAC (C-DAC). The C-DAC is sized as a cascode current source with the lower device designed as a binary weighted, selectable current source. A fixed upper cascode device minimizes the capacitive load at the I-latch input. The purpose of the C-DAC is to cancel unavoidable intrinsic offsets due to device mismatches

3 82 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 1, JANUARY 2005 Fig. 5. FIR filter architecture. in the I-latch, current mirror and VIC. It is also required to provide a reference offset during the adaptation process. The I-latch requires a low input impedance to maintain a small voltage swing and keep the input parasitic pole as high as possible, even though many devices from the I-DAC and C-DAC are connected to its input. The I-latch architecture is based on the current summing circuit proposed in [8], where the upper devices, M6 and M7, are forced into the linear region by M4 and M5, respectively. The linear devices provide a low impedance node for current summation. Each tap, by way of the I-DAC, multiplies the differential and common-mode current by the weight factor. Depending on the polarity of the weight coefficient, the differential summed current can decrease in magnitude. The common-mode current, however, will continue to increase per tap. The device sizes of the I-latch were sized to accommodate large variations in the common-mode current due to multiple taps with a wide range of possible tap weights. The required transversal behavior for the FIR filter operation is achieved by making adjacent clock samples with adjacent clock phases, separated by one unit interval (UI). These samples are applied to the VIC and multiplied by the I-DAC. In order to reduce the required circuitry and power requirements, the outputs of each of the VIC s are current mirrored to four different I-DACs that are associated with four independent filters. For example, when an I/O sample is acquired, it becomes the fourth, third, second and first sample for four adjacent FIR filters. Thus, the transversal behavior is implemented without requiring additional devices that load the I/O pad. Fig. 6. Adaptive receiver diagram. III. ADAPTIVE ALGORITHM The on-die ACU cancels receiver offsets, sets the transmitter and receiver bit alignment, determines the optimal clock de-skew and optimizes the channel filter coefficients to cancel ISI [9]. Fig. 6 shows the block diagram of the ACU and its interface with the analog receiver. The adaptation of the receiver is based on a training sequence, which is summarized in the simplified flowchart in Fig. 7. There are five required states to adapt the receiver, number one through five. The following paragraphs will describe the purpose of each state. State 1: During the initial offset trim phase, dominant offsets at the eight I-latch inputs are cancelled. The transmitter sends

4 JAUSSI et al.: 8-Gb/s SOURCE-SYNCHRONOUS I/O LINK 83 Fig. 8. Modified adaptor implementation. Fig. 7. Adaptive training sequence block diagram. 0 and 1 dc patterns. For each transmitted dc pattern, the C-DAC offset code is incremented until the I-latch outputs are tripped to the opposite state. The offset code results from each dc value are averaged, leaving the intrinsic offset value. By initially removing intrinsic offsets, poor sensitivities do not dominate the filter response and the risk of a suboptimum filter response is substantially reduced. State 2: The alignment phase consists of optimally aligning the received bit-stream with the expected training pattern to enable decision-directed adaptation. This state has a two step process involving coarse alignment and fine alignment. Initially 0 s are transmitted followed by 32 1 s. In the presence of channel loss, the 0 to 1 transition will be detected, albeit, late. Even though it is detected late, the location of the transition narrows the alignment window. Then, a 128 bit pseudo-random bit sequence (PRBS) is transmitted repetitively. Even in the presence of ISI induced errors and with no equalization, the training patterns can be aligned by correlating the expected pattern with the received pattern. The adaptor adjusts the variable delay multiplexer (shown in Fig. 6) until the number of detected errors reaches a minimum, indicating the patterns are aligned. State 3: The adaptation phase optimally determines the filter coefficients and offsets. Both filter and offset coefficients need to be adapted simultaneously, as input offsets are scaled by the filter coefficients before they appear at the latch input. While the eight interleaved equalizers share the same filter tap weights, the offset C-DACs are independently controlled to account for within-die mismatch. Two adaptive update equations were implemented using sign-sign least mean squares (SS-LMS) and partial zero-forcing (PZF) algorithms. To implement the SS-LMS algorithm, one of the eight filters has independently controlled coefficients. The adjacent filters are enabled to extract the sign of the received samples. Following adaptation, the filter coefficients are shared with the remaining seven filters. This modification avoids the requirement of additional samplers and comparators. All eight filters can be adapted simultaneously using the PZF algorithm implementation. Only the PZF algorithm is described in this paper. The PZF coefficient update equations are variations of those in [10] and are given by the equations shown at the bottom of the page, where is the vector of filter (offset reference) coefficients, is the desired data vector, is the current adaptation error, is the filter (offset) tap index, is the update index, is the actual transmit binary symbol and represents the adaptation polarity. and are the update step sizes for coefficients and offsets, respectively. The updates are performed in a block-based fashion by averaging over 32 bits. Use of selective updates through the indicator function, simplifies the adaptor implementation as shown in Fig. 8 by eliminating the need for a high-speed analog-digital interface. The selective update followed by averaging the results for both polarities, allows both the offset cancellation current and adaptation reference current to be realized using a single C-DAC. =

5 84 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 1, JANUARY 2005 Fig. 9. Transceiver cell plot. Fig. 10. An FIR tap receiver sensitivity at 6 GS/s. State 4: Following adaptation and while the 128 bit PRBS training pattern is still being transmitted, the noise margin for the current sampling phase is estimated by setting the C-DAC offsets to their maximum offset value and then decreasing the offset until no errors are detected. This offset code is recorded along with the sampling phase code. States 1 through 4 are then repeated for the desired number of sampling phases, controlled through the interpolator. State 5: The optimal sampling phase is selected based on the sampling phase code with the largest offset value and lowest number of detected errors. This concludes the port training process and the adaptor is disabled. The filter and offset settings are held unchanged for the duration of the port operation. The adaptation process requires approximately 20 ms to complete. While testing the chip, supply voltage and temperature were well controlled so that the equalization settlings and clock de-skew settings did not require updates. For implementations where significant environment variations exist, a subset of the adaptive algorithm can be run. For example, States 3 and 4 would scan through offset from the original optimum de-skew phase. State 5 would also run selecting the new optimum sampling phase. Depending on the gradient of environment change, the frequency of additional adaptation runs can be determined. The abbreviated adaptive sequence would require only hundreds of microseconds. IV. EXPERIMENTAL RESULTS A. Circuit Characterization A transceiver I/O cell plot is shown in Fig. 9. The chip was fabricated in m bulk CMOS technology and was flip-chip bonded into a ball-grid array package. The test board consists of two chips separated by 5 cm of FR4 and 17 cm of FR4. An additional chip is connected through a backplane with 55 cm and 102 cm FR4 links. Through measurements, we determined that when source degeneration in the VIC was enabled, the filter sensitivity was very poor since the degeneration severely limited the maximum differential current. To obtain a reasonable sensitivity, we disabled the source degeneration and the differential current increased through the differential input pair by a factor of four. With the Fig. 11. Simulated FIR tap input referred device noise breakdown. source degeneration disabled and the weight value of the I-DAC set to its maximum value, the sensitivity of one filter tap (which includes a VIC, IDAC and I-latch shown in Fig. 5) is shown in Fig. 10 as a function of input differential voltage. The measured behavior follows a Gaussian distribution with the sigma value of 6.3 mv at 6 GS/s. The Gaussian distribution suggests that the sensitivity is dominated by device noise. Taking a closer look at the device noise effects by using a time domain noise simulator, it is clear that the latch contributes a significant portion of the input referred noise as shown in Fig. 11. The I-latch devices make up 73% of the input referred noise where the input devices and current mirror yield a rather small 6% of the total input referred noise. Simulations confirm that redesigning the latch with a pre-amplification stage and optimizing the equalizing switch can dramatically improve the sensitivity. Fig. 12 shows the measured peak-to-peak input referred noise as a function of C-DAC offset code. This measurement shows the effective sensitivity due to various offsets from the C-DAC. With the peak-to-peak sensitivity curve relatively flat as a function of the C-DAC offset code, the C-DAC contributes negligible amounts of device noise for a reasonable offset range. Nonidealities that limit the accuracy of linear equalizers also hinder their effectiveness. For this architecture, the VIC is the most critical element since it sets the resolution ceiling for the

6 JAUSSI et al.: 8-Gb/s SOURCE-SYNCHRONOUS I/O LINK 85 Fig. 12. Peak-to-peak FIR tap sensitivity as a function of C-DAC offset. Fig. 13. FIR tap offset histogram, normalized to maximum transmit swing of mv (72 samples). filter design. The VIC was designed to have five bits of linearity when the source degeneration is enabled. The measured bit integral nonlinearity (INL) resolution with and without source degeneration is 5.6 bits and 3.0 bits, respectively. Because of the aforementioned I-latch sensitivity issue, source degeneration was not used. The second important linearity component is the I-DAC. The I-DAC is designed to have 6.0 bits of resolution while the measured INL was 3.3 bits. Finally, the C-DAC is designed with a 10-bit resolution and the measured INL was 6.7 bits. For both the I-DAC and C-DAC, the accuracy could be enhanced by increasing the design area to implement better layout techniques. However, due to optimizing the small footprint to be compatible for parallel port implementations, we found some accuracy was sacrificed. Fig. 13 shows the statistical offset distributions for 72 filter taps and the relative contribution of I-latch offsets, current mirror offsets and the transmitter and VIC offsets. The offset code is normalized based on a maximum transmitter differential swing of mv. The I-latch contributes the largest amount of offset. This offset is directly canceled by the C-DAC. Current mirror and VIC offsets, however, are multiplied by the weight coefficient and will change as the ACU updates the filter weights. Hence, the filter tap weights and offset coefficients need to be updated simultaneously as described in Section III. B. Adaptive Algorithm Performance and Characterization Additional states were introduced in the synthesized ACU to enable observation of the adaptation dynamics. A typical example of measured coefficient and offset evolution curves is shown in Fig. 14. Fractional step sizes can be approximated by using excess precision in the registers storing the C-DAC offsets and FIR coefficients. It can be seen that while the FIR tap weights converge to the same value regardless of the adaptation polarity, the offset C-DAC codes converge to different values since they include the polarity-dependent adaptation reference. The starting value for the C-DAC codes is the initial calculated offsets as determined in State 1 of the ACU (Section III). As shown, the starting values are significantly different for each C-DAC, i.e., the offset of each latch can be significantly different. When the average of the two adaptive polarities is calculated, the resulting offset takes into account the offset from the four VICs, four I-DACs, and one I-Latch. A typical convergence time of State 3 is less than 25 s. The statistical nature of the adaptation process implies a certain amount of random variation in the converged coefficient values. This variation degrades noise-margins above and beyond those due to channel and circuit nonidealities. Fig. 15 shows this variation for the eight I-latch offset values over 500 iterations of the adaptor. The variation is grouped into five bins. Fractional step sizes of bit of an offset code and bit of an I-DAC code were used for the offsets and filter coefficients, respectively. The filter coefficients have a tighter distribution since more error bits are available for their adaptation. As all the interleaved FIR filters share the same filter coefficients, 64 bits (half of the 128 error bits) are available for adaptation for each polarity as described in Section III. However, the offsets are independently controlled and each offset code is updated based on just eight bits of error information ( th of 64 bits). Hence, greater variation is observed in the offset codes compared to the filter tap weights. The additional degradation in noise-margins due to these statistical fluctuations is found to be less than 3% of the transmit swing. C. Link and Circuit Performance Using BERs to evaluate the operating margins with and without the equalizer enabled for a single data rate can become impractical if the BER is very low. For this reason, we have chosen to use the measured normalized estimated noise-margin (NENM). We normalize this figure of merit by the transmit swing. Using the estimated noise-margin calculated by the adaptor, the relative increase in the link margin can be determined. Fig. 16 shows the link margins over 102 cm of FR4 at 4 Gb/s with and without equalization as a function of interpolator sampling phase, demonstrating the dramatic improvement in negative link margin to positive link margin afforded by equalization. Additionally, it shows that there are a number of sampling phases that yield the peak voltage margins. During the adaptation phase, the ACU records this estimated noise-margin plot and picks the optimum sampling phase based on the maximum margins. Another method available for port characterization and to show the improvement from equalization is the pulse response capture capability. Using waveform capture methods [6], the discrete pulse responses with and without equalization are captured at 3.2 Gb/s over the 102 cm channel as shown in Fig. 17. Again, the y-axis is normalized by the dc transmitter swing. The pulse response before equalization shows pre and post-cursor ISI. After equalization, the first pre-cursor and the first and second post-cursor ISI

7 86 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 1, JANUARY 2005 Fig. 14. Evolution of four coefficients and eight offsets for 4 Gb/s transmission over 102 cm FR4. Fig. 15. Four histograms of calculated offsets during adaptation (500 iterations). Fig. 17. Comparison of a sampled pulse response with and without equalization over 102 cm FR4 at 3.2 Gb/s with one pre-cursor and two post-cursor taps. Fig. 16. Estimated noise margin with and without equalization over 102 cm FR4 at 4 Gb/s. terms are significantly reduced. The cursor value is essentially unchanged as compared to the reduced cursor value in transmit equalization [1]. The residual ISI is a result of the finite resolution and span of the FIR filter. Summarized in Fig. 18 is the measured NENM given as a function of data rate for four different FR4 channels. These measurements were made with the same link operating conditions for all data rates. The margins with and without equalization are compared. Assuming the minimum required noise-margin is 10% of the transmit signal swing, the 4-tap adaptive equalizer increases the achievable data rates by 33% for 5 cm and 17 cm FR4, 60% for 55 cm FR4 and 110% for 102 cm FR4. A 10% NENM measured at the receiver approximately equates to a BER less than. For maximum data rates, the supply was elevated from 1.5 to 1.7 V and the circuit was optimized to reach a data rate of 8 Gb/s over 5 cm FR4, 8 Gb/s over 17 cm FR4 and 5.6 Gb/s over 50 cm FR4, all with a BER of.

8 JAUSSI et al.: 8-Gb/s SOURCE-SYNCHRONOUS I/O LINK 87 Fig. 18. Measured comparison of NENM versus data rate for cm FR4 at 1.5-V VCC To quantify the maximum amount of loss that the FIR filter can equalize given the previously measured nonlinearities and sensitivities, the link is operated over a lossy interconnect. Based on the characterization of this lossy interconnect and the measured pad capacitance, the approximate channel loss is 16 db at 3.75 GHz. At this frequency, the FIR filter equalized the channel to zero NENM at 7.5 Gb/s. V. CONCLUSION An adaptive, analog 4-tap FIR filter is described. The analog circuitry requires relatively low power and small silicon area. Significant data rate improvements, up to 110%, are shown when the equalizer is enabled. The receiver equalization demonstrates several interpolator sampling phases that yield the maximum received voltage margin. The PZF and SS-LMS algorithms are modified to accommodate operating the digital adaptive control circuitry at a lower frequency than the I/O data rate to conserve power. Using an adaptive training sequence, the comparators are offset trimmed, the transmitter and receiver are logically aligned, sampling clocks are de-skewed and equalization coefficients are optimized. Multiple adaptive iterations yielded minor statistical variations in the filter coefficients and offset values. ACKNOWLEDGMENT The authors would like to thank G. Dermer and C. Roberts for design and characterization of the test boards, and H. Wilson, J. Howard, G. Ruhl, D. Klowden, K. Truong, C. Parsons and K. Ikeda for their help in building the test chip. REFERENCES [1] J. T. Stonick et al., An adaptive PAM-4 5 Gb/s backplane transceiver in 0.25-m CMOS, IEEE J. Solid-State Circuits, vol. 38, no. 3, pp , Mar [2] J. E. Jaussi et al., 8 Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation and clock de-skew, in IEEE ISSCC Dig. Tech. Papers, Feb. 2004, pp [3] T. Lee et al., A 125-MHz CMOS mixed-signal equalizer for gigabit ethernet on copper wire, Proc. IEEE CICC, pp , [4] R. Farjad-Rad et al., A 0.3-m CMOS 8 Gb/s 4-PAM serial link transceiver, IEEE J. Solid-State Circuits, vol. 35, no. 5, pp , May [5] R. Mooney et al., A 900 Mb/s bidirectional signaling scheme, IEEE J. Solid-State Circuits, vol. 30, no. 12, pp , Dec [6] B. Casper et al., 8 Gb/s SBD link with on-die waveform capture, IEEE J. Solid-State Circuits, vol. 38, no. 12, pp , Dec [7] S. Sidiropoulos et al., A semi-digital DLL with unlimited phase shift capability and MHz operation range, in IEEE ISSCC Dig. Tech. Papers, Feb. 1997, pp [8] D. Comer et al., A high-frequency CMOS current summing circuit, Analog Integrated Circuits and Signal Processing, pp , [9] G. Balamurugan et al., Receiver adaptation and system characterization of an 8 Gbps source-synchronous I/O Link using on-die circuits in 0.13 m CMOS, in VLSI Symp. Tech. Dig., Jun. 2004, pp [10] J. G. Proakis, Digital Communications, 4th ed. New York: McGraw- Hill, 2000.

9 88 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 1, JANUARY 2005 extraction architectures. James E. Jaussi (M 01) received the B.S. and M.S. degrees in electrical engineering from Brigham Young University, Provo, UT, in He is currently working toward the Ph.D. degree in electrical engineering at Oregon State University, Corvallis, OR. For the past four years, he has worked for Intel Laboratories, Hillsboro, OR. His main focus is research, design, and characterization of high-speed CMOS transceivers and mixed signal circuits, with an emphasis in receiver equalization and clock Joseph Kennedy (S 88 M 91) received the B.S. degree in electrical and computer engineering from Oregon State University, Corvallis, OR, in He is a Senior Circuits Researcher with Intel s Circuits Research Labs, Hillsboro, OR. Over the past nine years at Intel, his responsibilities have included all aspects of research and design of high-speed mixed-signal circuits and I/O systems. Prior to joining Intel, Joe spent four years with Lattice Semiconductor where he worked as a lead circuit designer developing data-path circuits and I/O interfaces for electrically programmable logic components. David R. Johnson (M 97) received the B.S degree in electrical engineering from the South Dakota School of Mines and Technology (SDSMT), Rapid City, SD, in 1996 and the M.S. degree in electrical engineering from the Oregon Graduate Institute (OGI), Beaverton, OR, in Since 1997, he has been a Design Engineer at Intel Corporation, where his research focus has been to develop integrated CMOS circuit designs for applications in high speed copper link interfaces. He is currently a strategic design lead in the Enterprise Products Group (EPG). Ganesh Balamurugan (S 99) received the Ph.D. degree from the University of Illinois at Urbana-Champaign in His research interests include adaptive equalization and noise cancellation in high-speed I/O, and noise-tolerant digital system design. Bryan Casper (S 97 M 98) received the B.S. and M.S. degrees in electrical engineering from Brigham Young University, Provo, UT. He is a Circuit Researcher with Intel Labs, Hillsboro, OR. He joined Intel in His current responsibilities include research, design, validation and characterization of high-speed mixed-signal circuits and I/O systems. Aaron Martin (M 99) received the Bachelor s and Master s degrees in electrical engineering from Brigham Young University, Provo, UT. He is a Signaling Circuits Researcher at Intel Labs, Hillsboro, OR. For the past four years, his responsibilities have included researching, developing and testing I/O circuits for PC and server platform interconnects. Naresh R. Shanbhag received the B.Tech. degree from the Indian Institute of Technology, New Delhi, India, in 1988, the M.S. degree from the Wright State University in 1990, and the Ph.D. degree from the University of Minnesota, Minneapolis, in 1993, all in electrical engineering. From 1993 to 1995, he worked at AT&T Bell Laboratories, Murray Hill, NJ, where he was the lead chip architect for AT&T s Mb/s transceiver chips over twisted-pair wiring for Asynchronous Transfer Mode (ATM)-LAN and very high-speed digital subscriber line (VDSL) chip-sets. Since August 1995, he is with the Department of Electrical and Computer Engineering, and the Coordinated Science Laboratory where he is presently a Professor. His research interests are in the design of integrated circuits and systems for broadband communications including digital signal processing and error-control coding algorithms and VLSI architectures, digital and analog integrated circuit design. He has published more than 90 journal articles/book chapters/conference publications in this area and holds three U.S. patents. He is also a co-author of the research monograph Pipelined Adaptive Digital Filters (Kluwer, 1994). Dr. Shanbhag received the 2001 IEEE TRANSACTIONS ON VLSI Best Paper Award, the 1999 IEEE Leon K. Kirchmayer Best Paper Award, the 1999 Xerox Faculty Award, the National Science Foundation CAREER Award in 1996, and the 1994 Darlington Best Paper Award from the IEEE Circuits and Systems Society. Since July 1997, he has been a Distinguished Lecturer for the IEEE Circuits and Systems Society. From and from , he served as an Associate Editor for the IEEE TRANSACTIONSON CIRCUITS AND SYSTEMS: PART II and the IEEE TRANSACTIONS ON VLSI, respectively. He has served on the technical program committees of major conferences such as the IEEE Conference on Acoustics, Speech and Signal Processing, the IEEE International Symposium on Low-Power Electronic Design, the IEEE Workshop on Signal Processing Systems, and the IEEE International Symposium on Circuits and Systems. Randy Mooney (M 88) received the M.S. degree in electrical engineering from Brigham Young University, Provo, UT. He is currently is an Intel Fellow and director of I/O research in Intel s Corporate Technology Group. He was with the Standard Products Division of Signetics Corporation in Orem, UT, from 1980 to 1992, where he developed products in Bipolar, CMOS, and BiCMOS technologies, concentrating on components for use in bus driving applications. In 1992, he joined the Supercomputer Systems Division of Intel Corporation, and worked on development of interconnect components for parallel processor communications. He was responsible for the development of signaling technology for these components, and developed a method of simultaneous bidirectional signaling that was used for the Intel Teraflops Supercomputer. His current work is focused on multi-gigabit, differential, serial stream based interfaces and pt-to-pt memory interfaces.