Statistical Link Modeling

Size: px
Start display at page:

Download "Statistical Link Modeling"

Transcription

1 April 26, 2018 Wendem Beyene UIUC ECE 546 Statistical Link Modeling Review of Basic Techniques

2 What is a High-Speed Link? TX Channel RX Clock Clock Three basic building blocks: Transmitter, Receiver, and Channel Channel accurately characterized in frequency domain Transmitter and receiver are circuit blocks and defined in time domain The transmitter and receiver require clock ticks (correlated) 2

3 Statistical Link Modeling / Analysis Statistical link analysis is not Monte Carlo analysis of high-speed link It is a technique of analytically solving of the signal amplitude probability of high-speed link Thus the method allows the result to be computed in a matter of seconds for inconceivably low BER p(t) C 0 C 1 C -1 C 2 C 3 C 4 C 5 C 6 t -1 t 0 t 1 t 2 t 3 t 4 t 5 t 6 time A convenient tool to explore link architecture and channel variations 3

4 Key Contributors to Statistical Link Modeling Bryan K. Casper, et. al, An accurate and efficient analysis method for multi-gb/s chip-to-chip signaling scheme, in Digest of Technical Papers from the IEEE Symposium on VLSI Circuits, June 2002, pp Introduced Peak Distortion Analysis to the community Vladimir Stojanovic, et. al, Modeling and analysis of high speed links, in IEEE Custom Integrated Circuits Conf. Dig. Tech. Papers, Sept 2003, pp introduced improved Jitter, Noise and CDR models Anthony Sanders, Channel Compliance Testing Utilizing Novel Statistical Eye Methodology, Euro DesignCon Wrote Wendem Beyene StatEye, the first complete link analysis tool for the public: 4

5 Today s High-Speed Links Channel Clock tracking loop vv TX RX Current high-speed links are very complex : transmitter and receiver equalization circuitries and clock recovery and tracking blocks Complex analogy front ends : Support high-modulation, transmitter and receiver implement bandwidth extension techniques Finding optimum timing and equalization setting requires repeated link simulation over long simulation time 5

6 Circuit Simulation Techniques Developed in late 60 s and released as public domain program in early 1970 Few modification/variants added since then to address new challenges There are frequency and time domain, large and small-signal signal and noise analysis techniques that are well researched and widely used S-parameter analysis for large and small-signal analysis : passive or linearized systems Transient analysis for baseband circuits and startup transient : SPICE and it variants Shooting Newton for strongly nonlinear RF circuits : PLL, oscillators, power convertors Harmonic Balance for nonlinear RF circuits : mixer, filters Envelope analysis for complex modulated RF waveforms 6

7 Standard Circuit Simulation Techniques 1. Use nodal analysis technique to construct a system of differential equation from the circuit topology 2. Use stable implicit integration methods to convert the differential equation into a sequence of nonlinear algebraic equations 3. Use modified newton methods to solve the algebraic equations by solving a sequence of linear equations 4. Use sparse Gaussian elimination to solve the systems of linear equations generated by the Newton method The Sparse-matrix solution time grows super linearly with the size of the problem 7

8 Modified Nodal Formulation G 1 C 1 ϕ L =h L (i L ) v 1 v 2 v 3 v 4 The modified nodal analysis matrix (MNA) of the linearized circuit results in 6x6 matrix E + - i E G 2 i D =g D (v D ) i L G 3 q 3 =f C (v C ) Variables : v 1, v 2, v 3, v 4, i E, and i L The asterisked linearized circuit variables are the solution at an iteration point during the analysis and h = t n -t n-1, is the time step 8

9 Circuit Blocks in High-Speed Links Data in 32:4 Serializer Phase Rotator 4-Tap FIR FIFO CML to CMOS 4:2 Serializer Clock Generator Pre- Driver Output- Driver Rterm & T-coil, Network ESD TX out Channel RX in T-coil & Rterm Network ESD VGA CTLE CTLE Phase Detector Banks Multi-Tap DFE CML to CMOS 2:16 DMUX DFE Weights Phase Rotators Integrator Calibration Logic DFE Adaptation CDR Data out PLL PLL Ref Clock There are more than 100,000 transistors and other components The MNA matrix to be solved at each time point is very large The circuit simulation of a complete link using FAST SPICE can take more than a week to complete over a very short simulation time BER > 10-6 Much faster link simulation technique is a necessity 9 Ref Clock

10 High-Speed Link Simulation Challenges Interconnect systems consist of a large number of linear (distributed) networks that are accurately characterized in frequency domain Transistor-level circuit simulators are not efficient or adequate to estimate the performances of high-speed links The simulation of large systems with mixed-signal design using nonlinear time-domain simulators is too expensive Different circuit variables are changing at very different rates Large circuit variables can be inactive or latent for interconnect system It is computationally prohibitive to calculate link performance to low BER 10

11 Channel Frequency or Time-Domain Response Channel characteristics : frequency or time-domain responses Channel including packages as well as on-die termination, tcoil, and parasitic Extract the pulse responses for a given data rate from frequency or time domain responses H(f) h(t) TX Circuit Blocks TX: Rterm, Tcoil, C,... Pkg Channel Pkg RX: Rterm, Tcoil, C,... RX Circuit Blocks H(f) or h(t) Frequency time 11

12 Passive Sub blocks in a High-Speed Link Channel vv TX RX 12

13 Channel Frequency and Time-Domain Responses Pulse response is obtained from link frequency and/or timedomain responses of the passive system H(f) p(t) C 0 C 1 h(t) Frequency C -1 C 2 C 3 C 4 C 5 C 6 t -1 t 0 t 1 t 2 t 3 t 4 t 5 t 6 time Cursors, c(t), of pulse response waveform are determined time 13

14 C -1 C2 C 4 C5 t -1 t 0 t 1 t 2 t 3 t 4 t 5 t 6 Peak Distortion Analysis 1 C 3 C 6 t 6 C 0 C 1 C -1 C 2 C 4 C5 t -1 t 0 t 1 t 2 t 3 t 4 t 5 t 6 C 3 C 6 t 6 14

15 Peak Distortion Analysis 1 PDA can estimate worst-case eye height and data pattern from pulse response Worst-case 1 is summation of a 1 pulse with all negative residual pulse responses (except for C 0 ) Worst-case 0 is summation of a 0 pulse with all positive residual pulse responses (except for C 0 ) The worst case pattern : 1: [-(sign(c 6 ), -(sign(c 5 ), -(sign(c 4 ), -(sign(c 3 ), -(sign(c 2 ),-(sign(c 1 ), 1, -(sign(c -1 )]] 0: [ (sign(c 6 ), (sign(c 5 ), (sign(c 4 ), (sign(c 3 ), (sign(c 2 ), (sign(c 1 ), 1, (sign(c -1 )]] The worst-case eye height at s 1 (t)-s 0 (t) : C 0 C 1 C -1 C 2 C 4 C5 t -1 t 0 t 1 t 2 t 3 t 4 t 5 t 6 C 6 C 3 t 6 s 1 t = y 1 t + k= k 0 y(t kt) y(t kt)<0 s 0 t = y 0 t + k= k 0 y(t kt) y(t kt)>0 Wendem Beyene 14

16 Peak Distortion Analysis Algorithm C 0 Divide the pulse response into UI sections τ i = i UI C 1 C -1 C 2 C 4 C5 t -1 t 0 t 1 t 2 t 3 t 4 t 5 t 6 C 6 C 3 Mark all non-zero cursors 1 Finding the Worst Case 1 Find all the cursors with voltage < 0 at t i and sum them up The worst case high side eye voltage at t 0 = C 0 - (C 3 +C 6 ) For example: The Worst Case Pattern is Finding the Worst Case 0 Find all the UI s with voltage > 0 at T1 and sum up The worst case low side eye voltage t 0 = C 1 + C 1 +C 2 +C 4 +C 5 The worst case pattern :

17 Peak Distortion Analysis Algorithm Cont d C 0 Repeat 1 & 2 for t 1 t 2 t N to find the C 1 worst case eye For every sampling time t 0, the worst case patterns C -1 C 2 C 4 C5 t -1 t 0 t 1 t 2 t 3 t 4 t 5 t 6 are different C 0 C 3 C 6 C 1 Voltage C -1 C 2 C 4 C5 t -1 t 0 t 1 t 2 t 3 t 4 t 5 t 6 Time C 3 C 6 16

18 Determining ISI PDF of Link from Pulse Response Non zero cursor values, C(t), are determined from pulse response PDF is built by summing the number of bit sequences which produce each amplitude value given C(t) and dividing by the total number of bit sequences p(t) C 0 Probability C 1 C -1 C 2 t -1 t 0 t 1 t 2 time ISI (V) 17

19 0.25 Probability Forming ISI PDF p(t) C 0 C 1 C -1 C 2 p(t) t -1 t 0 t 1 t 2 time ISI (V) Probability time ISI (V) 18

20 ISI pdf of High-Speed Link from Pulse Response Each possible amplitude is determined by convolution of the bit sequence with C(t): with N non-zero cursors, the ISI combination is 2 N ISI PDF can be generated using progressive convolution of ISI Probability Probability = Probability ISI (Voltage) ISI (Voltage) ISI (Voltage) Probability Probability = Probability ISI (Voltage) ISI (Voltage) ISI (Voltage) 0 Probability 1 ISI (Voltage) 19

21 Voltage Constructing Eye Diagram From The ISI PDF Probability Probability ISI (Voltage) ISI (Voltage) ISI (Voltage) Time 20

22 Transmitter and receiver Jitter and Noise 2, TX Channel RX Tx jitter Rx jitter Receiver noise v v Tx Jitter (time) Rx Jitter (time) Rx noise (voltage) The transceiver jitter and noise can be added in the analysis Spectrum and correlation are not considered Transmitter jitter are not enhanced or colored by the channel 21

23 Voltage Next Steps in Statistical Modeling or Analysis 4 The transmitter adds jitter and nonlinearity to the signal Assume the jitter is independent of the data pattern and channel response Ä v v ISI (voltage) Jitter (time) The receiver adds jitter, noise and nonlinearity to the signal Assume the jitter and noise are independent of the data pattern and channel response time RX aperture 22

24 Summary of Statistical Channel ISI Modeling Obtain pulse (bit) response p(t) C 0 C 1 C -1 C 2 2. Compute ISI PDF of passive channel t -1 t 0 t 1 t 2 time 3. Convolve with the transmitter jitter 4. Convolve with the receiver jitter and noise ISI (voltage) Ä v v Jitter (time) 5. Compute BER with RX sampling distribution. 23

25 Transceiver Nonlinearity in High-Speed Link Vout (Voltage) Vout (Voltage) Vin (Voltage) Vin (Voltage) TX Channel RX Receiver Tx Rx noise jitter jitter High data rate Reduced slew rate (bandwidth limitation) High channel loss More complex transmitter and receiver equalization Low-power signaling Circuit topology Reduced parasitic Technology scaling Reduced supply (Headroom) On-chip AC coupling Circuit blocks to control baseline wandering 24

26 Typical Transceiver Nonlinearities 7 Linearity assumptions do not hold for current high-speed link analysis Nonlinearities in transmitter and receivers get worst with PVT Receiver nonlinearities significantly affect link performance The impact of nonlinearities in high-speed links can be captured via Volterra series expansion Nonlinearities are approximated by polynomial functions Nonlinearities represented using Hammerstein and Wiener models Probability distribution function (pdf) at the output as the function of pdf at the input 25

27 A High-Speed Link with Receiver Nonlinearity Consider a high-speed link with receiver nonlinearity y t = g R o x + n T h TCR + n R t where the LTI response : h TCR t = h T t *h C t *h R t 26

28 Transformation of Random Variable The random variable X with known pdf can be mapped to a random variable Y by function g 27

29 Hammerstein and Wiener Models LTI System : Let X denote the output of linear system f X X = f Y1 X Äf X2 X Ä f Y3 X f X3 X f Y3 Y Let Y denote the output of nonlinear transmitter Given Y = a 0 X + a 1 X 2 + a 1 X 3, f Y Y = dx dy f X X f X X g X f Y Y ο = 28

30 Receiver Nonlinearity : PAM Voltage (mv) Probability Density Eye diagram from linear receiver x 10-3 Eye diagram from nonlinear receiver Higher Modulation signaling suffers more from nonlinearity Voltage margin is significantly reduced Optimal reference voltage is shifted 29

31 Statistical Signal-Flow Based Link Analysis 5,6 Statistical link analysis Assumes linear-time invariant transmitter and receiver Assumes independent random bits : coded bit sequence is too complicated Time-domain response is not available It is not possible to handle time-dependent jitter and noise Impact of channel loss (jitter amplification and jitter coloring)not captured Signal-flow (bit-by-bit, waveform, convolution-based) time-domain analysis Eye diagrams are efficiently calculated from given bit patterns Provide time-domain waveforms and frequency-domain responses (FFT) Provide flexibility to use training and encoded patterns Straight forward to add jitter and noise Need extrapolation to go down to low BER levels (Long simulation time) Computationally still inefficient for low BER 30

32 Convolution-Based Link Analysis Time-domain jitter and voltage noise can be introduced b i : digital bit sequence, either 1 or 0 and V 0 : output voltage t TX : Transmitter jitter and V TX : Transmitter voltage noise V TX (t) = b i (V 0 + V TX (t+ t TX )) is the jittery and noisy transmitter waveform V RX : Receiver voltage noise b i V TX Tx (t) V CH (t) V Channel : h C (t) h ctle (t) CTLE (t) DFE y(t) 31

33 Summary Statistical : Public, in-house or commercial tools with widely different capabilities Signal flow : Commercial system simulators, consulting groups and in-house tools Transistor-level : Commercial tools Statistical Signal-Flow Transistor-Level Seconds to minutes minutes to hours days to weeks 32

34 References 1. Bryan K. Casper, et. al, An accurate and efficient analysis method for multi-gb/s chip-to-chip signaling scheme, in Digest of Technical Papers from the IEEE Symposium on VLSI Circuits, June 2002, pp Vladimir Stojanovic, et. al, Modeling and analysis of high speed links, in IEEE Custom Integrated Circuits Conf. Dig. Tech. Papers, Sept 2003, pp A Sanders, et. al, Channel Compliance Testing Utilizing Novel Statistical Eye Methodology, DesignCon G. Balamurugan, et. al, "Modeling and Analysis of High-Speed I/O Links," IEEE Transactions on Advanced Packaging, vol. 32, no. 2, , G. Balamurugan, et. al, Modeling and mitigation of jitter in multi-gbps source-synchronous I/O links, in Int. Conf. Comput. Design, Oct. 2003, pp N. Blitvic, et. al, Channel coding for high-speed links: A systematic look at code performance and system simulation, IEEE Transactions on Advanced Packaging, W. Beyene, et. al, Statistical simulation of high-speed links with transmitter and receiver nonlinearities, in IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems, Oct. 2014, pp J. Vlach and K. Singhal. Computer Methods for Circuit Analysis and Design. Van Nostrand Reinhold Co., New York, NY, second edition,

35 Questions & Discussion

DesignCon Comparison of Two Statistical Methods for High Speed Serial Link Simulation

DesignCon Comparison of Two Statistical Methods for High Speed Serial Link Simulation DesignCon 2013 Comparison of Two Statistical Methods for High Speed Serial Link Simulation Masashi Shimanouchi, Altera Corporation mshimano@alatera.com Mike Peng Li, Altera Corporation mpli@altera.com

More information

ECEN 720 High-Speed Links: Circuits and Systems

ECEN 720 High-Speed Links: Circuits and Systems 1 ECEN 720 High-Speed Links: Circuits and Systems Lab4 Receiver Circuits Objective To learn fundamentals of receiver circuits. Introduction Receivers are used to recover the data stream transmitted by

More information

To learn fundamentals of high speed I/O link equalization techniques.

To learn fundamentals of high speed I/O link equalization techniques. 1 ECEN 720 High-Speed Links: Circuits and Systems Lab5 Equalization Circuits Objective To learn fundamentals of high speed I/O link equalization techniques. Introduction An ideal cable could propagate

More information

ECEN 720 High-Speed Links Circuits and Systems

ECEN 720 High-Speed Links Circuits and Systems 1 ECEN 720 High-Speed Links Circuits and Systems Lab4 Receiver Circuits Objective To learn fundamentals of receiver circuits. Introduction Receivers are used to recover the data stream transmitted by transmitters.

More information

Comparison of Time Domain and Statistical IBIS-AMI Analyses Mike LaBonte SiSoft

Comparison of Time Domain and Statistical IBIS-AMI Analyses Mike LaBonte SiSoft Comparison of Time Domain and Statistical IBIS-AMI Analyses Mike LaBonte SiSoft Asian IBIS Summit 2017 Taipei, ROC November 15, 2017 9 Combinations of TX and RX Model Types AMI file has: GetWave_Exists

More information

Comparison of Time Domain and Statistical IBIS-AMI Analyses

Comparison of Time Domain and Statistical IBIS-AMI Analyses Comparison of Time Domain and Statistical IBIS-AMI Analyses Mike LaBonte SiSoft Asian IBIS Summit 2017 Shanghai, PRC November 13, 2017 9 Combinations of TX and RX Model Types AMI file has: GetWave_Exists

More information

ECEN720: High-Speed Links Circuits and Systems Spring 2017

ECEN720: High-Speed Links Circuits and Systems Spring 2017 ECEN72: High-Speed Links Circuits and Systems Spring 217 Lecture 4: Channel Pulse Model & Modulation Schemes Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements & Agenda Lab 1 Report

More information

As presented at Euro DesignCon 2004 Channel Compliance Testing Utilizing Novel Statistical Eye Methodology

As presented at Euro DesignCon 2004 Channel Compliance Testing Utilizing Novel Statistical Eye Methodology T10/05-198r0 As presented at Euro DesignCon 2004 Channel Compliance Testing Utilizing Novel Statistical Eye Methodology Anthony Sanders Infineon Technologies Mike Resso John D Ambrosia Technologies Agilent

More information

Appendix. RF Transient Simulator. Page 1

Appendix. RF Transient Simulator. Page 1 Appendix RF Transient Simulator Page 1 RF Transient/Convolution Simulation This simulator can be used to solve problems associated with circuit simulation, when the signal and waveforms involved are modulated

More information

ECEN720: High-Speed Links Circuits and Systems Spring 2017

ECEN720: High-Speed Links Circuits and Systems Spring 2017 ECEN720: High-Speed Links Circuits and Systems Spring 2017 Lecture 12: CDRs Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Project Preliminary Report #2 due Apr. 20 Expand

More information

SV2C 28 Gbps, 8 Lane SerDes Tester

SV2C 28 Gbps, 8 Lane SerDes Tester SV2C 28 Gbps, 8 Lane SerDes Tester Data Sheet SV2C Personalized SerDes Tester Data Sheet Revision: 1.0 2015-03-19 Revision Revision History Date 1.0 Document release. March 19, 2015 The information in

More information

ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012

ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012 ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 0 Lecture 8: RX FIR, CTLE, & DFE Equalization Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Exam is

More information

A 5-Gb/s 156-mW Transceiver with FFE/Analog Equalizer in 90-nm CMOS Technology Wang Xinghua a, Wang Zhengchen b, Gui Xiaoyan c,

A 5-Gb/s 156-mW Transceiver with FFE/Analog Equalizer in 90-nm CMOS Technology Wang Xinghua a, Wang Zhengchen b, Gui Xiaoyan c, 4th International Conference on Computer, Mechatronics, Control and Electronic Engineering (ICCMCEE 2015) A 5-Gb/s 156-mW Transceiver with FFE/Analog Equalizer in 90-nm CMOS Technology Wang Xinghua a,

More information

ECEN720: High-Speed Links Circuits and Systems Spring 2017

ECEN720: High-Speed Links Circuits and Systems Spring 2017 ECEN720: High-Speed Links Circuits and Systems Spring 2017 Lecture 9: Noise Sources Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Lab 5 Report and Prelab 6 due Apr. 3 Stateye

More information

To learn statistical bit-error-rate (BER) simulation, BER link noise budgeting and using ADS to model high speed I/O link circuits

To learn statistical bit-error-rate (BER) simulation, BER link noise budgeting and using ADS to model high speed I/O link circuits 1 ECEN 720 High-Speed Links: Circuits and Systems Lab6 Link Modeling with ADS Objective To learn statistical bit-error-rate (BER) simulation, BER link noise budgeting and using ADS to model high speed

More information

Studies on FIR Filter Pre-Emphasis for High-Speed Backplane Data Transmission

Studies on FIR Filter Pre-Emphasis for High-Speed Backplane Data Transmission Studies on FIR Filter Pre-Emphasis for High-Speed Backplane Data Transmission Miao Li Department of Electronics Carleton University Ottawa, ON. K1S5B6, Canada Tel: 613 525754 Email:mili@doe.carleton.ca

More information

CLOCK AND DATA RECOVERY (CDR) circuits incorporating

CLOCK AND DATA RECOVERY (CDR) circuits incorporating IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 9, SEPTEMBER 2004 1571 Brief Papers Analysis and Modeling of Bang-Bang Clock and Data Recovery Circuits Jri Lee, Member, IEEE, Kenneth S. Kundert, and

More information

High Speed I/O 2-PAM Receiver Design. EE215E Project. Signaling and Synchronization. Submitted By

High Speed I/O 2-PAM Receiver Design. EE215E Project. Signaling and Synchronization. Submitted By High Speed I/O 2-PAM Receiver Design EE215E Project Signaling and Synchronization Submitted By Amrutha Iyer Kalpana Manickavasagam Pritika Dandriyal Joseph P Mathew Problem Statement To Design a high speed

More information

ECEN720: High-Speed Links Circuits and Systems Spring 2017

ECEN720: High-Speed Links Circuits and Systems Spring 2017 ECEN720: High-Speed Links Circuits and Systems Spring 207 Lecture 8: RX FIR, CTLE, DFE, & Adaptive Eq. Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Lab 4 Report and Prelab

More information

A 10Gbps Analog Adaptive Equalizer and Pulse Shaping Circuit for Backplane Interface

A 10Gbps Analog Adaptive Equalizer and Pulse Shaping Circuit for Backplane Interface Proceedings of the 5th WSEAS Int. Conf. on CIRCUITS, SYSTEMS, ELECTRONICS, CONTROL & SIGNAL PROCESSING, Dallas, USA, November 1-3, 2006 225 A 10Gbps Analog Adaptive Equalizer and Pulse Shaping Circuit

More information

TITLE. Capturing (LP)DDR4 Interface PSIJ and RJ Performance. Image. Topic: Topic: John Ellis, Synopsys, Inc. Topic: malesuada blandit euismod.

TITLE. Capturing (LP)DDR4 Interface PSIJ and RJ Performance. Image. Topic: Topic: John Ellis, Synopsys, Inc. Topic: malesuada blandit euismod. TITLE Topic: o Nam elementum commodo mattis. Pellentesque Capturing (LP)DDR4 Interface PSIJ and RJ Performance malesuada blandit euismod. Topic: John Ellis, Synopsys, Inc. o o Nam elementum commodo mattis.

More information

100 Gb/s: The High Speed Connectivity Race is On

100 Gb/s: The High Speed Connectivity Race is On 100 Gb/s: The High Speed Connectivity Race is On Cathy Liu SerDes Architect, LSI Corporation Harold Gomard SerDes Product Manager, LSI Corporation October 6, 2010 Agenda 100 Gb/s Ethernet evolution SoC

More information

To learn S-parameter, eye diagram, ISI, modulation techniques and to simulate in Matlab and Cadence.

To learn S-parameter, eye diagram, ISI, modulation techniques and to simulate in Matlab and Cadence. 1 ECEN 689 High-Speed Links Circuits and Systems Lab2- Channel Models Objective To learn S-parameter, eye diagram, ISI, modulation techniques and to simulate in Matlab and Cadence. Introduction S-parameters

More information

To learn S-parameters, eye diagram, ISI, modulation techniques and their simulations in MATLAB and Cadence.

To learn S-parameters, eye diagram, ISI, modulation techniques and their simulations in MATLAB and Cadence. 1 ECEN 720 High-Speed Links: Circuits and Systems Lab2- Channel Models Objective To learn S-parameters, eye diagram, ISI, modulation techniques and their simulations in MATLAB and Cadence. Introduction

More information

To learn Statistical Bit-error-rate (BER) simulation, BERlink noise budgeting and usage of ADS to model high speed I/O link circuits.

To learn Statistical Bit-error-rate (BER) simulation, BERlink noise budgeting and usage of ADS to model high speed I/O link circuits. 1 ECEN 720 High-Speed Links Circuits and Systems Lab6 Link Modeling with ADS Objective To learn Statistical Bit-error-rate (BER) simulation, BERlink noise budgeting and usage of ADS to model high speed

More information

ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012

ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012 ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012 Lecture 6: RX Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Lab 4 Prelab due now Exam

More information

A10-Gb/slow-power adaptive continuous-time linear equalizer using asynchronous under-sampling histogram

A10-Gb/slow-power adaptive continuous-time linear equalizer using asynchronous under-sampling histogram LETTER IEICE Electronics Express, Vol.10, No.4, 1 8 A10-Gb/slow-power adaptive continuous-time linear equalizer using asynchronous under-sampling histogram Wang-Soo Kim and Woo-Young Choi a) Department

More information

ULTRASCALE DDR4 DE-EMPHASIS AND CTLE FEATURE OPTIMIZATION WITH STATISTICAL ENGINE FOR BER SPECIFICATION

ULTRASCALE DDR4 DE-EMPHASIS AND CTLE FEATURE OPTIMIZATION WITH STATISTICAL ENGINE FOR BER SPECIFICATION ULTRASCALE DDR4 DE-EMPHASIS AND CTLE FEATURE OPTIMIZATION WITH STATISTICAL ENGINE FOR BER SPECIFICATION Penglin Niu, penglin@xilinx.com Fangyi Rao, fangyi_rao@keysight.com Juan Wang, juanw@xilinx.com Gary

More information

Toward SSC Modulation Specs and Link Budget

Toward SSC Modulation Specs and Link Budget Toward SSC Modulation Specs and Link Budget (Spreading the Pain) Guillaume Fortin, Rick Hernandez & Mathieu Gagnon PMC-Sierra 1 Overview The JTF as a model of CDR performance Using the JTF to qualify SSC

More information

EQUALIZERS. HOW DO? BY: ANKIT JAIN

EQUALIZERS. HOW DO? BY: ANKIT JAIN EQUALIZERS. HOW DO? BY: ANKIT JAIN AGENDA DFE (Decision Feedback Equalizer) Basics FFE (Feed-Forward Equalizer) Basics CTLE (Continuous-Time Linear Equalizer) Basics More Complex Equalization UNDERSTANDING

More information

TITLE. Image. Topic: Topic: Hee-Soo o LEE, Keysight Technologies Cindy Cui, Keysight Technologies

TITLE. Image. Topic: Topic: Hee-Soo o LEE, Keysight Technologies Cindy Cui, Keysight Technologies TITLE Topic: Accurate o Nam elementum Statistical-Based commodo mattis. Pellentesque DDR4 Margin Estimation using malesuada SSN blandit Induced euismod. Jitter Model Topic: Hee-Soo o LEE, Keysight Technologies

More information

A Complete 64Gb/s/lane Active Electrical Repeater. Yue Lu, Jaeduk Han, Nicholas Sutardja Prof. Elad Alon January 23, 2014

A Complete 64Gb/s/lane Active Electrical Repeater. Yue Lu, Jaeduk Han, Nicholas Sutardja Prof. Elad Alon January 23, 2014 A Complete 64Gb/s/lane Active Electrical Repeater Yue Lu, Jaeduk Han, Nicholas Sutardja Prof. Elad Alon January 23, 2014 The Electrical Signaling Challenge Required I/O speed rising dramatically, but power

More information

ECEN620: Network Theory Broadband Circuit Design Fall 2014

ECEN620: Network Theory Broadband Circuit Design Fall 2014 ECEN620: Network Theory Broadband Circuit Design Fall 2014 Lecture 16: CDRs Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Project descriptions are posted on the website Preliminary

More information

A CMOS Multi-Gb/s 4-PAM Serial Link Transceiver*

A CMOS Multi-Gb/s 4-PAM Serial Link Transceiver* A CMOS Multi-Gb/s 4-PAM Serial Link Transceiver* March 11, 1999 Ramin Farjad-Rad Center for Integrated Systems Stanford University Stanford, CA 94305 *Funding from LSI Logic, SUN Microsystems, and Powell

More information

Ultrascale DDR4 De-emphasis and CTLE Feature Optimization with Statistical Engine for BER Specification

Ultrascale DDR4 De-emphasis and CTLE Feature Optimization with Statistical Engine for BER Specification DesignCon 2015 Ultrascale DDR4 De-emphasis and CTLE Feature Optimization with Statistical Engine for BER Specification Penglin Niu, Xilinx Inc Fangyi Rao, Keysight Technologies Juan Wang, Xilinx Inc Gary

More information

Detection and Estimation of Signals in Noise. Dr. Robert Schober Department of Electrical and Computer Engineering University of British Columbia

Detection and Estimation of Signals in Noise. Dr. Robert Schober Department of Electrical and Computer Engineering University of British Columbia Detection and Estimation of Signals in Noise Dr. Robert Schober Department of Electrical and Computer Engineering University of British Columbia Vancouver, August 24, 2010 2 Contents 1 Basic Elements

More information

Effect of Power Noise on Multi-Gigabit Serial Links

Effect of Power Noise on Multi-Gigabit Serial Links Effect of Power Noise on Multi-Gigabit Serial Links Ken Willis (kwillis@sigrity.com) Kumar Keshavan (ckumar@sigrity.com) Jack Lin (jackwclin@sigrity.com) Tariq Abou-Jeyab (tariqa@sigrity.com) Sigrity Inc.,

More information

06-496r3 SAS-2 Electrical Specification Proposal. Kevin Witt SAS-2 Phy Working Group 1/16/07

06-496r3 SAS-2 Electrical Specification Proposal. Kevin Witt SAS-2 Phy Working Group 1/16/07 06-496r3 SAS-2 Electrical Specification Proposal Kevin Witt SAS-2 Phy Working Group 1/16/07 Overview Motivation Multiple SAS-2 Test Chips Have Been Built and Tested, SAS-2 Product Designs have Started

More information

08-027r2 Toward SSC Modulation Specs and Link Budget

08-027r2 Toward SSC Modulation Specs and Link Budget 08-027r2 Toward SSC Modulation Specs and Link Budget (Spreading the Pain) Guillaume Fortin, Rick Hernandez & Mathieu Gagnon PMC-Sierra 1 Overview The JTF as a model of CDR performance Using the JTF to

More information

LSI and Circuit Technologies for the SX-8 Supercomputer

LSI and Circuit Technologies for the SX-8 Supercomputer LSI and Circuit Technologies for the SX-8 Supercomputer By Jun INASAKA,* Toshio TANAHASHI,* Hideaki KOBAYASHI,* Toshihiro KATOH,* Mikihiro KAJITA* and Naoya NAKAYAMA This paper describes the LSI and circuit

More information

Introduction to RF Simulation and Its Applications

Introduction to RF Simulation and Its Applications Introduction to RF Simulation and Its Applications by Kenneth S. Kundert Presenter - Saurabh Jain What will he talk about? Challenges for RF design and simulations RF circuit characteristics Basic RF building

More information

Two for One: SerDes Flows for AMI Model Development

Two for One: SerDes Flows for AMI Model Development Two for One: SerDes Flows for AMI Model Development Corey Mathis, Ren Sang Nah (MathWorks) Richard Allred, Todd Westerhoff (SiSoft) DesignCon 2016 IBIS Summit Santa Clara, California January 22, 2016 *

More information

Ultra-high-speed Interconnect Technology for Processor Communication

Ultra-high-speed Interconnect Technology for Processor Communication Ultra-high-speed Interconnect Technology for Processor Communication Yoshiyasu Doi Samir Parikh Yuki Ogata Yoichi Koyanagi In order to improve the performance of storage systems and servers that make up

More information

ISSCC 2003 / SESSION 4 / CLOCK RECOVERY AND BACKPLANE TRANSCEIVERS / PAPER 4.3

ISSCC 2003 / SESSION 4 / CLOCK RECOVERY AND BACKPLANE TRANSCEIVERS / PAPER 4.3 ISSCC 2003 / SESSION 4 / CLOCK RECOVERY AND BACKPLANE TRANSCEIVERS / PAPER 4.3 4.3 A Second-Order Semi-Digital Clock Recovery Circuit Based on Injection Locking M.-J. Edward Lee 1, William J. Dally 1,2,

More information

DesignCon 2017 Characterization of DDR4 Receiver Sensitivity Impact on Post-equalization Eye

DesignCon 2017 Characterization of DDR4 Receiver Sensitivity Impact on Post-equalization Eye DesignCon 2017 Characterization of DDR4 Receiver Sensitivity Impact on Post-equalization Eye Yong Wang, Xilinx Inc. Thomas To, Xilinx Inc. Penglin Niu, Xilinx Inc. Fangyi Rao, Keysight Technologies Juan

More information

ECEN620: Network Theory Broadband Circuit Design Fall 2012

ECEN620: Network Theory Broadband Circuit Design Fall 2012 ECEN620: Network Theory Broadband Circuit Design Fall 2012 Lecture 20: CDRs Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Exam 2 is on Friday Nov. 9 One double-sided 8.5x11

More information

Instantaneous Loop. Ideal Phase Locked Loop. Gain ICs

Instantaneous Loop. Ideal Phase Locked Loop. Gain ICs Instantaneous Loop Ideal Phase Locked Loop Gain ICs PHASE COORDINATING An exciting breakthrough in phase tracking, phase coordinating, has been developed by Instantaneous Technologies. Instantaneous Technologies

More information

10Gb/s PMD Using PAM-5 Trellis Coded Modulation

10Gb/s PMD Using PAM-5 Trellis Coded Modulation 10Gb/s PMD Using PAM-5 Trellis Coded Modulation Oscar Agazzi, Nambi Seshadri, Gottfried Ungerboeck Broadcom Corp. 16215 Alton Parkway Irvine, CA 92618 1 Goals Achieve distance objective of 300m over existing

More information

OIF CEI 6G LR OVERVIEW

OIF CEI 6G LR OVERVIEW OIF CEI 6G LR OVERVIEW Graeme Boyd, Yuriy Greshishchev T10 SAS-2 WG meeting, Houston, 25-26 May 2005 www.pmc-sierra.com 1 Outline! Why CEI-6G LR is of Interest to SAS-2?! CEI-6G- LR Specification Methodology!

More information

56+ Gb/s Serial Transmission using Duobinary Signaling

56+ Gb/s Serial Transmission using Duobinary Signaling 56+ Gb/s Serial Transmission using Duobinary Signaling Jan De Geest Senior Staff R&D Signal Integrity Engineer, FCI Timothy De Keulenaer Doctoral Researcher, Ghent University, INTEC-IMEC Introduction Motivation

More information

06-011r0 Towards a SAS-2 Physical Layer Specification. Kevin Witt 11/30/2005

06-011r0 Towards a SAS-2 Physical Layer Specification. Kevin Witt 11/30/2005 06-011r0 Towards a SAS-2 Physical Layer Specification Kevin Witt 11/30/2005 Physical Layer Working Group Goal Draft a Specification which will: 1. Meet the System Designers application requirements, 2.

More information

This chapter discusses the design issues related to the CDR architectures. The

This chapter discusses the design issues related to the CDR architectures. The Chapter 2 Clock and Data Recovery Architectures 2.1 Principle of Operation This chapter discusses the design issues related to the CDR architectures. The bang-bang CDR architectures have recently found

More information

ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012

ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012 ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012 Lecture 5: Termination, TX Driver, & Multiplexer Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements

More information

A 2.2GHZ-2.9V CHARGE PUMP PHASE LOCKED LOOP DESIGN AND ANALYSIS

A 2.2GHZ-2.9V CHARGE PUMP PHASE LOCKED LOOP DESIGN AND ANALYSIS A 2.2GHZ-2.9V CHARGE PUMP PHASE LOCKED LOOP DESIGN AND ANALYSIS Diary R. Sulaiman e-mail: diariy@gmail.com Salahaddin University, Engineering College, Electrical Engineering Department Erbil, Iraq Key

More information

Lecture 8. Jaeha Kim. Seoul National University

Lecture 8. Jaeha Kim. Seoul National University Lecture 8. Introduction to RF Simulation Jaeha Kim Mixed-Signal IC and System Group (MICS) Seoul National University jaeha@ieee.org 1 Overview Readings: K. Kundert, Introduction to RF Simulation and Its

More information

2002 IEEE International Solid-State Circuits Conference 2002 IEEE

2002 IEEE International Solid-State Circuits Conference 2002 IEEE Outline 802.11a Overview Medium Access Control Design Baseband Transmitter Design Baseband Receiver Design Chip Details What is 802.11a? IEEE standard approved in September, 1999 12 20MHz channels at 5.15-5.35

More information

Chapter 9. Digital Communication Through Band-Limited Channels. Muris Sarajlic

Chapter 9. Digital Communication Through Band-Limited Channels. Muris Sarajlic Chapter 9 Digital Communication Through Band-Limited Channels Muris Sarajlic Band limited channels (9.1) Analysis in previous chapters considered the channel bandwidth to be unbounded All physical channels

More information

Course Overview. EELE 461/561 Digital System Design. Module #1 Digital Signaling. Course Overview. Course Overview. Course Content.

Course Overview. EELE 461/561 Digital System Design. Module #1 Digital Signaling. Course Overview. Course Overview. Course Content. Topics EELE 46/56 Digital System Design. Course Overview. Definitions 3. Textbook Reading Assignments...7,.,.0 Module # Digital What you should be able to do after this module. Describe what signal integrity

More information

A Two-Tone Test Method for Continuous-Time Adaptive Equalizers

A Two-Tone Test Method for Continuous-Time Adaptive Equalizers Two-Tone Test Method for Continuous-Time daptive Equalizers Dongwoo Hong*, Shadi Saberi**, Kwang-Ting (Tim) Cheng*, C. Patrick Yue* University of California, Santa Barbara, C, US* Carnegie Mellon University,

More information

Jitter in Digital Communication Systems, Part 1

Jitter in Digital Communication Systems, Part 1 Application Note: HFAN-4.0.3 Rev.; 04/08 Jitter in Digital Communication Systems, Part [Some parts of this application note first appeared in Electronic Engineering Times on August 27, 200, Issue 8.] AVAILABLE

More information

High-Speed Serial IO Testing: Jitter Extraction & Bit-Error Rate Estimation. Serial Signaling Speed Trend

High-Speed Serial IO Testing: Jitter Extraction & Bit-Error Rate Estimation. Serial Signaling Speed Trend High-Speed Serial IO Testing: Jitter Extraction & Bit-Error Rate Estimation K.-T. Tim Cheng Dept. of ECE University of California, Santa Barbara Serial Signaling Speed Trend 8/6/04 Bus Topologies 8/6/04

More information

Bridging the Measurement and Simulation Gap Sarah Boen Marketing Manager Tektronix

Bridging the Measurement and Simulation Gap Sarah Boen Marketing Manager Tektronix Bridging the Measurement and Simulation Gap Sarah Boen Marketing Manager Tektronix 1 Agenda Synergy between simulation and lab based measurements IBIS-AMI overview Simulation and measurement correlation

More information

High-Speed Link Tuning Using Signal Conditioning Circuitry in Stratix V Transceivers

High-Speed Link Tuning Using Signal Conditioning Circuitry in Stratix V Transceivers High-Speed Link Tuning Using Signal Conditioning Circuitry in Stratix V Transceivers AN678 Subscribe This application note provides a set of guidelines to run error free across backplanes at high-speed

More information

A digital phase corrector with a duty cycle detector and transmitter for a Quad Data Rate I/O scheme

A digital phase corrector with a duty cycle detector and transmitter for a Quad Data Rate I/O scheme A digital phase corrector with a duty cycle detector and transmitter for a Quad Data Rate I/O scheme Young-Chan Jang a) School of Electronic Engineering, Kumoh National Institute of Technology, 1, Yangho-dong,

More information

Chip-to-module far-end TX eye measurement proposal

Chip-to-module far-end TX eye measurement proposal Chip-to-module far-end TX eye measurement proposal Raj Hegde & Adam Healey IEEE P802.3bs 400 Gb/s Ethernet Task Force March 2017 Vancouver, BC, Canada 1 Background In smith_3bs_01a_0915, it was shown that

More information

Low power SERDES transceiver for supply-induced jitter sensitivity methodology analysis

Low power SERDES transceiver for supply-induced jitter sensitivity methodology analysis Low power SERDES transceiver for supply-induced jitter sensitivity methodology analysis Micro Chang htc Michael_Chang@hTC.com Jan 9, 2019 X 1 Agenda Jitter-aware target impedance of power delivery network

More information

DesignCon 2010 Predicting BER with IBIS-AMI: experiences correlating SerDes simulations and measurement

DesignCon 2010 Predicting BER with IBIS-AMI: experiences correlating SerDes simulations and measurement DesignCon 2010 Predicting BER with IBIS-AMI: experiences correlating SerDes simulations and measurement Todd Westerhoff, Signal Integrity Software, Inc. twesterh@sisoft.com Adge Hawes, IBM adge@uk.ibm.com

More information

ECEN 620: Network Theory Broadband Circuit Design Fall 2012

ECEN 620: Network Theory Broadband Circuit Design Fall 2012 ECEN 620: Network Theory Broadband Circuit Design Fall 2012 Lecture 23: High-Speed I/O Overview Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Exam 3 is postponed to Dec. 11

More information

Efficient End-to-end Simulations

Efficient End-to-end Simulations Efficient End-to-end Simulations of 25G Optical Links Sanjeev Gupta, Avago Technologies Fangyi Rao, Agilent Technologies Jing-tao Liu, Agilent Technologies Amolak Badesha, Avago Technologies DesignCon

More information

Signal Processing Techniques for Software Radio

Signal Processing Techniques for Software Radio Signal Processing Techniques for Software Radio Behrouz Farhang-Boroujeny Department of Electrical and Computer Engineering University of Utah c 2007, Behrouz Farhang-Boroujeny, ECE Department, University

More information

Integrated Circuit Design for High-Speed Frequency Synthesis

Integrated Circuit Design for High-Speed Frequency Synthesis Integrated Circuit Design for High-Speed Frequency Synthesis John Rogers Calvin Plett Foster Dai ARTECH H O US E BOSTON LONDON artechhouse.com Preface XI CHAPTER 1 Introduction 1 1.1 Introduction to Frequency

More information

HIGH-SPEED LOW-POWER ON-CHIP GLOBAL SIGNALING DESIGN OVERVIEW. Xi Chen, John Wilson, John Poulton, Rizwan Bashirullah, Tom Gray

HIGH-SPEED LOW-POWER ON-CHIP GLOBAL SIGNALING DESIGN OVERVIEW. Xi Chen, John Wilson, John Poulton, Rizwan Bashirullah, Tom Gray HIGH-SPEED LOW-POWER ON-CHIP GLOBAL SIGNALING DESIGN OVERVIEW Xi Chen, John Wilson, John Poulton, Rizwan Bashirullah, Tom Gray Agenda Problems of On-chip Global Signaling Channel Design Considerations

More information

10GBASE-T T Tutorial. SolarFlare Communications IEEE Kauai, Hawaii. November 11, 2002

10GBASE-T T Tutorial. SolarFlare Communications IEEE Kauai, Hawaii. November 11, 2002 10GBASE-T T Tutorial IEEE 802.3 Kauai, Hawaii November 11, 2002 Communications Communications 10GBASE-T IEEE Tutorial, 11/11/2002 1 Agenda Introduction, Cabling & Challenges - George Zimmerman, Ph.D. CEO

More information

High-Throughput, High- Sensitivity Measurement of Power Supply-Induced Bounded, Uncorrelated Jitter in Time, Frequency, and Statistical Domains

High-Throughput, High- Sensitivity Measurement of Power Supply-Induced Bounded, Uncorrelated Jitter in Time, Frequency, and Statistical Domains DesignCon 2013 High-Throughput, High- Sensitivity Measurement of Power Supply-Induced Bounded, Uncorrelated Jitter in Time, Frequency, and Statistical Domains Daniel Chow, Ph.D., Altera Corporation dchow@altera.com

More information

BER-optimal ADC for Serial Links

BER-optimal ADC for Serial Links BER-optimal ADC for Serial Links Speaker Name: Yingyan Lin Co-authors: Min-Sun Keel, Adam Faust, Aolin Xu, Naresh R. Shanbhag, Elyse Rosenbaum, and Andrew Singer Advisor s name: Naresh R. Shanbhag Affiliation:

More information

CHARACTERIZATION and modeling of large-signal

CHARACTERIZATION and modeling of large-signal IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 53, NO. 2, APRIL 2004 341 A Nonlinear Dynamic Model for Performance Analysis of Large-Signal Amplifiers in Communication Systems Domenico Mirri,

More information

LOW COST PHASED ARRAY ANTENNA TRANSCEIVER FOR WPAN APPLICATIONS

LOW COST PHASED ARRAY ANTENNA TRANSCEIVER FOR WPAN APPLICATIONS LOW COST PHASED ARRAY ANTENNA TRANSCEIVER FOR WPAN APPLICATIONS Introduction WPAN (Wireless Personal Area Network) transceivers are being designed to operate in the 60 GHz frequency band and will mainly

More information

EDI CON USA Addressing DDR5 design challenges with IBIS-AMI modeling techniques. Todd Westerhoff, SiSoft Doug Burns, SiSoft Eric Brock, SiSoft

EDI CON USA Addressing DDR5 design challenges with IBIS-AMI modeling techniques. Todd Westerhoff, SiSoft Doug Burns, SiSoft Eric Brock, SiSoft EDI CON USA 2017 Addressing DDR5 design challenges with IBIS-AMI modeling techniques Todd Westerhoff, SiSoft Doug Burns, SiSoft Eric Brock, SiSoft This page intentionally blank to support double-sided

More information

Wideband Channel Characterization. Spring 2017 ELE 492 FUNDAMENTALS OF WIRELESS COMMUNICATIONS 1

Wideband Channel Characterization. Spring 2017 ELE 492 FUNDAMENTALS OF WIRELESS COMMUNICATIONS 1 Wideband Channel Characterization Spring 2017 ELE 492 FUNDAMENTALS OF WIRELESS COMMUNICATIONS 1 Wideband Systems - ISI Previous chapter considered CW (carrier-only) or narrow-band signals which do NOT

More information

Theory of Telecommunications Networks

Theory of Telecommunications Networks Theory of Telecommunications Networks Anton Čižmár Ján Papaj Department of electronics and multimedia telecommunications CONTENTS Preface... 5 1 Introduction... 6 1.1 Mathematical models for communication

More information

Multi-Gigabit Serial Link Simulation with Xilinx 7 Series FPGA GTX Transceiver IBIS-AMI Models

Multi-Gigabit Serial Link Simulation with Xilinx 7 Series FPGA GTX Transceiver IBIS-AMI Models White Paper: 7 Series FPGAs WP424 (v1.) September 28, 212 Multi-Gigabit Serial Link Simulation with Xilinx 7 Series FPGA GTX Transceiver IBIS-AMI Models By: Harry Fu, Romi Mayder, and Ian Zhuang The 7

More information

Line Coding for Digital Communication

Line Coding for Digital Communication Line Coding for Digital Communication How do we transmit bits over a wire, RF, fiber? Line codes, many options Power spectrum of line codes, how much bandwidth do they take Clock signal and synchronization

More information

Analog-to-Digital Converter Performance Signoff with Analog FastSPICE Transient Noise at Qualcomm

Analog-to-Digital Converter Performance Signoff with Analog FastSPICE Transient Noise at Qualcomm Analog-to-Digital Converter Performance Signoff with Analog FastSPICE Transient Noise at Qualcomm 2009 Berkeley Design Automation, Inc. 2902 Stender Way, Santa Clara, CA USA 95054 www.berkeley-da.com Tel:

More information

Dedication. To Mum and Dad

Dedication. To Mum and Dad Dedication To Mum and Dad Acknowledgment Table of Contents List of Tables List of Figures A B A B 0 1 B A List of Abbreviations Abstract Chapter1 1 Introduction 1.1. Motivation Figure 1. 1 The relative

More information

ISSCC 2006 / SESSION 13 / OPTICAL COMMUNICATION / 13.2

ISSCC 2006 / SESSION 13 / OPTICAL COMMUNICATION / 13.2 13.2 An MLSE Receiver for Electronic-Dispersion Compensation of OC-192 Fiber Links Hyeon-min Bae 1, Jonathan Ashbrook 1, Jinki Park 1, Naresh Shanbhag 2, Andrew Singer 2, Sanjiv Chopra 1 1 Intersymbol

More information

Introduction. In the frequency domain, complex signals are separated into their frequency components, and the level at each frequency is displayed

Introduction. In the frequency domain, complex signals are separated into their frequency components, and the level at each frequency is displayed SPECTRUM ANALYZER Introduction A spectrum analyzer measures the amplitude of an input signal versus frequency within the full frequency range of the instrument The spectrum analyzer is to the frequency

More information

Analysis and Design of Autonomous Microwave Circuits

Analysis and Design of Autonomous Microwave Circuits Analysis and Design of Autonomous Microwave Circuits ALMUDENA SUAREZ IEEE PRESS WILEY A JOHN WILEY & SONS, INC., PUBLICATION Contents Preface xiii 1 Oscillator Dynamics 1 1.1 Introduction 1 1.2 Operational

More information

AS DATA RATES increase, the variation in channel

AS DATA RATES increase, the variation in channel 80 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 1, JANUARY 2005 8-Gb/s Source-Synchronous I/O Link With Adaptive Receiver Equalization, Offset Cancellation, and Clock De-Skew James E. Jaussi, Member,

More information

6.976 High Speed Communication Circuits and Systems Lecture 21 MSK Modulation and Clock and Data Recovery Circuits

6.976 High Speed Communication Circuits and Systems Lecture 21 MSK Modulation and Clock and Data Recovery Circuits 6.976 High Speed Communication Circuits and Systems Lecture 21 MSK Modulation and Clock and Data Recovery Circuits Michael Perrott Massachusetts Institute of Technology Copyright 2003 by Michael H. Perrott

More information

A 10-Gb/s Multiphase Clock and Data Recovery Circuit with a Rotational Bang-Bang Phase Detector

A 10-Gb/s Multiphase Clock and Data Recovery Circuit with a Rotational Bang-Bang Phase Detector JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.3, JUNE, 2016 ISSN(Print) 1598-1657 http://dx.doi.org/10.5573/jsts.2016.16.3.287 ISSN(Online) 2233-4866 A 10-Gb/s Multiphase Clock and Data Recovery

More information

Real Time Jitter Analysis

Real Time Jitter Analysis Real Time Jitter Analysis Agenda ı Background on jitter measurements Definition Measurement types: parametric, graphical ı Jitter noise floor ı Statistical analysis of jitter Jitter structure Jitter PDF

More information

Lab 3.0. Pulse Shaping and Rayleigh Channel. Faculty of Information Engineering & Technology. The Communications Department

Lab 3.0. Pulse Shaping and Rayleigh Channel. Faculty of Information Engineering & Technology. The Communications Department Faculty of Information Engineering & Technology The Communications Department Course: Advanced Communication Lab [COMM 1005] Lab 3.0 Pulse Shaping and Rayleigh Channel 1 TABLE OF CONTENTS 2 Summary...

More information

SINCE the performance of personal computers (PCs) has

SINCE the performance of personal computers (PCs) has 334 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 57, NO. 5, MAY 2010 Multi-Slot Main Memory System for Post DDR3 Jaejun Lee, Sungho Lee, and Sangwook Nam, Member, IEEE Abstract This

More information

Application Note AN-23 Copyright September, 2009

Application Note AN-23 Copyright September, 2009 Removing Jitter From Picosecond Pulse Measurements James R. Andrews, Ph.D, IEEE Fellow PSPL Founder and former President (retired) INTRODUCTION: Uncertainty is always present in every measurement. Uncertainties

More information

A Subsampling UWB Radio Architecture By Analytic Signaling

A Subsampling UWB Radio Architecture By Analytic Signaling EE209AS Spring 2011 Prof. Danijela Cabric Paper Presentation Presented by: Sina Basir-Kazeruni sinabk@ucla.edu A Subsampling UWB Radio Architecture By Analytic Signaling by Mike S. W. Chen and Robert W.

More information

A SIGNAL DRIVEN LARGE MOS-CAPACITOR CIRCUIT SIMULATOR

A SIGNAL DRIVEN LARGE MOS-CAPACITOR CIRCUIT SIMULATOR A SIGNAL DRIVEN LARGE MOS-CAPACITOR CIRCUIT SIMULATOR Janusz A. Starzyk and Ying-Wei Jan Electrical Engineering and Computer Science, Ohio University, Athens Ohio, 45701 A designated contact person Prof.

More information

Appendix. Harmonic Balance Simulator. Page 1

Appendix. Harmonic Balance Simulator. Page 1 Appendix Harmonic Balance Simulator Page 1 Harmonic Balance for Large Signal AC and S-parameter Simulation Harmonic Balance is a frequency domain analysis technique for simulating distortion in nonlinear

More information

Understanding Apparent Increasing Random Jitter with Increasing PRBS Test Pattern Lengths

Understanding Apparent Increasing Random Jitter with Increasing PRBS Test Pattern Lengths JANUARY 28-31, 2013 SANTA CLARA CONVENTION CENTER Understanding Apparent Increasing Random Jitter with Increasing PRBS Test Pattern Lengths 9-WP6 Dr. Martin Miller The Trend and the Concern The demand

More information

High-Performance Analog and RF Circuit Simulation using the Analog FastSPICE Platform at Columbia University. Columbia University

High-Performance Analog and RF Circuit Simulation using the Analog FastSPICE Platform at Columbia University. Columbia University High-Performance Analog and RF Circuit Simulation using the Analog FastSPICE Platform at Columbia University By: K. Tripurari, C. W. Hsu, J. Kuppambatti, B. Vigraham, P.R. Kinget Columbia University For

More information

PV-PPV: Parameter Variability Aware, Automatically Extracted, Nonlinear Time-Shifted Oscillator Macromodels

PV-PPV: Parameter Variability Aware, Automatically Extracted, Nonlinear Time-Shifted Oscillator Macromodels PV-PPV: Parameter Variability Aware, Automatically Extracted, Nonlinear Time-Shifted Oscillator Macromodels Zhichun Wang, Xiaolue Lai and Jaijeet Roychowdhury Dept of ECE, University of Minnesota, Twin

More information